Multi-Level Fault Simulation of Digital Systems on Decision Diagrams Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik Tallinn Technical University, Raja 15, 12618 Tallinn, Estonia {raiub, jaan, ieero, brik}@pld.ttu.ee Abstract A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation levels. The approach proposed allows to reduce time expenses in the comparison to traditional gate-level fault simulation approach.
1. Introduction Fault Simulators are used widely in electronic design. Test generation, fault diagnosis, test set compaction etc. can serve in testing as examples of application of faultfree/fault simulators. As is well known, the quality of Automatic Test Pattern Generation (ATPG) significantly relies on efficient fault simulation, especially in the case of simulation-based test generators [1]. In such means as Genetic Algorithm-based tools fault simulation performs even more important role [2]. Fault simulation has traditionally been performed at the gate-level with the stuck-at fault model. Usually these methods are timeconsuming. Hierarchical methods allow taking the advantage of high level information while simulating tests for gate-level faults. Binary Decision Diagrams (BDDs) are today commonly used for representing Boolean functions because of their efficiency in terms of time and space [3,4]. They have become the state-of-the–art data structure in many VLSI CAD systems. On the other hand, there have been also several approaches to broaden the use of Decision Diagrams (DD) for representing digital systems at higher level presentations. Decision Diagrams have been successfully introduced as a uniform mathematical model of the system behavior for the different domains of application in the design process: for system verification by simulation, test generation and fault simulation [5-7]. It has been shown that the performance of the simulation of a system represented by DDs is higher than the simulation on the hardware description language model [7].
In this paper, we present a new hierarchical fault simulation approach based on a uniform DD model for the higher RT-level and lower gate-level representations. Faults are analysed on low-level and fault propagation is carried out on high-level. In such a way the efficiency of high-level calculation is combined with the accuracy of low-level fault analysis. The paper is organized as follows: Section 2 gives a general description of the method. Section 3 introduces the system representation by means of DDs. Section 4 describes the idea of the fault simulation on high-level DDs, Section 5 discusses fault similation on low-level DDs, and Secton 6 presents experimental data. In Section 7 some concluding remarks are given.
2. Description of the method The fault analysis of the system for the given test is carried out for the blocks of the higher level network block by block. At each iteration, a target block is chosen and represented on the gate level wheras all other blocks are represented on the RT level. Set of patterns with faults P; P1(R1)…Pm( Rm)
Set of patterns With faults P; P1(R1)…Pn( Rn)
C High-Level component
P: Pattern High-Level component
B
R
A High-Level component
Sequence of patterns
Set of patterns with faults P; P1(R1)…Pn( Rn)
P: First Pattern
Fig.1. Multi-level fault simulation
Always when the target block is simulated, the faults of the block are determined which cause erroneous output
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behaviour of the block at the given input pattern and given state of the target block. The propagation of detected faults of the target block is analysed by using the RTL description. Example 1. An example of the approach is illustrated in Fig.1 where the network of the system consists of three blocks: A,B, and C. The block B is taken here as the target block for fault analysis, and is represented on the gate level. Test sequence is simulated for the whole system on the higher level, pattern by pattern. When the target block B is reached by the first input pattern P, low level fault analysis in B is carried out, and the subset of all faults R activated in B by the pattern P at the given state of B is calculated. For each fault r ∈ R, the corresponding faulty output pattern P(r) of the block B is calculated. Activated faults are grouped into subsets Ri ⊆ R, so that for each r ∈ Ri the output pattern P(r) would be the same. The fault-free pattern P, and all the faulty patterns P1, …,Pk are simulated through other blocks of the network on the higher level. If Pi ≠ P at the observable output then the faults Ri are claimed as detected. The detected faults can be removed from further analysis. In general, at the output of each higher level block, a data structure (complex test pattern) D = {P, (P1,R1), …, (Pk,Rk)} will be generated where R1 ∪ R2 ∪ …∪ Rk ⊆ R. When the target block B is reached by a complex pattern D, all the patterns in {P,P1, …,Pk} should be fault simulated on the lowP20 P21 P22 P23 P24 P25
Target block under fault analysis
1010 1100 0110 1011 1110 0010
R21 R22 R23 R24 R25
level. For P, new faults will be determined which are activated by P, and for all the faults in each Ri it will be checked if they are propagated by the pattern Pi again through B or not. After that, a new data structure D will be created for the output of B. Consider a block with a function of n arguments y = f(x1, … xn) (xi is either input or a state variable), and a set of complex patterns Di = {Pi,0, (Pi,1,Ri,1), …, (Pi,ki,Ri,ki)}, i = 1,2, …, n where Pi,0 is the fault-free pattern on the input xi, and Pi,j are the possible faulty patterns on the same input for the cases of faults in Ri,j , j=1,2,… ki. Denote by
Ri = Ri ,1 ∪ Ri , 2 ∪ ... ∪ Ri ,ki ⊆ R the set of faults propagated to the input xi, where R is the whole set of faults in the system to be simulated. Procedure 1. To fault simulate a high-level block for a complex pattern D = (D1,…, Dn), first, the correct behaviour of the block for the pattern (P1,0,…,Pn,0) is calculated on the high-level. Then, for all the faults
r ∈ R’=
∅ 2,4,9 1,3 6,10 5,8 7,11,12
P30 P31 P32 P33 P34 P35
3
2 P10 P11 P12
1100 0010 1001
∅ R11 3 R12 2,4,8
)⊆R
To be fault simulated To be simulated at given faults
0100 1000 1100 0110 1100 0100
R31 R32 R33 R34 R35
∅ 2,4,9 1,3 6,10 5,8 7,11,12
High-level fault propagation
Registerlevel block
Gatelevel block
ij
j =1, ki
propagated to the block, all the possible combinations of patterns (P1(r),…,Pn(r)) where for each i = 1, …, n either Pi(r) = Pi,0 if r ∉ Ri, or Pi(r)= Pij if r ∈ Rij, are simulated on high-level.
Low-level fault simulation
1
U(U R
i =1, n
P30 P31 P32 P33
0100 1000 1100 0110
R31 R32 R33
∅ 2,4,9 1,3,5,8 6,10
Updated complex pattern
Fig.2. Fault propagation in the multi-level fault simulation
Procedure 2. To fault simulate the target low-level block for a complex pattern D = (D1,…, Dn), first, the correct behaviour of the block for the pattern (P1,…,Pn) is calculated, and the faults causing erroneous output behaviour of the block at this pattern are determined. Then, for all the faults r ∈ R’ in the complex pattern D which have propagated back to the same target block, all
the possible combinations of patterns (P1(r), …,Pn(r)) are simulated in the presence of the given fault r. Example 2. An example of the fault propagation in multi-level fault simulation is presented on Fig.2. Assume the input 1 of the target block represented on gate-level is reached by a complex test pattern D1 = {P10, (P11,R11), (P12,R12)} = {1100, 0010(3), 1001(2,4,8)}. The faults 2,3,4,8 of the block have been propagated through the
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simulated feedback loop back to the same block. By the fault analysis we find that 12 faults are detected by the current input pattern P10 = 1100 (or propagated by faulty patterns 0010 and 1001) on the output of the target block. They cause 5 different output patterns which differ from the expected one 1010. All the 6 output patterns are simulated now on high-level for the next block. From P30=P35 we conclude that the faults 7,11 and 12 are selfmasked – the pair (P35,R35) is removed from further simulation. From P32=P34 we conclude that the faults 1,3 and 5,8 can not be distinguished, and we include them into the same group of faults R32 = {1,3,5,8}. For fault analysis of the target block on the lower level and fault propagation through other blocks on the higher level we use the same mathematical model of decision diagrams. To increase the speed of low-level fault analysis, we use macro networks instead of gate networks where each macro is represented by a SSBDD. For fault propagation through other blocks we use word-level DDs.
Each function fk (Zk) ∈ F of the system S = (Z, F) is represented by a decision diagram Gk : zk = Gk (Zk), zk ∈Z, Zk ⊆ Z [4, 5]. Data Path
M A B C MUX1 MUX2 COND
ADR
z1 z
CC
z2
y
x
Control Path
δ/λ q′
q
FF
3. High-level decision diagrams
Begin s0
Consider a digital system S = (Z, F) as a network of components where Z is the set of variables (Boolean, Boolean vectors or integers), which represent connections between components, inputs and outputs of the network. Denote by X ⊂ Z and Y ⊂ Z, correspondingly, the subsets of input and output variables. V(z) denotes the set of possible values for z ∈ Z, which are finite. Let F be the set of digital functions on Z: zk = fk (zk,1, zk,2, ... , zk,p) = fk (Zk ) where zk ∈ Z, fk ∈ F, and Zk ⊂ Z. Some of the functions fk ∈ F, for the state variables z ∈ ZSTATE ⊂ Z, are next state functions. Definition 1. A decision diagram (denoted as DD) is a directed acyclic graph Gk = (M, Γ, z) where M is a set of nodes, Γ is a relation in M, and Γ(m) ⊂ M denotes the set of successor nodes of m ∈ M. The nodes m ∈ M are marked by labels z(m). The labels can be ether variables z ∈ Z, or algebraic expressions of z ∈ Z, or constants. For non-terminal nodes m, where Γ(m) ≠ ∅, an onto function exists between the values of z(m) and the successors me ∈ Γ(m) of m. By me we denote the successor of m for the value z(m) = e. The edge (m, me) which connects nodes m and me is called activated iff there exists an assignment z(m) = e. Activated edges, which connect mi and mj make up an activated path l(mi, mj). An activated path l(m0, mT) from the initial node m0 to a terminal node mT is called full activated path. Definition 2. A decision diagram Gk represents a function zk = fk (zk,1, zk,2, …, zk,p) = fk (Zk) iff for each value v(Zk) = v(zk,1) × v(zk,2) × ... × v(zk,p), a full path in Gk to a terminal node mT in Gk is activated, so that zk = z(mT) is valid.
A=B+C 0 A= s4
0
xC
1
0
xB
C =¬ C
B=¬B 0
B=B+C
A+1 xA
1
A=A+ B
s1
1
xA
s2
1 C =¬C
0 C=A+B
xC
1
s3
A = ¬C + B s5
END
Fig.3. A digital system and its behavior Example 3. In Fig.3 a digital system S = (Z,F) where Z = {A,B,C, q,x,y,z,z1,z2} and its behavior is represented. The FSM of the control part is given by the output function y = λ (q’, x) and the next-state function q = δ (q’, x), where x = (xA, xC) is a Boolean input vector variable. The value j of the state variable q corresponds to the state sj of the FSM. The apostrophe refers to the value of the previous state. The data path consists of the memory M with 3 registers A, B, C together with the addressing block ADR, represented by 3 DDs: A = GA (y, z), B = GB (y, z), C = GC (y, z); of the data manipulation block CC where z = Gz (y, z1 , z2 ); and of two multiplexers z1 = Gz,1 (y, M) and z2 = Gz,2 (y, M). The block COND calculates the condition function x = Gx (A, C). The component level DD-model of the
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system consists of the following set of DDs G:={Gq ,Gy ,GA ,GB ,GC ,Gz ,Gz,1 ,Gz,2 , Gx }. Using the following chain of graph superpositions: A = GA (y, z) = GA (y,Gz ( z1 , z2 )) = = GA (y,Gz(Gz,1(M), Gz,2(M))) = GA (y, M) = = GA (Gy (q’, x), M) = G’A (q’, A, B, C) we can create a new compact DD model G’A for representing the behaviour of register A. In similar way, we can compress the whole DD-model, and obtain the following set of DDs: G’={Gq ,G’A ,G’B ,G’C ,Gx } (Fig.4). For simplicity, in Fig.4 we have omitted the branches of nodes which enter the terminal node with label A’. A
q′
0 1 3 4
B
q′
1 4
C
q′
2 3 4
q
0
q′ 1
2 3,4
B′ + C′ 0 xA A′ + 1 1 xC ¬C′ + B′ 0 0 xC xA A′ + B′ xA xA
1 0
B′ + C′ ¬B′
0 xB A′ + B′ 1 0 xC xA
1
¬C′
#1 xA
xB 1
0
#4
1
#2
0
#5 #3
Fig. 4. High Level Decision Diagrams for the system in Figure 1
Procedure 3. Simulation on DDs is carried out by tracing the activated paths on DDs in accordance to the given values of variables as specified in Definition 1. For example, at the given input (state) pattern P = {q’=1, xA =0} of the block A we reach the terminal node mT of the graph GA with label A′ + 1 (see the highlighted path in Fig.4). The new value of A will be A = A′ + 1.
4. Fault-propagation on high-level DDs In high-level fault propagation in the digital system S=(Z,F) through a block with function z = f (z1, z2, …, zn)= f(Z’), Z’⊆ Z, which is represented by decision diagram Gz, we proceed from the fact that the faults may have been propagated to all of the variables zi ∈ Z’ used in labels of nodes in the graph. To each node m of the DD with the label z(m), a complex pattern
Dz(m) = {Pz(m),0, (Pz(m),1,Rz(m),1), …, (Pz(m),kz,Rz(m),kz)} corresponds. From this pattern, it results that a set of faults Rz(m)= Rz(m),1 ∪ …∪ Rz(m),k has been propagated to the node m. Consider the fault simulation on the decision diagram Gz as the following set of procedures. Procedure 4. First, the fault-free path is simulated in accordance to Procedure 3, and the fault-free value of z=z(mT,0) is calculated, where mT,0 is the terminal node of the fault-free activated path. Denote the set of all nodes traced in the fault-free path up to the node m (m itself not included) by MFF(m). Let RFF (m) be the set of all faults propagated to the nodes m∈MFF(m). The condition of reaching the node m in the fault-free path during fault simulation is the absence of all the faults in RFF (m). Denote by RCF(m) the set of faults consistent to the current faulty path from the initial node m0 up to the node m. For the nodes m on the fault-free path we have RCF(m) = R - RFF (m). Denote by L the list of all nodes of the DD to be fault simulated. All the nodes on the fault-free path are included into L. For carrying out fault simulation of the nodes in L, either Procedure 4 or Procedure 5 will be used. As the result of the procedure the list L will be updated. Fault simulation is terminated when the list L gets empty. Procedure 5. Fault simulation of a terminal node mT,0∈L with the function z = z(mT,0) = f(z1,…, zp) for the complex pattern D = (D1,…, Dp), Di = {Pi,0, (Pi,1,R’i,1), …, (Pi,ki,R’i,ki)}, i = 1,2, …, p, where
∀ i,j: R’i,j = (Ri,j - RFF (mT,0)) ∩ RCF(m) is equivalent to Procedure 1 of high-level fault simulation of a block discussed in Section 2. Procedure 6. Fault simulation of a nonterminal node m∈L with the variable z(m) for the complex pattern Dz(m) = {Pz(m),0, (Pz(m),1,R’z(m),1), …, (Pz(m),km,R’z(m),km)} where ∀ j: R’z(m),j = (Rz(m),j - RFF (m)) ∩ RCF(m), consists in the following: a) if m belongs to the fault-free path, and if R´z(m) = R’z(m),1 ∪ …∪ R’z(m),km =∅ no nodes will be included into L; b) if m does not belong to the fault-free path, and if R´z(m) =∅, the node me where e = Pz(m),0, will be included into L; for the new node me in L we calculate: RFF(me) = RFF(m) ∪ Rz(me), RCF(me) = RCF(m),
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if R´z(m) ≠∅, all the nodes me, where e = Pz(m),i, i: R’z(m),i ≠∅, will be included into L; for all these nodes we calculate RCF(me) = RCF(m) ∩ R’z(m),i, RFF(me) = RFF(m). As the result of fault simulation by Procedures 6 and 7 we get a complex pattern for the graph variable z: Dz = {Pz,0, (Pz,1,Rz,1), …, (Pz,kz,Rz,kz)}. All the pairs (Pz,i,Rz,i) where Pz,i = Pz,0 are eliminated since the faults Rz,i have self-masked at this point. All the groups of pairs {(Pz,i,Rz,i), (Pz,j,Rz,j)} where Pz,i = Pz,j are merged into a single pair (Pz,i,Rz,i) where Rz,i = Rz,i ∪ Rz,j. c)
1 (1,2,3,4,5) q’
0 (1,2,3,4,5) xA
A’+1
1
8 (∅) 9 (8) 5 (9)
0 (1,2,5) B’+C’
5. Fault simulation on low-level DDs
2 3
8(∅) + 1(1) = 9(1) 6(2) + 2(2) = 8(2) 3(5) + 4(∅) = 7(5)
4 (3,4)
0 (4) xA
1 xC
1 (3) A’ 7 (3)
node xA: R’xA = (RxA - RFF (xA)) = ∅. From all the faults propagated to A’, only the faults 8 and 9 are simulated in A’+1; for other faults other paths are simulated starting from the node q’. In the terminal node B’+C’ only the faults 1,2,5 are simulated, since only they are consistent to the condition of leaving the node q’at this direction. After fault simulation of all 4 terminal nodes reached at the given complex pattern we compose the whole result as follows: the fault 2 propagated to the node B’+C’ is self-masked because the value B’+C’=8 calculated for the fault 2 is equal to the fault-free value calculated at the node A’+1. The faults 3,4 and 5 propagated to different nodes in DD are merged into the same group because it produces the same new value 7 for A. Also the faults 1 and 8 are merged into the same group. The final value of the new complex pattern for A is: DA = {8, 5(9), 7 (3,4,5), 9 (1,8)}.
0 (4) A’
7 (4)
Fig. 5. Fault simulation on the graph GA on Fig.4
Example 4. Consider the DD GA in Fig.4 with a set of complex patterns: Dq = {1, 0 (1,2,5), 4 (3,4)}, DxA = {0, 1 (3,5)}, DxC = {1, 0 (4,6)}, DA = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, DB = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, DC = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. All the paths traced during fault simulation are depicted in Fig.5. The fault free paths are shown by bold lines in Fig.4 and Fig.5. The edges on paths are labelled by pairs (e,R) where e is the value of the node variable when leaving the node at the given direction, and R is the subset of faults RFF(m) for the next node m on the fault-free path, and the subset of faults RCF(m) for the next node m on the faulty paths. Since RFF(xA) = {1,2,3,4,5,6} includes all the faults propagated to xA, no faulty paths are simulated from the
Low-level binary decision diagrams are used for fault simulation of target blocks. We use here stucturally synthesized BDDs (SSBDD) [8] which allow easily to represent gate-level faults by node faults on SSBDDs. By superposition of SSBDDs [8] we can generate a macrolevel network from the given gate-level circuit which allows significally to increase the speed of simulation. Using DDs at both lower and higher levels we can implement uniform path tracing algorithms for fault simulation and fault propagation. Consider now the fault simulation of the DD Gz representing a binary function z = f(z1, z2, …, zp) = f(Z’), Z’⊆ Z at the given complex pattern D = {P0, (P1,R1), …, (Pn,Rn)} as the following set of procedures. First, the fault-free path is simulated for the fault-free pattern P0 in accordance to Procedure 4, and the fault-free value of z =z(mT,0) is calculated, where mT,0 is the terminal node reached by graph tracing (in case of BDDs z(mT,0)∈{0,1}). Denote the set of all nodes traced in the fault-free path except the terminal node mT,0 by MFF. Procedure 7. For all the nodes m ∈ MFF fault simulation is carried out: the value of z(m)=e is inverted, and a new path starting from the node m for this inverted value is traced. If the same terminal node mT,0 is reached the fault z(m)≡e is not detected, otherwise it is detected Procedure 8. Next, the faulty patterns Pi , i = 1,…,n for all the faults r ∈ R1 ∪ … ∪ Rn, are simulated. For each fault r∈Ri, first, the fault is injected then a fault free simulation for the pattern Ri is carried out. Assume, a terminal node mT,r is reached. If z(mT,r)≠ z(mT,0) the fault r remains in the list of propagated faults, otherwise it is removed.
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6. Experimental results In Table 1, the gain in speed for low level fault analysis of SSBDD macros compared to the gate-level fault simulation is demonstrated. For the experiments, ISCAS’85 benchmark circuits were used. The speed of fault simulation on the macro-network was found from 2.55 to 9.04 times (in average 5.98 times) higher than the speed of fault simulation on the gate-network. Table 1. Low-level fault simulation efficiency ISCAS
Gates
C432 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552
232 383 546 880 1193 1669 2307 2416 2978
Fault cover % 97.33 100.00 99.64 99.75 99.67 95.58 99.78 99.80 99.46
Number of test patterns 55 100 52 122 119 145 108 33 198
Fault sim. Macro/gate speed ratio 3.86 5.15 3.08 6.46 6.47 8.81 8.37 2.55 9.04
simulation was found from 2.69 to 121 times (in average 35.1 times) higher than the speed of fault simulation on the plain gate-network. The characteristics of the benchmark circuits are depicted in Table 3.
7. Conclusions We introduced a multi-level fault simulation method for digital systems. We have used decision diagrams as a mathematical model for systematic multi-level solution for fault simulation. Two levels were used: RT and gate levels. Using DDs as a uniform model for both lower and higher level representations we can work with uniform path tracing algorithms for fault simulation and fault propagation. Faults are analysed on low-level and fault propagation is carried out on high-level. In such a way the efficiency of high-level calculation is combined with the accuracy of low-level fault analysis.The method proposed reduces dramatically the computation cost of fault grading in digital systems.
8. Acknowledgements
Table 2. Hierarchical fault simulation results FSM Test length Fault circuit cover % bbsse 300 74.1 dk16 150 95.1 ex2 600 25.9 ex3 1000 46.2 log 200 99.6 s832 300 59.6 s1488 400 63.48 sand 400 84.2 styr 500 74.1
Time, sec HSIM 0.01 0.01 0.01 0.01 0.01 1.00 2.00 1.00 2.00
GSIM 0.38 0.55 1.21 0.77 0.11 2.69 9.17 3.18 6.81
Table 3. Benchmark circuits for hierarchical simulation FSM bbsse dk16 ex2 ex3 log s832 s1488 sand scf styr
States 16 27 20 10 17 25 48 32 121 30
Inp 7 2 2 2 9 18 8 11 27 9
Out 7 3 2 2 24 19 19 9 56 10
Tran 56 108 73 37 29 245 251 184 166 166
Cells 80 156 77 38 76 162 332 259 428 262
Flts 562 1038 480 274 486 1090 2234 1622 2800 1734
In Table 2 the results of multi-level simulation for FSM benchmark circuits are used for evaluating the proposed multi-level approach. A hierarchical multi-level fault simulator (HSIM) is compared to the plain gate-level simulator (GSIM). The speed of multi-level fault
This work has been supported by the Estonian Science Foundation grants G3658 and G4300.
9. References [1] R Guo, I. Pomeranz and al., “A Fault Simulation Based Test pattern Generator for Sequential Circuits”. 17th IEEE VLSI Symposium, California, April 25-29, 1999, [2] D.Krishnaswamy, M. S. Hsiao and al. “Parallel Genetic Algorithms for Simulation-Based Sequential Circuit test Generation”. IEEE VLSI Design Conference, 1997. pp. 475-481 [3] S.Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Acad. Publishers, 1996, 141 p. [4] R.Drechsler, B.Becker. BDDs. Theory and Implementation. Kluwer Academic Publishers, 1998, 200 p. [5] R.Ubar. Vektorielle Alternative Graphen für digitale Systeme. Nachrichtentechnik/ Elektronik, (31) 1981, H.1, pp.25-29. [6] R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59. [7] R.Ubar, A.Morawiec, J.Raik. Cycle-based Simulation with Decision Diagrams. DATE, Munich, 1999, pp.454458. [8] R.Ubar. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams. OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic, Vol.4, pp. 141-157, 1998.
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