Notes On Pulse Signaling
Notes On Pulse Signaling Jo Ebergen, Steve Furber, Arash Saifhashemi, Naela Nissar, Alex Chow VLSI Research Group Sun Microsystems Laboratories SML 2007-0082
Introduction • Most common signaling techniques > Level signaling > Transition signaling > Single-track signaling
• Let’s look at pulse signaling
> Do simple implementations exist? > How robust are these circuits? > How efficient are these circuits in terms of
delay, energy, and area?
SML2007-0082
2
Signaling Protocols • Level signaling req ack
one cycle
req ack
• Transition signaling req ack
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one cycle
one cycle
req ack
3
More Signaling Protocols • Single-track signaling one cycle req ack req+ack
• Pulse signaling one cycle
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req
req
ack
ack
4
An Example of a Pulse Module • The Pulse Repeater
b a
p
b
a
K
weak K
= weak
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5
Variations • Larger pulse width • Guard against too long input pulse b a
p
b
a
K
• Negative pulse implementation a
p
b
a b K
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Pulse Merge • The ‘OR’ for events
a b
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pM
K
c
c a
b
7
Pulse Join • The ‘AND’ for events a K
a b
pJ
c
c
b K
• An incorrect implementation c a
K
b
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A Better Pulse Join? • Negative-pulse implementation
a a b
pJ
c K c b
K
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2-by-1 Pulse Join • Also known as 2-by-1 Decision-Wait • (a0 AND c produces b0) OR (a1 AND c produces b1)
c
c a0
K
b0 pJ
a1
b0
b1 a0
K
b1 a1
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K
10
A Better Implementation c
K
c a0
b0 b0
pJ
a1
b1
a0
K
b1 a1
K
• Is negative pulse implementation even better? SML2007-0082
11
Properties of Pulse Modules • • • •
Self-reset produces fixed-width pulse Pulse module restores ‘poor’ pulses (Nyström) Output always strongly driven Condition: Cycle time > 2x Pulse Width
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12
A Comparison • • • • •
Compare level signaling with pulse signaling Application: a pipeline Estimate energy (area) as a function of cycle time Analysis based on Logical Effort 180nm CMOS TSMC technology
SML2007-0082
13
Pipeline with Level Signaling • Four-phase, level signaling (as in CHAIN) • Cycle Time: 2x5 = 10 ‘gate delays’ 500!m
req (1-out-of-4)
C
C
C
C
C
C
C
C 100!m
100!m
500!m
ack SML2007-0082
14
Pipeline with Pulse Signaling • Positive or negative pulse implementation • Cycle time: 6 ‘gate delays’ 500!m
req
pJ
pJ
(1-out-of-4) 100!m
100!m pM
pM 500!m
ack SML2007-0082
15
Energy vs Cycle Time Energy vs. Cycle Time 8000 Level Signaling
Energy Consumption per Stage [ε]
Positive Pulse Signaling 7000
Negative Pulse Signaling
6000
5000
4000
3000
2000
1000
0
40
50
60
70
80
90
100
Cycle Time [τ]
τ = 14.5ps, ε = 2.8fJ
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Robustness Issues • Long wires deteriorate pulses
> What wire length deteriorates pulses beyond detection? Rw ,Cw p
p
• Capacitive coupling deteriorates pulses
> Can we quantify effect of coupling on pulses? victim p
p
p
p aggressor
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17
Max Wire Length vs Pulse Width Rw ,Cw
Rw ,Cw
p
p
Maximum Wire Length vs. Pulse Width Maximum Wire Length (mm)
3 2.75 2.5 2.25 2 1.75
Stepup = 3
1.5
Stepup = 4
1.25
Stepup = 5
1
Stepup = 6
0.75 0.5 0.25 0
0
50
100
150
200
250
300
350
400
Pulse Width (ps) SML2007-0082
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Effect of Capacitive Coupling victim p
p
p
p aggressor
320 310
Pulse width (ps)
300 290 280 270 260
L = 0.5mm L = 1.0mm L = 2.0mm Without crosstalk
250 240
−100
−50
0
50
100
Normalized timing offset between aggressor and pulse (ps) SML2007-0082
19
Summary • Pulse signaling is an attractive signaling protocol • Simple implementation templates exist • Pulse signaling compares favorably with level signaling wrt energy-vs-delay performance • Pulse signaling offers good robustness > Deals gracefully with long wires > Deals gracefully with capacitive coupling
• Negative pulse implementations are better than positive pulse implementations SML2007-0082
20
Concluding Remarks • • • • •
More research needed Influence of other noise sources? Effect of device variations? Effect of threshold voltage variations? Need to build and test chips
SML2007-0082
21
Thank you!
Jo Ebergen [email protected]
22
Introduction • Most common signaling techniques > Level signaling > Transition signaling > Single-track signaling
• Let’s look at pulse signaling
> Do simple implementations exist? > How robust are these circuits? > How efficient are these circuits in terms of
delay, energy, and area?
SML2007-0082
2
Signaling Protocols • Level signaling req ack
one cycle
req ack
• Transition signaling req ack
SML2007-0082
one cycle
one cycle
req ack
3
More Signaling Protocols • Single-track signaling one cycle req ack req+ack
• Pulse signaling one cycle
SML2007-0082
req
req
ack
ack
4
An Example of a Pulse Module • The Pulse Repeater
b a
p
b
a
K
weak K
= weak
SML2007-0082
5
Variations • Larger pulse width • Guard against too long input pulse b a
p
b
a
K
• Negative pulse implementation a
p
b
a b K
SML2007-0082
6
Pulse Merge • The ‘OR’ for events
a b
SML2007-0082
pM
K
c
c a
b
7
Pulse Join • The ‘AND’ for events a K
a b
pJ
c
c
b K
• An incorrect implementation c a
K
b
SML2007-0082
8
A Better Pulse Join? • Negative-pulse implementation
a a b
pJ
c K c b
K
SML2007-0082
9
2-by-1 Pulse Join • Also known as 2-by-1 Decision-Wait • (a0 AND c produces b0) OR (a1 AND c produces b1)
c
c a0
K
b0 pJ
a1
b0
b1 a0
K
b1 a1
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K
10
A Better Implementation c
K
c a0
b0 b0
pJ
a1
b1
a0
K
b1 a1
K
• Is negative pulse implementation even better? SML2007-0082
11
Properties of Pulse Modules • • • •
Self-reset produces fixed-width pulse Pulse module restores ‘poor’ pulses (Nyström) Output always strongly driven Condition: Cycle time > 2x Pulse Width
SML2007-0082
12
A Comparison • • • • •
Compare level signaling with pulse signaling Application: a pipeline Estimate energy (area) as a function of cycle time Analysis based on Logical Effort 180nm CMOS TSMC technology
SML2007-0082
13
Pipeline with Level Signaling • Four-phase, level signaling (as in CHAIN) • Cycle Time: 2x5 = 10 ‘gate delays’ 500!m
req (1-out-of-4)
C
C
C
C
C
C
C
C 100!m
100!m
500!m
ack SML2007-0082
14
Pipeline with Pulse Signaling • Positive or negative pulse implementation • Cycle time: 6 ‘gate delays’ 500!m
req
pJ
pJ
(1-out-of-4) 100!m
100!m pM
pM 500!m
ack SML2007-0082
15
Energy vs Cycle Time Energy vs. Cycle Time 8000 Level Signaling
Energy Consumption per Stage [ε]
Positive Pulse Signaling 7000
Negative Pulse Signaling
6000
5000
4000
3000
2000
1000
0
40
50
60
70
80
90
100
Cycle Time [τ]
τ = 14.5ps, ε = 2.8fJ
SML2007-0082
16
Robustness Issues • Long wires deteriorate pulses
> What wire length deteriorates pulses beyond detection? Rw ,Cw p
p
• Capacitive coupling deteriorates pulses
> Can we quantify effect of coupling on pulses? victim p
p
p
p aggressor
SML2007-0082
17
Max Wire Length vs Pulse Width Rw ,Cw
Rw ,Cw
p
p
Maximum Wire Length vs. Pulse Width Maximum Wire Length (mm)
3 2.75 2.5 2.25 2 1.75
Stepup = 3
1.5
Stepup = 4
1.25
Stepup = 5
1
Stepup = 6
0.75 0.5 0.25 0
0
50
100
150
200
250
300
350
400
Pulse Width (ps) SML2007-0082
18
Effect of Capacitive Coupling victim p
p
p
p aggressor
320 310
Pulse width (ps)
300 290 280 270 260
L = 0.5mm L = 1.0mm L = 2.0mm Without crosstalk
250 240
−100
−50
0
50
100
Normalized timing offset between aggressor and pulse (ps) SML2007-0082
19
Summary • Pulse signaling is an attractive signaling protocol • Simple implementation templates exist • Pulse signaling compares favorably with level signaling wrt energy-vs-delay performance • Pulse signaling offers good robustness > Deals gracefully with long wires > Deals gracefully with capacitive coupling
• Negative pulse implementations are better than positive pulse implementations SML2007-0082
20
Concluding Remarks • • • • •
More research needed Influence of other noise sources? Effect of device variations? Effect of threshold voltage variations? Need to build and test chips
SML2007-0082
21
Thank you!
Jo Ebergen [email protected]
22
