Novel Topologies for Symmetric, Asymmetric, and Cascade Switched ...
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Novel Topologies for Symmetric, Asymmetric, and Cascade Switched-Diode Multilevel Converter With Minimum Number of Power Electronic Components Rasoul Shalchi Alishah, Daryoosh Nazarpour, Seyed Hossein Hosseini, Member, IEEE, and Mehran Sabahi, Member, IEEE
Abstract—In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation. Index Terms—Asymmetric, bidirectional switch, cascade, fullbridge converter, multilevel converter, symmetric.
I. I NTRODUCTION
M
ULTILEVEL power conversion was first presented over 30 years ago [1]. Multilevel converters can produce a large number of output voltage levels, which results in high voltage capability, lower harmonic contents, lower switching losses, better electromagnetic compatibility, and high power quality. Multilevel converters have been used for several applications such as static reactive power compensation, adjustablespeed drives, renewable energy sources, and so on [2]–[4]. The principal function of multilevel converter is to synthesize
Manuscript received May 8, 2013; revised August 21, 2013; accepted November 14, 2013. Date of publication January 2, 2014; date of current version May 2, 2014. R. Shalchi Alishah and D. Nazarpour are with the Faculty of Electrical and Computer Engineering, Urmia University, Urmia 51747, Iran (e-mail: Rasoul. [email protected]; [email protected]). S. H. Hosseini and M. Sabahi are with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51666, Iran (e-mail: hosseini@ tabrizu.ac.ir; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2013.2297300
a desired ac voltage from several separate dc sources [5], [6]. Many kinds of topologies for multilevel converters have been proposed. In general, there are three types of multilevel converters: 1) Neutral Point Clamped (NPC) converter [7], [8]; 2) Flying Capacitor (FC) converter [9], [10]; and 3) Cascade H-bridge (CHB) converter [11], [12]. The unequal voltage sharing among series connected capacitors is the main drawback of NPC converter. In addition, this structure needs a large number of clamping diode for higher levels. The FC converter requires a great number of storage capacitors for higher output voltage levels and the capacitors voltage balancing is difficult. Conventional cascade multilevel converter is one of the most important topologies in the family of conventional multilevel converters because cascade converter requires the least number of components, when compared with the flying capacitor and diode clamped converter [13], [14]. A cascade multilevel converter consists of the number of H-bridge converter units with separate dc sources for each unit, which connected in cascade or series [15]. In symmetric cascaded multilevel converter, dc voltage sources values of similar cells are equal. For the same number of power devices, asymmetric cascade multilevel topology significantly increases the number of output voltage levels. In these topologies, the values of dc voltage sources of different cells are nonequal [16], [17]. However, the symmetric and asymmetric CHB converter requires a large number of switches and dc voltage sources. An attempt has been made in [18] to propose a new structure for multilevel converter with reduced number of power electronic components in comparison with conventional cascade converter. This converter needs a large number of bidirectional switches. In addition, the magnitude of blocked voltage by bidirectional switches is high. In [19], another new topology for cascade multilevel converter has been introduced, which reduces the number of bidirectional switches, power diodes, and dc voltage source in comparison with proposed topology in [18]. This topology consists of several submultilevel converters and full-bridge converters. But, this topology requires a large number of bidirectional switches and gate driver circuits. In this paper, new topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which have more advantages in comparison with presented topologies in [18], [19].
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SHALCHI ALISHAH et al.: SYMMETRIC, ASYMMETRIC, AND CASCADE SWITCHED-DIODE CONVERTER
Fig. 1.
Basic circuit of proposed switched-diode multilevel converter.
Fig. 2.
Proposed symmetric switched-diode multilevel converter topology.
Fig. 3. Comparison of conventional symmetric cascade topology with proposed symmetric switched-diode topology.
Fig. 4.
TABLE I S WITCH S TATES FOR S YMMETRICAL T OPOLOGY
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Proposed asymmetrical switched-diode multilevel converter topology.
the basic unit generates a staircase voltage waveform (Eo ) with positive polarity (E, 2E, 3E, . . . . . .). It is connected to a fullbridge converter, which particularly alternates the input voltage polarity and generates positive or negative staircase waveform (Eo ) at the output voltage (0, ±E, ±2E, ±3E, . . . . . .). The number of output levels (Nlevel ), IGBTs (NIGBT ), and the maximum output voltage (Eo,max ) in the proposed symmetric converter are obtained as follows, respectively: Nlevel = 2K + 1 NIGBT = K + 3 Eo,max = KE.
II. BASIC OF P ROPOSED M ULTILEVEL C ONVERTER T OPOLOGIES Fig. 1 shows the basic topology for proposed switched-diode multilevel converter. In this circuit, when the switch S is turned off, the current flows from the diode D and load voltage will be E. But, when the switch S is turned on, the diode is reverse biased and current flows from the voltage source E and load voltage will be (2E). By the use of this method, the load voltage is controlled. This method is the basic of proposed multilevel converter. The new presented structures in three different topologies are introduced and consist of: 1) symmetric switched-diode multilevel converter; 2) asymmetric switcheddiode multilevel converter; and 3) cascade switched-diode multilevel converter. III. P ROPOSED S YMMETRICAL S WITCHED -D IODE M ULTILEVEL C ONVERTER The structure of proposed symmetric switched-diode multilevel converter is shown in Fig. 2. In this structure, the values of the dc voltage sources are equal. Therefore, this topology is called symmetric switcheddiode multilevel converter. Table I gives the values of output voltages (Eo ) for different states of switches. In this topology,
(1) (2) (3)
Where K represents the number of dc voltage sources. Fig. 3 compares the number of IGBTs versus the number of output levels (Nlevel ) in the proposed symmetric switched-diode topology and the symmetric conventional cascade topology. This figure shows that the proposed converter requires the least number of IGBTs. IV. P ROPOSED A SYMMETRICAL S WITCHED -D IODE M ULTILEVEL C ONVERTER Asymmetrical multilevel converter provides an increased number of output voltage levels for the same number of power electronic devices than its symmetric counterpart. In [16], [17], for dc voltage sources of conventional cascade H-bridge topology, two main methods have been suggested, which have been called binary and trinary configuration. The trinary configuration can produce a great number of levels in comparison with binary configuration [17]. Fig. 4 shows the proposed topology for asymmetrical switched-diode converter, which consists of one basic unit and a full-bridge converter. Table II shows the ON switches look-up table for proposed asymmetric topology. In this topology, the values of dc sources are suggested to be chosen according to the following algorithm: E1 = E Ej = 2(j−1) E
For j = 2, 3, 4, . . . , Z.
(4) (5)
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TABLE II S WITCH S TATES FOR A SYMMETRICAL T OPOLOGY
Fig. 6. Voltage balancing of dc-link in recommended converter using (a) dc/dc converters and (b) multitap transformer.
Fig. 5. Comparison of proposed asymmetric switched-diode topology with trinary cascade topology in [17].
For this method, the number of levels and maximum output voltage are given by (6) and (7), respectively Nlevel = 2(Z+1) − 1 Eo,max = (2Z − 1)E
(6) (7)
where Z represents the number of dc sources. In the proposed asymmetric topology, the number of IGBTs is obtained by NIGBT = Z + 4.
(8)
Fig. 5 shows the comparison between proposed asymmetric switched-diode topology with trinary configuration of conventional cascade in [17]. This comparison shows that the proposed asymmetric switched-diode converter generates the maximum number of level with fewer numbers of switches. It is important to note that the proposed symmetric and asymmetric switched-diode topologies can be used in renewable energy sources and medium-voltage applications. However, this structures needs several dc voltage sources. For renewable energy source applications, instead of dc voltage sources, we can use photovoltaic panels. In this application, capacitor voltage balancing is important. For example, in fuel cells, the output voltages are changed during the converter performance and lead to reduction of the quality of output voltage in dc-link of converter. To solve this problem, as shown in Fig. 6(a), the voltage of each capacitor is controlled with one dc/dc converter. Fig. 6(b) illustrates another method for control of capacitor voltages of proposed converter for medium-voltage applications. This circuit consists of an ac voltage source, multitap transformer, and several rectifiers. The proposed symmetric and asymmetric switched-diode topologies use only one full-bridge
Fig. 7.
Proposed cascade switched-diode multilevel converter topology.
converter, which is a restriction for high-voltage applications. In addition, these topologies need more number of devices. V. P ROPOSED C ASCADE S WITCHED -D IODE M ULTILEVEL C ONVERTER To provide a large number of levels with less number of components, cascade switched-diode multilevel converters can be used. Fig. 7 shows the structure of proposed cascade multilevel converter. The output voltage of the proposed cascade switcheddiode multilevel converter is given by Eout = Eo1 + Eo2 + · · · + Eon .
(9)
For the proposed cascade topology, two methods for determination of values of the dc sources are presented.
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A. First Algorithm In this algorithm, the values of all of the dc voltage sources in each stage are the same. For stage 1, E1i = E1
i = 1, 2, 3, . . . , Z1 .
(10)
Therefore, the maximum output voltage of this stage (Eo1,max ) will be Eo1,max = Z1 × E1 .
(11)
For stage 2,
E2i = E2 = E1 + 2×Eo1,max = (2Z1 +1)×E1 i = 1, 2, . . . , Z2. (12)
In this stage, the maximum output voltage (Eo2,max ) will be Eo2,max = Z2 × E2 . For stage 3,
E3i =E3 = E1 + 2 × Eo2,max + 2 × Eo1,max =(2Z1 + 1) × (2Z2 + 1) × E1 i = 1, 2, 3, . . . , Z3 .
(13) 1Z+4
(14)
Fig. 8. Variation of (a) (2Z + 1)1/Z+4 and (2Z+1 − 1) . (b) (2Z + 1/Z . (c) Variation of (Z + 4)/ ln(2Z + 1) and 1)1/Z and (2Z+1 − 1) (Z + 4)/ ln(2Z+1 − 1). (d) Variation of (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) versus Z.
For the jth stage,
VI. O PTIMAL T OPOLOGIES
Eji = Ej = (2Z1 +1)×(2Z2 +1)×· · ·×(2Zj−1 +1)×E1 . (15) In this method, the number of output voltage levels (Nlevel,F ) can be determined by the following equation: Nlevel,F = Nlevel,stage1 ×Nlevel,stage.2 × · · · × Nlevel,stage.n = (2Z1 + 1) × (2Z2 + 1) × · · · × (2Zn + 1). (16) n
Zi × Ei1 .
In this structure for the jth stage, the dc voltage source magnitudes are given by (18) and (19) Ej1 = 2(Z1 +1) − 1 × 2(Z2 +1) − 1 × · · · × 2(Zj−1 +1) − 1 × E (18) Ej1
i = 2, 3, . . . , Zj .
n=
(19)
(24)
n
Nlevel,S = (2Z+1 − 1) .
(20)
= Nlevel,stage.1 ×Nlevel,stage.2 ×· · ·×Nlevel,stage.n = (2Z1 +1 − 1)×(2Z2 +1 − 1)×· · ·×(2Zn +1 − 1). (21)
The number of IGBTs in the proposed cascade topology is (22)
(25)
Using (24) and (25), it is obvious that
NIGBT Nlevel,F = (2Z + 1)1/Z+4
1/Z+4 NIGBT Nlevel,S = (2Z+1 − 1) .
(26)
Fig. 8(a) shows the variation of (2Z + 1)1/Z+4 and 1/Z+4 (2 − 1) versus Z. It is clear that the maximum number of levels for the first method is obtained for Z = 3. This means that a topology consisting of three dc sources in each stage can generate maximum output levels for Eo . For the second method, the maximum is obtained for Z = ∞. From theoretical point of view, this means that a topology consisting of one stage with available IGBTs is favorable for a constant number of IGBTs. It is important to note that the number of IGBTs and gate driver circuits is the same. Z+1
i=1 Nlevel,S
NIGBT = (Z1 + Z2 + Z3 + · · · + Zn ) + 4n.
NIGBT . Z +4
Nlevel,F = (2Z + 1)n
In this method, the maximum output voltages of converter (Eomax,S ) and the number of output voltage levels (Nlevel,S ) can be calculated as follows, respectively: Eomax,S n Z +1 (2 i − 1) ×Ei1 =
(23)
Now, the magnitude of Z must be determined. Using (16), (21), and (23), the maximum number of levels for two suggested methods is given by the following equations:
B. Second Algorithm
Eji = 2
Z1 = Z2 = Z3 = · · · = Zn = Z.
(17)
i=1
(i−1)
The product of the numbers (whose summation is constant) will be maximized, when the following relation is valid:
Using (22) and (23) can be written as follows:
In this method, the maximum output voltage (Eomax,F ) is Eomax,F =
A. Optimization of the Proposed Cascade Converter for Maximum Number of Levels With Constant Number of IGBTs
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B. Optimization of the Proposed Cascade Converter for Maximum Number of Levels With Constant Number of DC Sources Suppose that the proposed structure consists of a series of n stage converters. In this topology, the number of dc sources can be obtained Nsource = Z1 + Z2 + · · · + Zn .
(27)
Using (23), the number of dc sources is obtained by (28) Nsource = Z × n.
(28)
Considering (25), the maximum number of output voltage levels for two methods is given by
Nsource Nlevel,F = (2Z + 1)1/Z
1/Z Nsource Nlevel,S = (2Z+1 − 1) .
(29) 1/Z
Fig. 8(b) shows the variation of (2Z +1)1/Z and (2Z+1 −1) versus Z. It is evident that the maximum number of output voltage levels for two proposed methods is obtained for Z = 1. It is noticeable that the proposed structure is converted to a conventional cascade converter. C. Optimization of the Proposed Cascade Converter for Minimum Number of IGBTs With Constant Number of Levels If the number of IGBTs in each stage is assumed to be equal to z, then considering (26), the numbers of IGBTs (NIGBT ) for two algorithms are given by the following equations, respectively: NIGBT,F = (Z + 4) × n = ln(Nlevel ) × NIGBT,S = (Z +4) × n = ln(Nlevel ) ×
(Z +4) ln(2Z +1) (Z +4) . ln(2Z+1 −1)
(30)
Fig. 8(c) shows the variation of (Z + 4)/ ln(2Z + 1) and (Z + 4)/ ln(2Z+1 − 1) versus Z. It is evident that the minimum number of IGBTs to realize Nlevel values for the first method is given for Z = 3. For the second method, the minimum number of IGBTs is theoretically realizable for Z = ∞.
Ndiode,F = (2Z +4) × n = ln(Nlevel ) ×
(2Z +4) ln(2Z +1)
Ndiode,S = (2Z +4) × n = ln(Nlevel ) ×
(2Z +4) . (33) ln(2Z+1 −1)
Since Nlevel is constant, Ndiode will be minimized, when (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) tends to be minimum. Fig. 8(d) shows variation of (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) versus Z. It is clear that the minimum number of power diodes to realize Nlevel values for the first method is given for Z = 2. From theoretical point of view, for the second methods, the minimum number of power diodes is obtained for Z = ∞.
A. Comparison of the Required Number of IGBTs
It is important to note that the number of IGBTs and diodes are not equal. In this topology, the number of power diodes is given by following equation: (31)
Using (23), we have Ndiode = (2Z + 4) × n.
Considering (25) and (32), it is clear that we have
VII. C OMPARISON OF THE P ROPOSED C ASCADE S WITCHED -D IODE T OPOLOGY W ITH OTHER T OPOLOGIES
D. Optimization of the Proposed Cascade Converter for Minimum Number of Power Diodes With Constant Number of Levels
Ndiode = 2(Z1 + Z2 + Z3 + · · · + Zn ) + 4n.
Fig. 9. (a) Number of IGBTs against the number of levels in different topologies, (b) number of drivers against the number of levels in different topologies, (c) number of diodes against the number of levels in different topologies, (d) blocking voltages on switches in different topologies, and (e) number of dc sources against the number of levels in different topologies.
(32)
It is important to note that in the presented topologies in [18] and [19], bidirectional switches have been used that are composed of two IGBTs [20], [21]. Fig. 9(a) compares the number of IGBTs versus the number of levels for two methods of determination of dc voltage sources in the proposed topology and topologies presented in [18] and [19]. It is obvious that the second method of proposed topology requires less number of IGBTs to realize Nlevel for Eo .
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B. Comparison of the Required Gate Driver Circuits In [18] and [19], each bidirectional switch consists of two IGBTs and two antiparallel diodes. Also, each unidirectional switch used in full-bridge converter consists of an IGBT and an antiparallel diode. Each bidirectional and unidirectional switch of the converter needs only one gate driver circuit. The gate driver circuits are the electronic part of the circuit and increasing the number of gate driver circuits is a considerable deficiency. Because, increasing the number of gate drivers cause increasing costs and control complexity. Fig. 9(b) compares the number of gate driver circuits versus the number of levels in different topologies. This figure shows that the second method of proposed cascade topology needs fewer numbers of gate driver circuits. C. Comparison of the Required Power Diodes Fig. 9(c) compares the number of power diodes versus the number of levels in the two methods of proposed topology and the proposed topologies in [18] and [19]. As shown in this figure, the number of required power diodes in the first method of proposed topology and suggested topology in [19] are equal and the second method of proposed topology requires minimum number of power diodes.
Fig. 10. Fifteen-level converter as a sum of seven-stepped waveforms.
D. Comparison of the Blocking Voltages on Switches In a multilevel converter, the voltage and current ratings of the switches play important roles in the cost and realization of the multilevel converter. In all structures, the currents of all the switches are equal to the rated current of the load. However, this is not true for the voltage [18], [19]. A lower magnitude of the blocking voltage on switches shows that a smaller voltage is applied at the terminal of the switches of the topology, which is considered an advantage. Suppose that the maximum magnitude of the blocking voltage of switches (Eswitch ) is indicated by the following equation: Eswitch = Eswitch,F + Eswitch,U .
(34)
In this equation, Eswitch,F and Eswitch,U represent the maximum voltage of the switches in the full bridges and basic units, respectively. According to Fig. 7, the maximum voltage of switches of the basic unit can be calculated, as follows: Eswitch,U =
z n
Eij = E × (Nlevel − 1).
(35)
i=1 j=1
The maximum voltage of switches in the jth full-bridges converter (Eswitch,F ) can be calculated as follows: Eswitch,F = 2 ×
z n
Eij = E × (Nlevel − 1).
(36)
i=1 j=1
Using (34)–(36), the maximum magnitude of the blocking voltage of switches can be obtained as follows: Eswitch = 2E × (Nlevel − 1).
(37)
Fig. 9(d) compares the blocking voltages on switches to realize Nlevel by the proposed structure and recommended
Fig. 11. Seven-level symmetric converter.
structures in [18] and [19]. This comparison shows that the blocking voltage on switches in the suggested structure is a few more than that suggested topologies in [19] for realizing Nlevel voltages for Eo . It is noticeable that the proposed structure and presented structure in [19] utilize multiple cascaded full bridges in the output side of the converter, while the presented structure in [18] utilizes one full bridge in the output side and this this full-bridge converter has to withstand a voltage equal to sum of all of dc sources. This leads to restriction on the high-voltage applications. However, the proposed cascade converter can be used in high-voltage applications. E. Comparison of the Required DC Sources Fig. 9(e) compares the number of dc sources to realize Nlevel voltages in the two algorithms of proposed topology and proposed structures in [18] and [19]. This figure shows that the two methods of proposed topologies and proposed topology in [19] need similar number of dc sources. VIII. E XPERIMENTAL AND S IMULATION R ESULTS This section deals with the simulation and experimental results for three proposed switched-diode multilevel converter topologies. First, the simulation results for a seven-level symmetric switched-diode converter are discussed. Then, the simulation and experimental results for a 15-level asymmetric switched-diode converter and 25-level cascade switched-diode converter are presented. For all of the studies, test has been made on the R-L load with the magnitude of 40 mH and 260 Ω. The value of output voltage frequency is 50 Hz.
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Fig. 12. Simulation results of seven-level symmetric switched-diode converter. (a) Output voltage and harmonic spectrum (THD = 9.50%). (b) Output current and harmonic spectrum (THD = 3.49%).
Several switching control strategies have been developed for multilevel converters such as fundamental frequency switching, sinusoidal PWM, selective harmonic elimination (SHE-PWM), space vector PWM (SV-PWM), and others [22]–[25]. In this paper, the fundamental frequency-switching strategy has been used. The benefit of the fundamental frequency-switching technique is its low switching frequency compared to other control strategies [26]. For power converters, the total harmonic distortion (THD) is a popular performance index, which evaluates the quantity of harmonic contents in the output waveform. For sinusoidal waveform, the THD is defined as follows: ∞
Voh 2 h=3,5,7,... Vorms = − 1. (38) T HD = Vo1 Vo1 In this equation, h represents the order of the corresponding harmonic, while the subindex 1 corresponds to the fundamental frequency. Hence, Voh and Vo1 are the rms of the h order harmonic and fundamental of the output voltage, respectively. Also, Vorms represents the rms magnitudes of the output voltage. In above relation, the value of Vo1 and Vorms can be obtained using the following equations, respectively: ⎞2 ⎛ √ N ∞ level cos(mθ ) 2 2V j ⎠ ⎝ × (39) Vorms = π m m=1,3,5,... j=1 √ N level 2 2V Vo 1 = × cos(θj ) (40) π j=1 where, the values of θ1 , θ2 , . . . , θNlevel represent switching angles and are calculated by j − 0.5 θj = sin−1 j = 1, 2, 3, . . . , Nlevel . (41) Nlevel For example, Fig. 10 shows 15-level inverter waveform as a sum of six-stepped waveforms. It is clear that the value of THD depends on the number of levels and switching angles. It is obvious that increasing the number of levels leads to the multilevel converter producing near-sinusoidal output voltage waveform and, as a result, very low harmonic distortion. The objective of this paper is not the calculation of the optimal switching angles for the elimination of selected harmonics and reducing the total harmonic distortion.
Fig. 13 (a) Fifteen-level asymmetric converter. (b) Photo of prototype.
Fig. 14.
Gate drive circuit of switches.
A. Seven-Level Symmetric Switched-Diode Converter Fig. 11 shows a seven-level symmetric switched-diode converter structure. In this topology, the values of dc sources are equal and for each one of them 35 V has been used. Hence, the maximum output voltage is 105 V. In this topology, three dc sources and six IGBTs has been used. For the same number of levels, the symmetric CHB topology needs three dc sources and 12 IGBTs, which the number of IGBTs is higher than that of recommended symmetric structure. The output voltage and current of proposed seven-level topology are shown in Fig. 12. THD values of output voltage and current based on simulation are 9.50% and 3.49%, respectively. Based on this figure and the value of THD for current, it is clear that the load current is almost sinusoidal because the R-L load of the symmetric switched-diode converter (R-L) behaves as a low-pass filter for the current. B. Fifteen-Level Asymmetric Switched-Diode Converter In this section, the simulation and experimental results for a 15-level asymmetric switched-diode converter are explained. Fig. 13(a) shows the structure of proposed 15-level converter. Fig. 13(b) shows photographs of the prototype. The prototype converter was built using IRFP450 MOSFET’s as switching devices with internal antiparallel diodes, TLP250
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Fig. 15. Simulation and measurement results (Time/div = 4 ms) and (Voltage/div = 5 V by 1 : 10 probe): (a) Experimental output voltage; (b) simulation output voltage and harmonic spectrum (THD = 3.08%); (c) experimental output voltage; (d) simulation output current and harmonic spectrum (THD = 1.01%).
as IGBT driver, and MUR460 as fast-recovery diodes. The gate driver circuit of switches in proposed topologies is shown in Fig. 14, which consists of an opto-coupler, a schmit trigger and a buffer. This topology has three dc sources and seven IGBTs. The values of dc sources are E1 = 15 V, E2 = 30 V, and E3 = 60 V so that maximum 105 V output voltage is obtainable. It is noticeable that two lamps are connected in parallel. Fig. 15 shows simulation and measurement results. For this case, THDs of the output voltage and current based on simulations are 3.08% and 1.01%, respectively. It is obvious that the simulations and experimental results have an excellent correspondence with each other. In a multilevel converter, to calculate the efficiency of the converter (η) based on measurements, it is necessary to measure the total (Pinput ) and output (Poutput ) powers. Then, the efficiency of a multilevel converter is obtained by the following equation: η=
Poutput . Pinput
TABLE III M AGNITUDES OF VARIOUS P OWERS AND E FFICIENCY OF THE C ASCADE C ONVERTER
(42)
In this relationship, Pinput is the sum of the output power of the dc voltage sources. Table III shows the values of the different powers and the efficiency of the proposed 15-level converter. The efficiency
Fig. 16. Twenty-five-level cascade converter.
of the converter is related to the applied control strategy. In this paper, the fundamental frequency control strategy has been used. Therefore, the converter has high efficiency.
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Fig. 17. Simulation results for 25-level cascade switched-diode converter. (a) Output voltage of the first stage (Eo,1 ); (b) output voltage of the second stage (Eo,2 ); (c) output voltage and harmonic spectrum (THD = 2.19%); (d) output current and harmonic spectrum (THD = 0.45%).
C. Twenty-Five-Level Cascade Switched-Diode Converter Fig. 16 shows a 25-level cascade converter topology structure based on the first method of proposed cascade topology (see Section V-A).
It is noticeable that if the values of dc sources in this topology are determined using the second method of proposed topology (see Section V-B), the number of output voltage levels will be 49.
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TABLE IV M AGNITUDES OF VARIOUS P OWERS AND E FFICIENCY OF THE C ASCADE C ONVERTER
TABLE V S IMULATION R ESULTS FOR P ROPOSED C ONVERTERS FOR D IFFERENT P OWER FACTOR
Fig. 18. Spikes in a simulated output voltage of seven-level symmetric converter.
table, the values of dc sources for each converter are mentioned in this table. This table shows that in all topologies active power (P) is maximum at unity power factor while reactive power is zero. When power factor decreases, P reduces and Q increases while the load current is approximately the same (due to fixed Z). It is noticeable that when the circuit is simulated, spikes occur in the output voltage wave which tends to deteriorate the power quality. Fig. 18 shows the output voltage waveform of seven-level converter where there are spikes at the output voltage. When the load is changed the amplitude of spikes is changed. Therefore, the value of rms output voltage is changed. These spikes occur in all of multilevel converters and several methods can be used to eliminate these spikes. However, the effect of spikes at the output voltage (VL,rms ) in the 25-level cascade converter is much less than other topologies, which is a positive advantage.
IX. C ONCLUSION
The values of dc sources have been selected based on the first method of proposed cascade switched-diode converter (E11 = E12 = 16 V, E21 = E22 = 80 V). Fig. 17(a) and (b) shows the output voltage of Eo,1 and Eo,2 based on simulation and experimental results. Fig. 17(c) and (d) shows output voltage and currents waveforms. THDs of the output voltage and current based on simulations are 2.19% and 0.46%, respectively. The comparison of THDs of output voltage and current in the three topologies shows that increasing the number of levels leads to the multilevel converter producing output voltage waveform with very low THD. Table IV indicates the magnitude of the various powers and the efficiency of the presented 25-level converter. The efficiency of the converter is %93.99. The comparison of the efficiency in 15-level asymmetric converter and 25-level cascade converter shows that the 25-level cascade converter has high efficiency. It means that the power losses in 25-level cascade converter are less than 15-level asymmetric converter. These topologies have been analyzed for different power factors. Table V shows the results for different power factor. In fact, the variation of rms voltage Vl , rms current Il , active power P , and reactive power Q with different load power factor (Cos(ϕ)) for simulated converters is shown in Table V. In this
This paper proposes new topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter with reduced number of components. The proposed cascade structure extends the design flexibility and the possibilities to optimize the converter for different objectives such as the minimization of the number of IGBTs, gate driver circuits, dc voltage sources, standing voltage on switches, and power diodes. Less number of the switches leads to the reduction of size, simple control strategy, and high efficiency. Comparison among the proposed converters with conventional cascade and other similar topologies was provided. It was shown that the proposed topologies can produce many levels with fewer components. R EFERENCES [1] R. Stala, “A natural DC-link voltage balancing of diode-clamped inverters in parallel systems,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 5008– 5018, Nov. 2013. [2] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel power conversion system: A competitive solution for high-power applications,” IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834–841, May/Jun. 2000. [3] R. Alonso, E. Roman, A. Sanz, V. E. M. Santos, and P. Ibanez, “Analysis of inverter-voltage influence on distributed MPPT architecture performance,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3900–3907, Oct. 2012. [4] M. N. A. Kadir, S. Mekhilef, and H. W. Ping, “Voltage vector control of a hybrid three-stage eighteen-level inverter by vector decomposition,” IET Trans. Power Electron., vol. 3, no. 4, pp. 601–611, Jul. 2010. [5] L. M. Tolbert and F. Z. Peng, “Multilevel converters as a utility interface for renewable energy system,” in Proc. IEEE Power Eng. Soc. Summer Meet., 2000, pp. 1271–1274.
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[6] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and Z. Du, “Control of multilevel converter using resultant theory,” IEEE Trans. Control. Syst. Technol., vol. 11, no. 3, pp. 345–354, May 2003. [7] R. Stala, “Application of balancing circuit for DC-link voltages balance in a single-phase diode-clamped inverter with two three-level legs,” IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4185–4195, Sep. 2011. [8] Z. Pan, F. Z. Peng, V. Stefanovic, and M. Leuthen, “A diode-clamped multilevel converter with reduced number of clamping diodes,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2004, pp. 820–824. [9] T. Maynard and H. Foch, “Multi-level conversion: High voltage choppers and voltage-source inverters,” in IEEE PESC/IEEE Power Electron. Spec. Conf., 1992, pp. 397–403. [10] F. Z. Peng, W. Qian, and D. Cao, “Recent advances in multilevel converter/inverter topologies and applications,” in Proc. Int. Power Electron. Conf., 2010, pp. 492–501. [11] E. Babaei, M. T. Haque, and S. H. Hosseini, “A novel structure for multilevel converters,” in Proc. ICEMS, 2005, vol. 2, pp. 1278–1283. [12] K. Sivakumar, A. Das, R. Ramchand, C. Patel, and K. Gopakumar, “A hybrid multilevel inverter topology for an open-end winding inductionmotor drive using two-level inverters in series with a capacitor-fed H-bridge cell,” IEEE Trans. Ind. Electron., vol. 57, no. 11, pp. 3707–3714, Nov. 2010. [13] M. G. H. Aghdam, S. H. Fathi, and G. B. Gharehpetian, “Comparison of OMTHD and OHSW harmonic optimization techniques in multi-level voltage-source inverter with non-equal DC sources,” in Proc. 7th Int. Conf. Power Electron., 2007, pp. 587–591. [14] M. Khazraei, H. Sepahvand, K. A. Corzine, and M. Ferdowsi, “Active capacitor voltage balancing in single-phase flying-capacitor multilevel power converters,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 769– 778, Feb. 2012. [15] R. A. Ahmed, S. Mekhilef, and H. W. Ping, “New multilevel inverter topology with reduced number of switches,” in Proc. Int. Middle East Power Syst. Conf., 2010, pp. 565–570. [16] M. Carpita and S. Teconi, “A novel multilevel structure for voltage source inverter,” in Proc. EPE, 1991, pp. 90–94. [17] Y. S. Lai and F. S. Shyu, “Topology for hybrid multilevel inverter,” Proc. Inst. Elect. Eng.—Elect. Power Appl., vol. 149, no. 6, pp. 449–458, Nov. 2002. [18] E. Babaei, “A cascade multilevel converter topology with reduced number of switches,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 2657–2664, Nov. 2008. [19] J. Ebrahimi, E. Babaei, and G. B. Gharehpetian, “A new multilevel converter topology with reduced number of power electronic components,” IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 655–667, Feb. 2012. [20] C. Klumpner and F. Blaabjerg, “Using reverse blocking IGBTs in power converters for adjustable speed drives,” IEEE Trans. Ind. Appl., vol. 42, no. 3, pp. 807–816, May/Jun. 2006. [21] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. T. Haque, and M. Sabahi, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology,” Elect. Power Syst. Res., vol. 77, no. 8, pp. 1073–1085, Jun. 2007. [22] S. Mekhilef and M. N. Abdul Kadir, “Novel vector control method for three-stage hybrid cascaded multilevel inverter,” IEEE Trans. Ind. Electon., vol. 58, no. 4, pp. 1339–1349, Apr. 2010. [23] K. K. Gupta and S. Jain, “A multilevel Voltage Source Inverter (VSI) to maximize the number of levels in output waveform,” Int. J. Elect. Power Energy Syst., vol. 44, no. 1, pp. 25–36, Jan. 2012. [24] P. T. Josh, J. Jerome, and A. Wilson, “The comparative analysis of multicarrier control techniques for SPWM controlled cascaded H-bridge multilevel inverter,” in Proc. ICETECT, 2011, pp. 459–464. [25] E. Villanueva, P. Correa, J. Rodriguez, and M. Pacas, “Control of a single-phase cascaded H-bridge multilevel inverter for grid-connected photo-voltaic systems,” IEEE Trans. Ind. Electron., vol. 56, no. 11, pp. 4399–4406, Nov. 2009. [26] D. C. Ludois, J. K. Reed, and G. Venkataramanan, “Hierarchical control of bridge-of-bridge multilevel power converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2679–2690, Aug. 2010.
Rasoul Shalchi Alishah was born in Alishah, Iran, in 1989. He received the B.Sc. degree in power electrical engineering from the Azad University of Tabriz, Tabriz, Iran, in 2011 and the M.Sc. degree in power electrical engineering from Urmia University, Urmia, Iran, in 2013. His current research interests include power electronic converters, multilevel converters, Z-source and matrix converters, application of power electronics in renewable energy systems, harmonics, and power quality. Mr. Shalchi Alishah was selected by the Department of Electrical and Computer Engineering of Urmia University as the best student in 2013. Since 2014, he has been a member of the Iran Elites National Foundation. He is the author of more than 20 journal and conference papers. Also, he is a reviewer and Editorial Board member of several international journals.
Daryoosh Nazarpour was born in Urmia, Iran, in 1958. He received the B.Sc. degree from the Iran University of Science and Technology, Tehran, Iran, in 1982 and the M.Sc. and Ph.D. degrees from the Faculty of Engineering, University of Tabriz, Tabriz, Iran, in 1988 and 2005, respectively, all in electrical power engineering. Currently, he is an Assistant Professor in Urmia University. His research interests include power electronics and flexible ac transmission system.
Seyed Hossein Hosseini (M’93) was born in Marand, Iran, in 1953. He received the M.S. degree from the Faculty of Engineering, University of Tabriz, Tabriz, Iran, in 1976; the DEA degree from the Institut National Polytechnique de Lorraine (INPL), Nancy, France, in 1978; and the Ph.D. degree from INPL, France, in 1981, all in electrical engineering. In 1982, he joined the University of Tabriz, Iran, as an Assistant Professor in the Department of Electrical Engineering. From September 1990 to September 1991, he was a Visiting Professor at the University of Queensland, Australia. From 1990 to 1995, he was an Associate Professor in the University of Tabriz. Since 1995, he has been a Professor in the Department of Electrical Engineering, University of Tabriz. From September 1996 to September 1997, he was a Visiting Professor at the University of Western Ontario, London, ON, Canada. His research interests include power electronic converters, matrix converters, active and hybrid filters, application of power electronics in renewable energy systems and electrified railway systems, reactive power control, harmonics, and power quality compensation systems such as SVC, UPQC, and FACTS devices.
Mehran Sabahi (M’09) was born in Tabriz, Iran, in 1968. He received the B.Sc. degree in electronic engineering from the University of Tabriz, Tabriz, Iran; the M.Sc. degree in electrical engineering from Tehran University, Tehran, Iran; and the Ph.D. degree in electrical engineering from the University of Tabriz, in 1991, 1994, and 2009, respectively. In 2009, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz, where he has been an Assistant Professor since 2009. His current research interests include power electronic converters and renewable energy systems.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 10, OCTOBER 2014
Novel Topologies for Symmetric, Asymmetric, and Cascade Switched-Diode Multilevel Converter With Minimum Number of Power Electronic Components Rasoul Shalchi Alishah, Daryoosh Nazarpour, Seyed Hossein Hosseini, Member, IEEE, and Mehran Sabahi, Member, IEEE
Abstract—In this paper, novel topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which can produce many levels with minimum number of power electronic switches, gate driver circuits, power diodes, and dc voltage sources. The number of required power electronic switches against required voltage levels is a very important factor in designing of multilevel converter, because switches define the reliability, circuit size, cost, installation area, and control complexity. For asymmetric and cascade converter, new algorithms for determination of dc voltage sources values are presented. To produce maximum number of levels at the output voltage, the proposed cascade topology is optimized for different goals, such as the minimization of the number of power electronic switches, gate driver circuits, power diodes, dc voltage sources, and blocking voltage on switches. Comparison of the results of various multilevel converters will be investigated to reflect the merits of the presented topologies. The operations of the proposed multilevel converters have been analyzed with the experimental and simulation results for different topologies. Verification of the analytical results is done using MATLAB simulation. Index Terms—Asymmetric, bidirectional switch, cascade, fullbridge converter, multilevel converter, symmetric.
I. I NTRODUCTION
M
ULTILEVEL power conversion was first presented over 30 years ago [1]. Multilevel converters can produce a large number of output voltage levels, which results in high voltage capability, lower harmonic contents, lower switching losses, better electromagnetic compatibility, and high power quality. Multilevel converters have been used for several applications such as static reactive power compensation, adjustablespeed drives, renewable energy sources, and so on [2]–[4]. The principal function of multilevel converter is to synthesize
Manuscript received May 8, 2013; revised August 21, 2013; accepted November 14, 2013. Date of publication January 2, 2014; date of current version May 2, 2014. R. Shalchi Alishah and D. Nazarpour are with the Faculty of Electrical and Computer Engineering, Urmia University, Urmia 51747, Iran (e-mail: Rasoul. [email protected]; [email protected]). S. H. Hosseini and M. Sabahi are with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51666, Iran (e-mail: hosseini@ tabrizu.ac.ir; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2013.2297300
a desired ac voltage from several separate dc sources [5], [6]. Many kinds of topologies for multilevel converters have been proposed. In general, there are three types of multilevel converters: 1) Neutral Point Clamped (NPC) converter [7], [8]; 2) Flying Capacitor (FC) converter [9], [10]; and 3) Cascade H-bridge (CHB) converter [11], [12]. The unequal voltage sharing among series connected capacitors is the main drawback of NPC converter. In addition, this structure needs a large number of clamping diode for higher levels. The FC converter requires a great number of storage capacitors for higher output voltage levels and the capacitors voltage balancing is difficult. Conventional cascade multilevel converter is one of the most important topologies in the family of conventional multilevel converters because cascade converter requires the least number of components, when compared with the flying capacitor and diode clamped converter [13], [14]. A cascade multilevel converter consists of the number of H-bridge converter units with separate dc sources for each unit, which connected in cascade or series [15]. In symmetric cascaded multilevel converter, dc voltage sources values of similar cells are equal. For the same number of power devices, asymmetric cascade multilevel topology significantly increases the number of output voltage levels. In these topologies, the values of dc voltage sources of different cells are nonequal [16], [17]. However, the symmetric and asymmetric CHB converter requires a large number of switches and dc voltage sources. An attempt has been made in [18] to propose a new structure for multilevel converter with reduced number of power electronic components in comparison with conventional cascade converter. This converter needs a large number of bidirectional switches. In addition, the magnitude of blocked voltage by bidirectional switches is high. In [19], another new topology for cascade multilevel converter has been introduced, which reduces the number of bidirectional switches, power diodes, and dc voltage source in comparison with proposed topology in [18]. This topology consists of several submultilevel converters and full-bridge converters. But, this topology requires a large number of bidirectional switches and gate driver circuits. In this paper, new topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter are proposed, which have more advantages in comparison with presented topologies in [18], [19].
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SHALCHI ALISHAH et al.: SYMMETRIC, ASYMMETRIC, AND CASCADE SWITCHED-DIODE CONVERTER
Fig. 1.
Basic circuit of proposed switched-diode multilevel converter.
Fig. 2.
Proposed symmetric switched-diode multilevel converter topology.
Fig. 3. Comparison of conventional symmetric cascade topology with proposed symmetric switched-diode topology.
Fig. 4.
TABLE I S WITCH S TATES FOR S YMMETRICAL T OPOLOGY
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Proposed asymmetrical switched-diode multilevel converter topology.
the basic unit generates a staircase voltage waveform (Eo ) with positive polarity (E, 2E, 3E, . . . . . .). It is connected to a fullbridge converter, which particularly alternates the input voltage polarity and generates positive or negative staircase waveform (Eo ) at the output voltage (0, ±E, ±2E, ±3E, . . . . . .). The number of output levels (Nlevel ), IGBTs (NIGBT ), and the maximum output voltage (Eo,max ) in the proposed symmetric converter are obtained as follows, respectively: Nlevel = 2K + 1 NIGBT = K + 3 Eo,max = KE.
II. BASIC OF P ROPOSED M ULTILEVEL C ONVERTER T OPOLOGIES Fig. 1 shows the basic topology for proposed switched-diode multilevel converter. In this circuit, when the switch S is turned off, the current flows from the diode D and load voltage will be E. But, when the switch S is turned on, the diode is reverse biased and current flows from the voltage source E and load voltage will be (2E). By the use of this method, the load voltage is controlled. This method is the basic of proposed multilevel converter. The new presented structures in three different topologies are introduced and consist of: 1) symmetric switched-diode multilevel converter; 2) asymmetric switcheddiode multilevel converter; and 3) cascade switched-diode multilevel converter. III. P ROPOSED S YMMETRICAL S WITCHED -D IODE M ULTILEVEL C ONVERTER The structure of proposed symmetric switched-diode multilevel converter is shown in Fig. 2. In this structure, the values of the dc voltage sources are equal. Therefore, this topology is called symmetric switcheddiode multilevel converter. Table I gives the values of output voltages (Eo ) for different states of switches. In this topology,
(1) (2) (3)
Where K represents the number of dc voltage sources. Fig. 3 compares the number of IGBTs versus the number of output levels (Nlevel ) in the proposed symmetric switched-diode topology and the symmetric conventional cascade topology. This figure shows that the proposed converter requires the least number of IGBTs. IV. P ROPOSED A SYMMETRICAL S WITCHED -D IODE M ULTILEVEL C ONVERTER Asymmetrical multilevel converter provides an increased number of output voltage levels for the same number of power electronic devices than its symmetric counterpart. In [16], [17], for dc voltage sources of conventional cascade H-bridge topology, two main methods have been suggested, which have been called binary and trinary configuration. The trinary configuration can produce a great number of levels in comparison with binary configuration [17]. Fig. 4 shows the proposed topology for asymmetrical switched-diode converter, which consists of one basic unit and a full-bridge converter. Table II shows the ON switches look-up table for proposed asymmetric topology. In this topology, the values of dc sources are suggested to be chosen according to the following algorithm: E1 = E Ej = 2(j−1) E
For j = 2, 3, 4, . . . , Z.
(4) (5)
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TABLE II S WITCH S TATES FOR A SYMMETRICAL T OPOLOGY
Fig. 6. Voltage balancing of dc-link in recommended converter using (a) dc/dc converters and (b) multitap transformer.
Fig. 5. Comparison of proposed asymmetric switched-diode topology with trinary cascade topology in [17].
For this method, the number of levels and maximum output voltage are given by (6) and (7), respectively Nlevel = 2(Z+1) − 1 Eo,max = (2Z − 1)E
(6) (7)
where Z represents the number of dc sources. In the proposed asymmetric topology, the number of IGBTs is obtained by NIGBT = Z + 4.
(8)
Fig. 5 shows the comparison between proposed asymmetric switched-diode topology with trinary configuration of conventional cascade in [17]. This comparison shows that the proposed asymmetric switched-diode converter generates the maximum number of level with fewer numbers of switches. It is important to note that the proposed symmetric and asymmetric switched-diode topologies can be used in renewable energy sources and medium-voltage applications. However, this structures needs several dc voltage sources. For renewable energy source applications, instead of dc voltage sources, we can use photovoltaic panels. In this application, capacitor voltage balancing is important. For example, in fuel cells, the output voltages are changed during the converter performance and lead to reduction of the quality of output voltage in dc-link of converter. To solve this problem, as shown in Fig. 6(a), the voltage of each capacitor is controlled with one dc/dc converter. Fig. 6(b) illustrates another method for control of capacitor voltages of proposed converter for medium-voltage applications. This circuit consists of an ac voltage source, multitap transformer, and several rectifiers. The proposed symmetric and asymmetric switched-diode topologies use only one full-bridge
Fig. 7.
Proposed cascade switched-diode multilevel converter topology.
converter, which is a restriction for high-voltage applications. In addition, these topologies need more number of devices. V. P ROPOSED C ASCADE S WITCHED -D IODE M ULTILEVEL C ONVERTER To provide a large number of levels with less number of components, cascade switched-diode multilevel converters can be used. Fig. 7 shows the structure of proposed cascade multilevel converter. The output voltage of the proposed cascade switcheddiode multilevel converter is given by Eout = Eo1 + Eo2 + · · · + Eon .
(9)
For the proposed cascade topology, two methods for determination of values of the dc sources are presented.
SHALCHI ALISHAH et al.: SYMMETRIC, ASYMMETRIC, AND CASCADE SWITCHED-DIODE CONVERTER
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A. First Algorithm In this algorithm, the values of all of the dc voltage sources in each stage are the same. For stage 1, E1i = E1
i = 1, 2, 3, . . . , Z1 .
(10)
Therefore, the maximum output voltage of this stage (Eo1,max ) will be Eo1,max = Z1 × E1 .
(11)
For stage 2,
E2i = E2 = E1 + 2×Eo1,max = (2Z1 +1)×E1 i = 1, 2, . . . , Z2. (12)
In this stage, the maximum output voltage (Eo2,max ) will be Eo2,max = Z2 × E2 . For stage 3,
E3i =E3 = E1 + 2 × Eo2,max + 2 × Eo1,max =(2Z1 + 1) × (2Z2 + 1) × E1 i = 1, 2, 3, . . . , Z3 .
(13) 1Z+4
(14)
Fig. 8. Variation of (a) (2Z + 1)1/Z+4 and (2Z+1 − 1) . (b) (2Z + 1/Z . (c) Variation of (Z + 4)/ ln(2Z + 1) and 1)1/Z and (2Z+1 − 1) (Z + 4)/ ln(2Z+1 − 1). (d) Variation of (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) versus Z.
For the jth stage,
VI. O PTIMAL T OPOLOGIES
Eji = Ej = (2Z1 +1)×(2Z2 +1)×· · ·×(2Zj−1 +1)×E1 . (15) In this method, the number of output voltage levels (Nlevel,F ) can be determined by the following equation: Nlevel,F = Nlevel,stage1 ×Nlevel,stage.2 × · · · × Nlevel,stage.n = (2Z1 + 1) × (2Z2 + 1) × · · · × (2Zn + 1). (16) n
Zi × Ei1 .
In this structure for the jth stage, the dc voltage source magnitudes are given by (18) and (19) Ej1 = 2(Z1 +1) − 1 × 2(Z2 +1) − 1 × · · · × 2(Zj−1 +1) − 1 × E (18) Ej1
i = 2, 3, . . . , Zj .
n=
(19)
(24)
n
Nlevel,S = (2Z+1 − 1) .
(20)
= Nlevel,stage.1 ×Nlevel,stage.2 ×· · ·×Nlevel,stage.n = (2Z1 +1 − 1)×(2Z2 +1 − 1)×· · ·×(2Zn +1 − 1). (21)
The number of IGBTs in the proposed cascade topology is (22)
(25)
Using (24) and (25), it is obvious that
NIGBT Nlevel,F = (2Z + 1)1/Z+4
1/Z+4 NIGBT Nlevel,S = (2Z+1 − 1) .
(26)
Fig. 8(a) shows the variation of (2Z + 1)1/Z+4 and 1/Z+4 (2 − 1) versus Z. It is clear that the maximum number of levels for the first method is obtained for Z = 3. This means that a topology consisting of three dc sources in each stage can generate maximum output levels for Eo . For the second method, the maximum is obtained for Z = ∞. From theoretical point of view, this means that a topology consisting of one stage with available IGBTs is favorable for a constant number of IGBTs. It is important to note that the number of IGBTs and gate driver circuits is the same. Z+1
i=1 Nlevel,S
NIGBT = (Z1 + Z2 + Z3 + · · · + Zn ) + 4n.
NIGBT . Z +4
Nlevel,F = (2Z + 1)n
In this method, the maximum output voltages of converter (Eomax,S ) and the number of output voltage levels (Nlevel,S ) can be calculated as follows, respectively: Eomax,S n Z +1 (2 i − 1) ×Ei1 =
(23)
Now, the magnitude of Z must be determined. Using (16), (21), and (23), the maximum number of levels for two suggested methods is given by the following equations:
B. Second Algorithm
Eji = 2
Z1 = Z2 = Z3 = · · · = Zn = Z.
(17)
i=1
(i−1)
The product of the numbers (whose summation is constant) will be maximized, when the following relation is valid:
Using (22) and (23) can be written as follows:
In this method, the maximum output voltage (Eomax,F ) is Eomax,F =
A. Optimization of the Proposed Cascade Converter for Maximum Number of Levels With Constant Number of IGBTs
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B. Optimization of the Proposed Cascade Converter for Maximum Number of Levels With Constant Number of DC Sources Suppose that the proposed structure consists of a series of n stage converters. In this topology, the number of dc sources can be obtained Nsource = Z1 + Z2 + · · · + Zn .
(27)
Using (23), the number of dc sources is obtained by (28) Nsource = Z × n.
(28)
Considering (25), the maximum number of output voltage levels for two methods is given by
Nsource Nlevel,F = (2Z + 1)1/Z
1/Z Nsource Nlevel,S = (2Z+1 − 1) .
(29) 1/Z
Fig. 8(b) shows the variation of (2Z +1)1/Z and (2Z+1 −1) versus Z. It is evident that the maximum number of output voltage levels for two proposed methods is obtained for Z = 1. It is noticeable that the proposed structure is converted to a conventional cascade converter. C. Optimization of the Proposed Cascade Converter for Minimum Number of IGBTs With Constant Number of Levels If the number of IGBTs in each stage is assumed to be equal to z, then considering (26), the numbers of IGBTs (NIGBT ) for two algorithms are given by the following equations, respectively: NIGBT,F = (Z + 4) × n = ln(Nlevel ) × NIGBT,S = (Z +4) × n = ln(Nlevel ) ×
(Z +4) ln(2Z +1) (Z +4) . ln(2Z+1 −1)
(30)
Fig. 8(c) shows the variation of (Z + 4)/ ln(2Z + 1) and (Z + 4)/ ln(2Z+1 − 1) versus Z. It is evident that the minimum number of IGBTs to realize Nlevel values for the first method is given for Z = 3. For the second method, the minimum number of IGBTs is theoretically realizable for Z = ∞.
Ndiode,F = (2Z +4) × n = ln(Nlevel ) ×
(2Z +4) ln(2Z +1)
Ndiode,S = (2Z +4) × n = ln(Nlevel ) ×
(2Z +4) . (33) ln(2Z+1 −1)
Since Nlevel is constant, Ndiode will be minimized, when (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) tends to be minimum. Fig. 8(d) shows variation of (2Z + 4)/ ln(2Z + 1) and (2Z + 4)/ ln(2Z+1 − 1) versus Z. It is clear that the minimum number of power diodes to realize Nlevel values for the first method is given for Z = 2. From theoretical point of view, for the second methods, the minimum number of power diodes is obtained for Z = ∞.
A. Comparison of the Required Number of IGBTs
It is important to note that the number of IGBTs and diodes are not equal. In this topology, the number of power diodes is given by following equation: (31)
Using (23), we have Ndiode = (2Z + 4) × n.
Considering (25) and (32), it is clear that we have
VII. C OMPARISON OF THE P ROPOSED C ASCADE S WITCHED -D IODE T OPOLOGY W ITH OTHER T OPOLOGIES
D. Optimization of the Proposed Cascade Converter for Minimum Number of Power Diodes With Constant Number of Levels
Ndiode = 2(Z1 + Z2 + Z3 + · · · + Zn ) + 4n.
Fig. 9. (a) Number of IGBTs against the number of levels in different topologies, (b) number of drivers against the number of levels in different topologies, (c) number of diodes against the number of levels in different topologies, (d) blocking voltages on switches in different topologies, and (e) number of dc sources against the number of levels in different topologies.
(32)
It is important to note that in the presented topologies in [18] and [19], bidirectional switches have been used that are composed of two IGBTs [20], [21]. Fig. 9(a) compares the number of IGBTs versus the number of levels for two methods of determination of dc voltage sources in the proposed topology and topologies presented in [18] and [19]. It is obvious that the second method of proposed topology requires less number of IGBTs to realize Nlevel for Eo .
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B. Comparison of the Required Gate Driver Circuits In [18] and [19], each bidirectional switch consists of two IGBTs and two antiparallel diodes. Also, each unidirectional switch used in full-bridge converter consists of an IGBT and an antiparallel diode. Each bidirectional and unidirectional switch of the converter needs only one gate driver circuit. The gate driver circuits are the electronic part of the circuit and increasing the number of gate driver circuits is a considerable deficiency. Because, increasing the number of gate drivers cause increasing costs and control complexity. Fig. 9(b) compares the number of gate driver circuits versus the number of levels in different topologies. This figure shows that the second method of proposed cascade topology needs fewer numbers of gate driver circuits. C. Comparison of the Required Power Diodes Fig. 9(c) compares the number of power diodes versus the number of levels in the two methods of proposed topology and the proposed topologies in [18] and [19]. As shown in this figure, the number of required power diodes in the first method of proposed topology and suggested topology in [19] are equal and the second method of proposed topology requires minimum number of power diodes.
Fig. 10. Fifteen-level converter as a sum of seven-stepped waveforms.
D. Comparison of the Blocking Voltages on Switches In a multilevel converter, the voltage and current ratings of the switches play important roles in the cost and realization of the multilevel converter. In all structures, the currents of all the switches are equal to the rated current of the load. However, this is not true for the voltage [18], [19]. A lower magnitude of the blocking voltage on switches shows that a smaller voltage is applied at the terminal of the switches of the topology, which is considered an advantage. Suppose that the maximum magnitude of the blocking voltage of switches (Eswitch ) is indicated by the following equation: Eswitch = Eswitch,F + Eswitch,U .
(34)
In this equation, Eswitch,F and Eswitch,U represent the maximum voltage of the switches in the full bridges and basic units, respectively. According to Fig. 7, the maximum voltage of switches of the basic unit can be calculated, as follows: Eswitch,U =
z n
Eij = E × (Nlevel − 1).
(35)
i=1 j=1
The maximum voltage of switches in the jth full-bridges converter (Eswitch,F ) can be calculated as follows: Eswitch,F = 2 ×
z n
Eij = E × (Nlevel − 1).
(36)
i=1 j=1
Using (34)–(36), the maximum magnitude of the blocking voltage of switches can be obtained as follows: Eswitch = 2E × (Nlevel − 1).
(37)
Fig. 9(d) compares the blocking voltages on switches to realize Nlevel by the proposed structure and recommended
Fig. 11. Seven-level symmetric converter.
structures in [18] and [19]. This comparison shows that the blocking voltage on switches in the suggested structure is a few more than that suggested topologies in [19] for realizing Nlevel voltages for Eo . It is noticeable that the proposed structure and presented structure in [19] utilize multiple cascaded full bridges in the output side of the converter, while the presented structure in [18] utilizes one full bridge in the output side and this this full-bridge converter has to withstand a voltage equal to sum of all of dc sources. This leads to restriction on the high-voltage applications. However, the proposed cascade converter can be used in high-voltage applications. E. Comparison of the Required DC Sources Fig. 9(e) compares the number of dc sources to realize Nlevel voltages in the two algorithms of proposed topology and proposed structures in [18] and [19]. This figure shows that the two methods of proposed topologies and proposed topology in [19] need similar number of dc sources. VIII. E XPERIMENTAL AND S IMULATION R ESULTS This section deals with the simulation and experimental results for three proposed switched-diode multilevel converter topologies. First, the simulation results for a seven-level symmetric switched-diode converter are discussed. Then, the simulation and experimental results for a 15-level asymmetric switched-diode converter and 25-level cascade switched-diode converter are presented. For all of the studies, test has been made on the R-L load with the magnitude of 40 mH and 260 Ω. The value of output voltage frequency is 50 Hz.
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Fig. 12. Simulation results of seven-level symmetric switched-diode converter. (a) Output voltage and harmonic spectrum (THD = 9.50%). (b) Output current and harmonic spectrum (THD = 3.49%).
Several switching control strategies have been developed for multilevel converters such as fundamental frequency switching, sinusoidal PWM, selective harmonic elimination (SHE-PWM), space vector PWM (SV-PWM), and others [22]–[25]. In this paper, the fundamental frequency-switching strategy has been used. The benefit of the fundamental frequency-switching technique is its low switching frequency compared to other control strategies [26]. For power converters, the total harmonic distortion (THD) is a popular performance index, which evaluates the quantity of harmonic contents in the output waveform. For sinusoidal waveform, the THD is defined as follows: ∞
Voh 2 h=3,5,7,... Vorms = − 1. (38) T HD = Vo1 Vo1 In this equation, h represents the order of the corresponding harmonic, while the subindex 1 corresponds to the fundamental frequency. Hence, Voh and Vo1 are the rms of the h order harmonic and fundamental of the output voltage, respectively. Also, Vorms represents the rms magnitudes of the output voltage. In above relation, the value of Vo1 and Vorms can be obtained using the following equations, respectively: ⎞2 ⎛ √ N ∞ level cos(mθ ) 2 2V j ⎠ ⎝ × (39) Vorms = π m m=1,3,5,... j=1 √ N level 2 2V Vo 1 = × cos(θj ) (40) π j=1 where, the values of θ1 , θ2 , . . . , θNlevel represent switching angles and are calculated by j − 0.5 θj = sin−1 j = 1, 2, 3, . . . , Nlevel . (41) Nlevel For example, Fig. 10 shows 15-level inverter waveform as a sum of six-stepped waveforms. It is clear that the value of THD depends on the number of levels and switching angles. It is obvious that increasing the number of levels leads to the multilevel converter producing near-sinusoidal output voltage waveform and, as a result, very low harmonic distortion. The objective of this paper is not the calculation of the optimal switching angles for the elimination of selected harmonics and reducing the total harmonic distortion.
Fig. 13 (a) Fifteen-level asymmetric converter. (b) Photo of prototype.
Fig. 14.
Gate drive circuit of switches.
A. Seven-Level Symmetric Switched-Diode Converter Fig. 11 shows a seven-level symmetric switched-diode converter structure. In this topology, the values of dc sources are equal and for each one of them 35 V has been used. Hence, the maximum output voltage is 105 V. In this topology, three dc sources and six IGBTs has been used. For the same number of levels, the symmetric CHB topology needs three dc sources and 12 IGBTs, which the number of IGBTs is higher than that of recommended symmetric structure. The output voltage and current of proposed seven-level topology are shown in Fig. 12. THD values of output voltage and current based on simulation are 9.50% and 3.49%, respectively. Based on this figure and the value of THD for current, it is clear that the load current is almost sinusoidal because the R-L load of the symmetric switched-diode converter (R-L) behaves as a low-pass filter for the current. B. Fifteen-Level Asymmetric Switched-Diode Converter In this section, the simulation and experimental results for a 15-level asymmetric switched-diode converter are explained. Fig. 13(a) shows the structure of proposed 15-level converter. Fig. 13(b) shows photographs of the prototype. The prototype converter was built using IRFP450 MOSFET’s as switching devices with internal antiparallel diodes, TLP250
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Fig. 15. Simulation and measurement results (Time/div = 4 ms) and (Voltage/div = 5 V by 1 : 10 probe): (a) Experimental output voltage; (b) simulation output voltage and harmonic spectrum (THD = 3.08%); (c) experimental output voltage; (d) simulation output current and harmonic spectrum (THD = 1.01%).
as IGBT driver, and MUR460 as fast-recovery diodes. The gate driver circuit of switches in proposed topologies is shown in Fig. 14, which consists of an opto-coupler, a schmit trigger and a buffer. This topology has three dc sources and seven IGBTs. The values of dc sources are E1 = 15 V, E2 = 30 V, and E3 = 60 V so that maximum 105 V output voltage is obtainable. It is noticeable that two lamps are connected in parallel. Fig. 15 shows simulation and measurement results. For this case, THDs of the output voltage and current based on simulations are 3.08% and 1.01%, respectively. It is obvious that the simulations and experimental results have an excellent correspondence with each other. In a multilevel converter, to calculate the efficiency of the converter (η) based on measurements, it is necessary to measure the total (Pinput ) and output (Poutput ) powers. Then, the efficiency of a multilevel converter is obtained by the following equation: η=
Poutput . Pinput
TABLE III M AGNITUDES OF VARIOUS P OWERS AND E FFICIENCY OF THE C ASCADE C ONVERTER
(42)
In this relationship, Pinput is the sum of the output power of the dc voltage sources. Table III shows the values of the different powers and the efficiency of the proposed 15-level converter. The efficiency
Fig. 16. Twenty-five-level cascade converter.
of the converter is related to the applied control strategy. In this paper, the fundamental frequency control strategy has been used. Therefore, the converter has high efficiency.
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Fig. 17. Simulation results for 25-level cascade switched-diode converter. (a) Output voltage of the first stage (Eo,1 ); (b) output voltage of the second stage (Eo,2 ); (c) output voltage and harmonic spectrum (THD = 2.19%); (d) output current and harmonic spectrum (THD = 0.45%).
C. Twenty-Five-Level Cascade Switched-Diode Converter Fig. 16 shows a 25-level cascade converter topology structure based on the first method of proposed cascade topology (see Section V-A).
It is noticeable that if the values of dc sources in this topology are determined using the second method of proposed topology (see Section V-B), the number of output voltage levels will be 49.
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TABLE IV M AGNITUDES OF VARIOUS P OWERS AND E FFICIENCY OF THE C ASCADE C ONVERTER
TABLE V S IMULATION R ESULTS FOR P ROPOSED C ONVERTERS FOR D IFFERENT P OWER FACTOR
Fig. 18. Spikes in a simulated output voltage of seven-level symmetric converter.
table, the values of dc sources for each converter are mentioned in this table. This table shows that in all topologies active power (P) is maximum at unity power factor while reactive power is zero. When power factor decreases, P reduces and Q increases while the load current is approximately the same (due to fixed Z). It is noticeable that when the circuit is simulated, spikes occur in the output voltage wave which tends to deteriorate the power quality. Fig. 18 shows the output voltage waveform of seven-level converter where there are spikes at the output voltage. When the load is changed the amplitude of spikes is changed. Therefore, the value of rms output voltage is changed. These spikes occur in all of multilevel converters and several methods can be used to eliminate these spikes. However, the effect of spikes at the output voltage (VL,rms ) in the 25-level cascade converter is much less than other topologies, which is a positive advantage.
IX. C ONCLUSION
The values of dc sources have been selected based on the first method of proposed cascade switched-diode converter (E11 = E12 = 16 V, E21 = E22 = 80 V). Fig. 17(a) and (b) shows the output voltage of Eo,1 and Eo,2 based on simulation and experimental results. Fig. 17(c) and (d) shows output voltage and currents waveforms. THDs of the output voltage and current based on simulations are 2.19% and 0.46%, respectively. The comparison of THDs of output voltage and current in the three topologies shows that increasing the number of levels leads to the multilevel converter producing output voltage waveform with very low THD. Table IV indicates the magnitude of the various powers and the efficiency of the presented 25-level converter. The efficiency of the converter is %93.99. The comparison of the efficiency in 15-level asymmetric converter and 25-level cascade converter shows that the 25-level cascade converter has high efficiency. It means that the power losses in 25-level cascade converter are less than 15-level asymmetric converter. These topologies have been analyzed for different power factors. Table V shows the results for different power factor. In fact, the variation of rms voltage Vl , rms current Il , active power P , and reactive power Q with different load power factor (Cos(ϕ)) for simulated converters is shown in Table V. In this
This paper proposes new topologies for symmetric, asymmetric, and cascade switched-diode multilevel converter with reduced number of components. The proposed cascade structure extends the design flexibility and the possibilities to optimize the converter for different objectives such as the minimization of the number of IGBTs, gate driver circuits, dc voltage sources, standing voltage on switches, and power diodes. Less number of the switches leads to the reduction of size, simple control strategy, and high efficiency. Comparison among the proposed converters with conventional cascade and other similar topologies was provided. It was shown that the proposed topologies can produce many levels with fewer components. R EFERENCES [1] R. Stala, “A natural DC-link voltage balancing of diode-clamped inverters in parallel systems,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 5008– 5018, Nov. 2013. [2] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel power conversion system: A competitive solution for high-power applications,” IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834–841, May/Jun. 2000. [3] R. Alonso, E. Roman, A. Sanz, V. E. M. Santos, and P. Ibanez, “Analysis of inverter-voltage influence on distributed MPPT architecture performance,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3900–3907, Oct. 2012. [4] M. N. A. Kadir, S. Mekhilef, and H. W. Ping, “Voltage vector control of a hybrid three-stage eighteen-level inverter by vector decomposition,” IET Trans. Power Electron., vol. 3, no. 4, pp. 601–611, Jul. 2010. [5] L. M. Tolbert and F. Z. Peng, “Multilevel converters as a utility interface for renewable energy system,” in Proc. IEEE Power Eng. Soc. Summer Meet., 2000, pp. 1271–1274.
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Rasoul Shalchi Alishah was born in Alishah, Iran, in 1989. He received the B.Sc. degree in power electrical engineering from the Azad University of Tabriz, Tabriz, Iran, in 2011 and the M.Sc. degree in power electrical engineering from Urmia University, Urmia, Iran, in 2013. His current research interests include power electronic converters, multilevel converters, Z-source and matrix converters, application of power electronics in renewable energy systems, harmonics, and power quality. Mr. Shalchi Alishah was selected by the Department of Electrical and Computer Engineering of Urmia University as the best student in 2013. Since 2014, he has been a member of the Iran Elites National Foundation. He is the author of more than 20 journal and conference papers. Also, he is a reviewer and Editorial Board member of several international journals.
Daryoosh Nazarpour was born in Urmia, Iran, in 1958. He received the B.Sc. degree from the Iran University of Science and Technology, Tehran, Iran, in 1982 and the M.Sc. and Ph.D. degrees from the Faculty of Engineering, University of Tabriz, Tabriz, Iran, in 1988 and 2005, respectively, all in electrical power engineering. Currently, he is an Assistant Professor in Urmia University. His research interests include power electronics and flexible ac transmission system.
Seyed Hossein Hosseini (M’93) was born in Marand, Iran, in 1953. He received the M.S. degree from the Faculty of Engineering, University of Tabriz, Tabriz, Iran, in 1976; the DEA degree from the Institut National Polytechnique de Lorraine (INPL), Nancy, France, in 1978; and the Ph.D. degree from INPL, France, in 1981, all in electrical engineering. In 1982, he joined the University of Tabriz, Iran, as an Assistant Professor in the Department of Electrical Engineering. From September 1990 to September 1991, he was a Visiting Professor at the University of Queensland, Australia. From 1990 to 1995, he was an Associate Professor in the University of Tabriz. Since 1995, he has been a Professor in the Department of Electrical Engineering, University of Tabriz. From September 1996 to September 1997, he was a Visiting Professor at the University of Western Ontario, London, ON, Canada. His research interests include power electronic converters, matrix converters, active and hybrid filters, application of power electronics in renewable energy systems and electrified railway systems, reactive power control, harmonics, and power quality compensation systems such as SVC, UPQC, and FACTS devices.
Mehran Sabahi (M’09) was born in Tabriz, Iran, in 1968. He received the B.Sc. degree in electronic engineering from the University of Tabriz, Tabriz, Iran; the M.Sc. degree in electrical engineering from Tehran University, Tehran, Iran; and the Ph.D. degree in electrical engineering from the University of Tabriz, in 1991, 1994, and 2009, respectively. In 2009, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz, where he has been an Assistant Professor since 2009. His current research interests include power electronic converters and renewable energy systems.
