Package of integrated circuits and vertical integration
US006322903B1
(12) United States Patent
(10) Patent N0.: (45) Date of Patent:
Siniaguine et al.
(54)
PACKAGE OF INTEGRATED CIRCUITS AND VERTICAL INTEGRATION
(75) Inventors: Oleg Siniaguine; Sergey Savastiouk, both of San Jose, CA (US)
(73) Assignee: Tru-Si Technologies, Inc., Sunnyvale, CA (US) (*)
Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
OTHER PUBLICATIONS
Comp, Pkg.& Mfg. Tech, Part A, vol. 19, No. 4, Dec. 1996,
Int. Cl.7 ................................................... .. H01L 21/44
(52)
US. Cl. ........................ .. 428/617; 438/108; 438/459;
438/977 Field of Search ................................... .. 438/616, 617,
438/118, 107, 112, 108, 113, 615, 119, 618, 315, 455—459, 598, 599 (56)
Anthony, T., “Forming Feedthroughs in Laser—Drilled Holes in Semiconductor Wafers by Double—Sided Sputtering”, IEEE Trans. On Comp, Hybrids,& Mfg. Tech, vol. CHMT—5, No. 1, Mar. 1982, pp. 171—180. Agrikov, U. et al “Dynamical Plasma Treatment of HIC
(Hybrid Integrated Circuits) Substrates”, Electronic Tech niques, Ser. 10, Microelectronic Devices 5(71), 1988, pp. 30—32, Russia.
References Cited
(List continued on neXt page.)
U.S. PATENT DOCUMENTS 3,810,129
5/1974 Behman et al. ............ .. 340/173 DR
3,811,117
5/1974 Anderson, Jr. et al.
3,881,884
5/1975
3,993,917
11/1976
4,368,106
1/1983
4,394,712
7/1983 Anthony
4,463,336
7/1984 Black et al.
4,467,518
8/1984 Bansal et al. ..
4,603,341 4,612,083
7/1986 Bertin et al. ...................... .. 357/237 9/1986 Yasumoto et al. ................. .. 156/633
Cook et al.
...........
340/173 DR . . . . . . . ..
Kalter ....... .. Anthony
Anthony
(EP). (EP). (EP) (W0) (W0) (W0) (W0) (W0). (W0). (WO).
pp. 516—521.
Dec. 6, 1999
(51)
(58)
11/1995 2/1996 7/1996 3/1992 4/1994 11/1994 7/1996 12/1997 12/1997 5/1998
NOV. 27, 2001
Christensen, C., et al. “Wafer Through—Hole Interconnec tions With High Vertical Wiring Densities”, IEEE Trans. On
(21) Appl. N0.: 09/456,225 (22) Filed:
0807964 A1 0698288 B1 0757431 A2 WO 92/03848 WO 94/09513 W0 94/25981 W0 96/21943 W0 97/45856 W0 97/45862 W0 98/19337
US 6,322,903 B1
.....
29/290
Primary Examiner—Charles BoWers Assistant Examiner—Yennhu B. Huynh
(74) Attorney,
Agent,
or
Firm—Skjerven
307/235 . . . . ..
204/15
(57)
ABSTRACT
361/411
4,628,174
12/1986
4,722,130
2/1988
4,769,738
9/1988 Nakamura et al.
4,807,021
2/1989
.........
Kimura et al. . . . . .
..... .. 338/4
A ?rst level packaging Wafer is made of a semiconductor or
29/571
insulating material. The bumps on the Wafer are made using vertical integration technology, Without solder or electro plating. More particularly, vias are etched part Way into a ?rst surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form
. . . . ..
. . . ..
219/76
29/413
361/283
Okumura ............................. .. 357/75
(List continued on neXt page.)
suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
FOREIGN PATENT DOCUMENTS 19707887A1
9/1998
Morrill
MacPherson, LLP; Michael Shenker
29 Claims, 13 Drawing Sheets
US 6,322,903 B1 Page 2
US. PATENT DOCUMENTS
OTHER PUBLICATIONS
4,842,699
6/1989
4,890,784
1/1990 Bampton ............................ .. 228/194
IPEC Precision brochure for PACEJET II (@ 1996 ), 2
4,897,708 4,954,458
1/1990 Clements ............................. .. 357/65 9/1990 Reid ...... .. 437/51
pages
4,978,639
Hua etal. ............................ .. 204/15
12/1990 H119 9t a1~ ----------- ~~
4,996,587
2/1991
5,064,771 5,071,792
- 437/230
Hinrichsmeyer et al.
Siniaguine, Oleg, “Plasma Jet Etching at Atomspheric Pres
357/74
.
.
,,
.
,
.
11/1991 Solomon ................................ .. 437/3 12/1991 VanVonno etal. ................ .. 437/227
Sure for Semlconductor Producnon just Int 1 Symposlum on Plasma Pr0C@SS—II1d11C@d Damage, May 13—14, 1996,
5,160,987
11/1992 Pricer et al.
Santa Clara, CA, pp 151—153_
5,166,097
11/1992
. 257/307
Tanielian ............................ .. 437/203
5,191,405
3/1993 Tomita et al. ..................... .. 257/777
5,225,771
7/1993
Leedy
........... ..
.
AZ Corporation, “Plasma Jet Etching Technology and
324/158
-
.
-
-
-
-
-
-
5,258,330
11/1993 Khandros et al. ................. .. 437/209
Equlpmenti Slhcon Wafer Th1nm_ng & lsotroplcal Etchmg at
5 270 261
12/1993 Bertin et al. ....................... .. 347/209
Atomsphenc
5,307,942
5/1994 Quelfeter et al.
211/26
Pressure”>
Sem1C°n/Eur°Pe>
APR
1995>
Geneva, SWitZerland, 4 pages.
5,309,318
5/1994 Beilstein, Jr. et al.
. 361/689
5,313,097
5/1994 Haj-Ali-Ahmadi et al
. 257/706
M. Amagai, et al., “Development of Chip Scale Packages
5,314,844
5/1994 Imamura ................. ..
. 437/226
(CSP) for Center Pad Devices”, 1997 E16 Ctronic compo_
5,322,816
6/1994
5,323,035
6/1994 Leedy ................................. .. 257/248
5,340,771
8/1994
5,380,681
1/1995 Hsu .................................... .. 437/209
P- E1en1u$>
5,399,898
3/1995 Rostoker ............................ .. 257/499
Electronic Components and Technology Conference, 1997
5,426,566 5,414,637
6/1995 Beilstein, Bertin 'et al. Jr. ..... et al. ..
. 361/735 364/489
9/1995 Leedy
""" "
' 437/203
Matsunami ....... ..
.257/621
534533404
Pinter ................................. .. 437/203 Rostoker .
5,463,246
10/1995
574667634
11/1995 Beilstein’ Jr_ et aL
5,467,305
11/1995 Bertin et al. .................. .. 365/185.01
5,468,663
11/1995
5,478,781
12/1995 Bertin et al.
437/189
2/1996 Gates """""" "
5,494,832
2/1996
575027333 5,502,667
3/1996 Benin et aL 3/1996 Bertin et al.
437/2
_ 257/685 365/51
535173754
5/1996 Bell§tem’ Jr‘ et a1‘
5,532,519
7/1996
8/1996 Sheem
Bertin et al. ..... ..
29/840
al.,
“Chip
Scale
Packaging
5,
Using
_
and Technology Conference, 1997 IEEE, pp. 638—641.
_
tromc Components and Technology Conference, 1997 IEEE, pp. 254—263. L. Levine, “Ball Bumping and Coining Operations for Tab
and Flip Chip”, 1997 Electronic Components and Technol
. 257/777
385/53
5,561,622
10/1996
Bertin et al.
365/51
575637086
“V1996 Benin et aL
437/52
5,567,653
10/1996 Bertin et al. ....................... .. 437/173
5,567,654
10/1996 Beilstein, Jr. et al. ............ .. 437/209
5,571,754 5,596,226
11/1996 Bertin et al. ........ .. . 437/209 1/1997 BellStelIl, Jr. et al. ............ .. 257/690
577427100 5,759,873 5,786,271
et
Bertin et al. ....................... .. 316/705
5,550,942
ogy Conference, 1997 IEEE PP- 265—273 “
_
_
5,
Sara M. Chen, Electroplated Hermetic Fiber , 1998 Elec tronic Conference, 1998 IEEE, p. 418.
L. Li, et al., “Stencil Printing Process Developing for LoW Cost Interconnect”, Electronic Components
Hsu .................................... .. 438/459
8/1997 Leedy 11/1997
Fillion, _
Chip—on—FleX Technology , 1997 Electromc Components
Lead Free Solders for Flip Chip Technology”, 1997 Elec
Lehmann et al. ..
4/1996
5,684,330
5,
J. Kloeser et al. “Fine Pitch Stencil Printing of Sn/Pb and
5/1996 Beilstien, Jr. et al. ............ .. 257/686
4/1997
_
Flex on Cap —S°1der Paste Bumplng > 1997
' 437/208
5,506,753
*
R.
“
. 437/209
5,517,057
576547127
_
Bertin et al. ......................... .. 437/43
5,489,554
5,621,106
nents and Technology Conference> 1997 IEEE PP 343—352~
.437/209
_ 430/315
Lee ............... ..
4/1998 Schroeder et a1_ _ 6/1998 Kata et al. 7/1998 Ohida et al.
.
_ 257/778 . 438/118 . 438/615
5,798,567
8/1998 Kelly et al. ........................ .. 257/723
5,817,541
10/1998 A‘fefklOll et al. .................. .. 438/107
5,831,832
11/1998
Gillette et al. .
and Technology Conference, 1998 IEEE, pp. 421—426.
257/692
. 361/760
_
“
_
_
_
G. Rmne, Solder Bumping Methods for Flip Chip Pack aging”, 1997 Electronic Components and Technology Con ference, 1997 IEEE, PP- 241—247
Shimokawa, et a1, “Micro_ban Bump for _
Intercon_
_
5834 830
11/1998 Cho ___________ __
_ 257/667
nections”, 1998 Electromc Components and Technology
5,843,844
12/1998 Miyanaga
. 438/694
Conference, 1998 IEEE, pp. 1472—1476.
5,858,815
1/1999 Heo etal.
. 438/112
5,862,816
1/1999 Cho ....... ..
. 438/123
5,863,812 5,872,051
2/1999 1/1999 Manteghi Fallon et al............................ ....................... .. 438/108 438/616
Components and Technology Conference, 358—363
5,879,964
3/1999 Paik et al.
5,886,398
3/1999
578897332 5,892,273
3/1999 Lawson et aL 4/1999 IWasaki et al.
5,892,290 5,918,113
6/1999 4/1999 Higashi Chakravorty et al.et .................... al. ... 257/786 438/119
LOW et al.
. 438/113 ..
.
257/667
_ 257/778 . 257/690
5,998,292 12/1999 Black et al. ....................... .. 438/618 6,083,773 * 7/2000 Lake ................................... .. 438/108
Y.C. Teo, “Low Cost Chip—Scale Package”, 1997 Electronic
__
“
_
_
5,
Y. YamaJi, et al., Development of Highly Reliable CSP , 1997 Electronic Components and Technology Conference, ’ * cited by examiner
U.S. Patent
Nov. 27, 2001
Sheet 1 0f 13
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 2 0f 13
US 6,322,903 B1
1508
1508 3 FIG.
1508
150B 230
150v
U.S. Patent
Nov. 27, 2001
Sheet 3 0f 13
US 6,322,903 B1
QZA
mag
.UE mom:
U.S. Patent
Nov. 27, 2001
Sheet 4 0f 13
QIA
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 6 0f 13
Q:
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 7 0f 13
US 6,322,903 B1
9 FIG.
U.S. Patent
Nov. 27, 2001
Sheet 8 0f 13
US 6,322,903 B1
mom? 2
.UE men P
U.S. Patent
Nov. 27, 2001
Sheet 9 0f 13
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
US 6,322,903 B1
Sheet 10 0f 13
0K)
J/\
9:0.1
me?o?
.5NHf?
3.03Q34..
MA\.mg0I)5 2:
32:2
nu
/ ~9:
.uE
(12) United States Patent
(10) Patent N0.: (45) Date of Patent:
Siniaguine et al.
(54)
PACKAGE OF INTEGRATED CIRCUITS AND VERTICAL INTEGRATION
(75) Inventors: Oleg Siniaguine; Sergey Savastiouk, both of San Jose, CA (US)
(73) Assignee: Tru-Si Technologies, Inc., Sunnyvale, CA (US) (*)
Notice:
Subject to any disclaimer, the term of this patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
OTHER PUBLICATIONS
Comp, Pkg.& Mfg. Tech, Part A, vol. 19, No. 4, Dec. 1996,
Int. Cl.7 ................................................... .. H01L 21/44
(52)
US. Cl. ........................ .. 428/617; 438/108; 438/459;
438/977 Field of Search ................................... .. 438/616, 617,
438/118, 107, 112, 108, 113, 615, 119, 618, 315, 455—459, 598, 599 (56)
Anthony, T., “Forming Feedthroughs in Laser—Drilled Holes in Semiconductor Wafers by Double—Sided Sputtering”, IEEE Trans. On Comp, Hybrids,& Mfg. Tech, vol. CHMT—5, No. 1, Mar. 1982, pp. 171—180. Agrikov, U. et al “Dynamical Plasma Treatment of HIC
(Hybrid Integrated Circuits) Substrates”, Electronic Tech niques, Ser. 10, Microelectronic Devices 5(71), 1988, pp. 30—32, Russia.
References Cited
(List continued on neXt page.)
U.S. PATENT DOCUMENTS 3,810,129
5/1974 Behman et al. ............ .. 340/173 DR
3,811,117
5/1974 Anderson, Jr. et al.
3,881,884
5/1975
3,993,917
11/1976
4,368,106
1/1983
4,394,712
7/1983 Anthony
4,463,336
7/1984 Black et al.
4,467,518
8/1984 Bansal et al. ..
4,603,341 4,612,083
7/1986 Bertin et al. ...................... .. 357/237 9/1986 Yasumoto et al. ................. .. 156/633
Cook et al.
...........
340/173 DR . . . . . . . ..
Kalter ....... .. Anthony
Anthony
(EP). (EP). (EP) (W0) (W0) (W0) (W0) (W0). (W0). (WO).
pp. 516—521.
Dec. 6, 1999
(51)
(58)
11/1995 2/1996 7/1996 3/1992 4/1994 11/1994 7/1996 12/1997 12/1997 5/1998
NOV. 27, 2001
Christensen, C., et al. “Wafer Through—Hole Interconnec tions With High Vertical Wiring Densities”, IEEE Trans. On
(21) Appl. N0.: 09/456,225 (22) Filed:
0807964 A1 0698288 B1 0757431 A2 WO 92/03848 WO 94/09513 W0 94/25981 W0 96/21943 W0 97/45856 W0 97/45862 W0 98/19337
US 6,322,903 B1
.....
29/290
Primary Examiner—Charles BoWers Assistant Examiner—Yennhu B. Huynh
(74) Attorney,
Agent,
or
Firm—Skjerven
307/235 . . . . ..
204/15
(57)
ABSTRACT
361/411
4,628,174
12/1986
4,722,130
2/1988
4,769,738
9/1988 Nakamura et al.
4,807,021
2/1989
.........
Kimura et al. . . . . .
..... .. 338/4
A ?rst level packaging Wafer is made of a semiconductor or
29/571
insulating material. The bumps on the Wafer are made using vertical integration technology, Without solder or electro plating. More particularly, vias are etched part Way into a ?rst surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form
. . . . ..
. . . ..
219/76
29/413
361/283
Okumura ............................. .. 357/75
(List continued on neXt page.)
suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.
FOREIGN PATENT DOCUMENTS 19707887A1
9/1998
Morrill
MacPherson, LLP; Michael Shenker
29 Claims, 13 Drawing Sheets
US 6,322,903 B1 Page 2
US. PATENT DOCUMENTS
OTHER PUBLICATIONS
4,842,699
6/1989
4,890,784
1/1990 Bampton ............................ .. 228/194
IPEC Precision brochure for PACEJET II (@ 1996 ), 2
4,897,708 4,954,458
1/1990 Clements ............................. .. 357/65 9/1990 Reid ...... .. 437/51
pages
4,978,639
Hua etal. ............................ .. 204/15
12/1990 H119 9t a1~ ----------- ~~
4,996,587
2/1991
5,064,771 5,071,792
- 437/230
Hinrichsmeyer et al.
Siniaguine, Oleg, “Plasma Jet Etching at Atomspheric Pres
357/74
.
.
,,
.
,
.
11/1991 Solomon ................................ .. 437/3 12/1991 VanVonno etal. ................ .. 437/227
Sure for Semlconductor Producnon just Int 1 Symposlum on Plasma Pr0C@SS—II1d11C@d Damage, May 13—14, 1996,
5,160,987
11/1992 Pricer et al.
Santa Clara, CA, pp 151—153_
5,166,097
11/1992
. 257/307
Tanielian ............................ .. 437/203
5,191,405
3/1993 Tomita et al. ..................... .. 257/777
5,225,771
7/1993
Leedy
........... ..
.
AZ Corporation, “Plasma Jet Etching Technology and
324/158
-
.
-
-
-
-
-
-
5,258,330
11/1993 Khandros et al. ................. .. 437/209
Equlpmenti Slhcon Wafer Th1nm_ng & lsotroplcal Etchmg at
5 270 261
12/1993 Bertin et al. ....................... .. 347/209
Atomsphenc
5,307,942
5/1994 Quelfeter et al.
211/26
Pressure”>
Sem1C°n/Eur°Pe>
APR
1995>
Geneva, SWitZerland, 4 pages.
5,309,318
5/1994 Beilstein, Jr. et al.
. 361/689
5,313,097
5/1994 Haj-Ali-Ahmadi et al
. 257/706
M. Amagai, et al., “Development of Chip Scale Packages
5,314,844
5/1994 Imamura ................. ..
. 437/226
(CSP) for Center Pad Devices”, 1997 E16 Ctronic compo_
5,322,816
6/1994
5,323,035
6/1994 Leedy ................................. .. 257/248
5,340,771
8/1994
5,380,681
1/1995 Hsu .................................... .. 437/209
P- E1en1u$>
5,399,898
3/1995 Rostoker ............................ .. 257/499
Electronic Components and Technology Conference, 1997
5,426,566 5,414,637
6/1995 Beilstein, Bertin 'et al. Jr. ..... et al. ..
. 361/735 364/489
9/1995 Leedy
""" "
' 437/203
Matsunami ....... ..
.257/621
534533404
Pinter ................................. .. 437/203 Rostoker .
5,463,246
10/1995
574667634
11/1995 Beilstein’ Jr_ et aL
5,467,305
11/1995 Bertin et al. .................. .. 365/185.01
5,468,663
11/1995
5,478,781
12/1995 Bertin et al.
437/189
2/1996 Gates """""" "
5,494,832
2/1996
575027333 5,502,667
3/1996 Benin et aL 3/1996 Bertin et al.
437/2
_ 257/685 365/51
535173754
5/1996 Bell§tem’ Jr‘ et a1‘
5,532,519
7/1996
8/1996 Sheem
Bertin et al. ..... ..
29/840
al.,
“Chip
Scale
Packaging
5,
Using
_
and Technology Conference, 1997 IEEE, pp. 638—641.
_
tromc Components and Technology Conference, 1997 IEEE, pp. 254—263. L. Levine, “Ball Bumping and Coining Operations for Tab
and Flip Chip”, 1997 Electronic Components and Technol
. 257/777
385/53
5,561,622
10/1996
Bertin et al.
365/51
575637086
“V1996 Benin et aL
437/52
5,567,653
10/1996 Bertin et al. ....................... .. 437/173
5,567,654
10/1996 Beilstein, Jr. et al. ............ .. 437/209
5,571,754 5,596,226
11/1996 Bertin et al. ........ .. . 437/209 1/1997 BellStelIl, Jr. et al. ............ .. 257/690
577427100 5,759,873 5,786,271
et
Bertin et al. ....................... .. 316/705
5,550,942
ogy Conference, 1997 IEEE PP- 265—273 “
_
_
5,
Sara M. Chen, Electroplated Hermetic Fiber , 1998 Elec tronic Conference, 1998 IEEE, p. 418.
L. Li, et al., “Stencil Printing Process Developing for LoW Cost Interconnect”, Electronic Components
Hsu .................................... .. 438/459
8/1997 Leedy 11/1997
Fillion, _
Chip—on—FleX Technology , 1997 Electromc Components
Lead Free Solders for Flip Chip Technology”, 1997 Elec
Lehmann et al. ..
4/1996
5,684,330
5,
J. Kloeser et al. “Fine Pitch Stencil Printing of Sn/Pb and
5/1996 Beilstien, Jr. et al. ............ .. 257/686
4/1997
_
Flex on Cap —S°1der Paste Bumplng > 1997
' 437/208
5,506,753
*
R.
“
. 437/209
5,517,057
576547127
_
Bertin et al. ......................... .. 437/43
5,489,554
5,621,106
nents and Technology Conference> 1997 IEEE PP 343—352~
.437/209
_ 430/315
Lee ............... ..
4/1998 Schroeder et a1_ _ 6/1998 Kata et al. 7/1998 Ohida et al.
.
_ 257/778 . 438/118 . 438/615
5,798,567
8/1998 Kelly et al. ........................ .. 257/723
5,817,541
10/1998 A‘fefklOll et al. .................. .. 438/107
5,831,832
11/1998
Gillette et al. .
and Technology Conference, 1998 IEEE, pp. 421—426.
257/692
. 361/760
_
“
_
_
_
G. Rmne, Solder Bumping Methods for Flip Chip Pack aging”, 1997 Electronic Components and Technology Con ference, 1997 IEEE, PP- 241—247
Shimokawa, et a1, “Micro_ban Bump for _
Intercon_
_
5834 830
11/1998 Cho ___________ __
_ 257/667
nections”, 1998 Electromc Components and Technology
5,843,844
12/1998 Miyanaga
. 438/694
Conference, 1998 IEEE, pp. 1472—1476.
5,858,815
1/1999 Heo etal.
. 438/112
5,862,816
1/1999 Cho ....... ..
. 438/123
5,863,812 5,872,051
2/1999 1/1999 Manteghi Fallon et al............................ ....................... .. 438/108 438/616
Components and Technology Conference, 358—363
5,879,964
3/1999 Paik et al.
5,886,398
3/1999
578897332 5,892,273
3/1999 Lawson et aL 4/1999 IWasaki et al.
5,892,290 5,918,113
6/1999 4/1999 Higashi Chakravorty et al.et .................... al. ... 257/786 438/119
LOW et al.
. 438/113 ..
.
257/667
_ 257/778 . 257/690
5,998,292 12/1999 Black et al. ....................... .. 438/618 6,083,773 * 7/2000 Lake ................................... .. 438/108
Y.C. Teo, “Low Cost Chip—Scale Package”, 1997 Electronic
__
“
_
_
5,
Y. YamaJi, et al., Development of Highly Reliable CSP , 1997 Electronic Components and Technology Conference, ’ * cited by examiner
U.S. Patent
Nov. 27, 2001
Sheet 1 0f 13
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 2 0f 13
US 6,322,903 B1
1508
1508 3 FIG.
1508
150B 230
150v
U.S. Patent
Nov. 27, 2001
Sheet 3 0f 13
US 6,322,903 B1
QZA
mag
.UE mom:
U.S. Patent
Nov. 27, 2001
Sheet 4 0f 13
QIA
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 6 0f 13
Q:
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
Sheet 7 0f 13
US 6,322,903 B1
9 FIG.
U.S. Patent
Nov. 27, 2001
Sheet 8 0f 13
US 6,322,903 B1
mom? 2
.UE men P
U.S. Patent
Nov. 27, 2001
Sheet 9 0f 13
US 6,322,903 B1
U.S. Patent
Nov. 27, 2001
US 6,322,903 B1
Sheet 10 0f 13
0K)
J/\
9:0.1
me?o?
.5NHf?
3.03Q34..
MA\.mg0I)5 2:
32:2
nu
/ ~9:
.uE
