Paper Title (use style: paper title)
LNA performance optimization with FFT engine Jin Kyung Lee, Jihyeok Ahn, Kyung Ki Kim Department of Electronic Engineering, Daegu University Gyeongsan, South Korea lzq881210@ live.daegu.ac.kr, [email protected], [email protected]
INTRODUCTION
Performance testing and optimization of parameter values after IC fabrication are essential steps to increase the debilitated performance and MTTF from process variation and aging effects of analog and RF circuits. Generally, the more integrated ICs require the more time and cost for performance measurement and tuning process when off-chip equipment is used. Therefore, on-chip built-in calibration (BIC) technique is emerging as an alternative [1], [2]. In this work, design of analog circuit performance tuning is focused, while the cost of LNA tuning circuits is efficiently reduced. Furthermore, the LNA performance is enhanced by estimating the third-order intermodulation (IM3) value which is one of the LNA linearity metrics [3]. In this purpose, frequency domain analysis is required, which leads to design ADC and FFT engine. Consequently, frequency down sampling method is proposed to operate ADC at low frequency to minimize chip area, and optimized FFT engine is designed that consumes smaller area than conventional FFT engines. II.
of silicon area. Figure 3 (a) shows the microphotograph of the test chip. In Figure 3 (b), the first two channels from the logic analyzer waveforms are real and imaginary part of the FFT outputs, respectively. The waveforms are well matched with the simulation results.
Lg2
Cgd2_ext
Ld
Cd
Rd vout
VBIAS
Input
Envelope Detector
LNA
ADC
FFT
M2
(down-converter)
Adjustable Elements within LNA for Linearity Tuning
I.
RBIAS
S3 Cgd2_ext3
Lg C2
S2
C1
S1
vin
C0
Controller
S0
M1
S2 Cgd2_ext2
Cgs1_ext S1 Cgd2_ext1
Registers
Data Signal Control Signal
Ls
IM3 Calculator
Cgd2_ext0
Digital Calibration Unit
Fig. 1. Block diagram of BIC system
Fig. 2. LNA with digitally tunable linearity
DESCRIPTION
A. Description System Architecture Figure 1 displays a block diagram of the proposed calibration method [4]. To estimate the IM3 components of the LNA, a two-tone input signal is applied and the output signal is down-converted through an envelope detector. After the envelope output signal is digitized by the ADC, it is analyzed in frequency domain using an FFT engine with a clock frequency equal to the ADC sampling frequency. B. Design and Implemention In Figure 2, the schematic of the cascode LNA with inductive source degeneration is shown. The changes of Cgd2_ext have minor effects on S11, S21 and noise figure. In this design, Cgd2_ext can be implemented with a fixed capacitor (Cgd2_ext0 = 90fF) and a 3-bit digitally-programmable capacitor (Cgd2_ext1 = 20fF, Cgd2_ext2 = 40fF, and Cgd2_ext3 = 80fF) is also used. III. CHIP IMPLEMENTAION AND RESULTS The LNA performance optimization with FFT engine was designed and fabricated with 0.13μm standard CMOS process. The digital hardware including FFT engine, IM3 calculator, controller and registers was designed with the Verilog hardware description language (Verilog-HDL), and synthesized. The layout of the digital calculation unit occupies 190×190μm2
(a)
(b)
Fig. 3. (a) Die photo of the BIC system, (b) Experimental result from logic analyzer REFERENCE [1]
[2]
[3]
[4]
J.-Y. Ryu, B. Kim, and I. Sylla, “A new low-cost RF built-in self-test measurement for system-on-chip transceivers,” IEEE Trans. Instrum. Meas., vol. 55, no. 2, pp. 381–388, Apr. 2006. N. Ahsan, J. Dabrowski, and A. Ouacha, “A self-tuning technique for optimization of dual band LNA,” in Proc. Eur. Conf. Wirel. Technol., Oct. 2008, pp. 178–181. H. Chauhan, Y. Choi, M. Onabajo, I.-S. Jung, and Y.-B. Kim, “Accurate and efficient on-chip spectral analysis for built-in testing and calibration approaches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 497–506, Mar. 2014. Y. Choi, C-H Chang et al., “A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers,” Circuits and Systems MWSCAS, 2014 IEEE 57th, pp.599,602, 3-6 Aug. 2014
This work was supported by IDEC.
ISOCC 2015 Chip Design Contest
INTRODUCTION
Performance testing and optimization of parameter values after IC fabrication are essential steps to increase the debilitated performance and MTTF from process variation and aging effects of analog and RF circuits. Generally, the more integrated ICs require the more time and cost for performance measurement and tuning process when off-chip equipment is used. Therefore, on-chip built-in calibration (BIC) technique is emerging as an alternative [1], [2]. In this work, design of analog circuit performance tuning is focused, while the cost of LNA tuning circuits is efficiently reduced. Furthermore, the LNA performance is enhanced by estimating the third-order intermodulation (IM3) value which is one of the LNA linearity metrics [3]. In this purpose, frequency domain analysis is required, which leads to design ADC and FFT engine. Consequently, frequency down sampling method is proposed to operate ADC at low frequency to minimize chip area, and optimized FFT engine is designed that consumes smaller area than conventional FFT engines. II.
of silicon area. Figure 3 (a) shows the microphotograph of the test chip. In Figure 3 (b), the first two channels from the logic analyzer waveforms are real and imaginary part of the FFT outputs, respectively. The waveforms are well matched with the simulation results.
Lg2
Cgd2_ext
Ld
Cd
Rd vout
VBIAS
Input
Envelope Detector
LNA
ADC
FFT
M2
(down-converter)
Adjustable Elements within LNA for Linearity Tuning
I.
RBIAS
S3 Cgd2_ext3
Lg C2
S2
C1
S1
vin
C0
Controller
S0
M1
S2 Cgd2_ext2
Cgs1_ext S1 Cgd2_ext1
Registers
Data Signal Control Signal
Ls
IM3 Calculator
Cgd2_ext0
Digital Calibration Unit
Fig. 1. Block diagram of BIC system
Fig. 2. LNA with digitally tunable linearity
DESCRIPTION
A. Description System Architecture Figure 1 displays a block diagram of the proposed calibration method [4]. To estimate the IM3 components of the LNA, a two-tone input signal is applied and the output signal is down-converted through an envelope detector. After the envelope output signal is digitized by the ADC, it is analyzed in frequency domain using an FFT engine with a clock frequency equal to the ADC sampling frequency. B. Design and Implemention In Figure 2, the schematic of the cascode LNA with inductive source degeneration is shown. The changes of Cgd2_ext have minor effects on S11, S21 and noise figure. In this design, Cgd2_ext can be implemented with a fixed capacitor (Cgd2_ext0 = 90fF) and a 3-bit digitally-programmable capacitor (Cgd2_ext1 = 20fF, Cgd2_ext2 = 40fF, and Cgd2_ext3 = 80fF) is also used. III. CHIP IMPLEMENTAION AND RESULTS The LNA performance optimization with FFT engine was designed and fabricated with 0.13μm standard CMOS process. The digital hardware including FFT engine, IM3 calculator, controller and registers was designed with the Verilog hardware description language (Verilog-HDL), and synthesized. The layout of the digital calculation unit occupies 190×190μm2
(a)
(b)
Fig. 3. (a) Die photo of the BIC system, (b) Experimental result from logic analyzer REFERENCE [1]
[2]
[3]
[4]
J.-Y. Ryu, B. Kim, and I. Sylla, “A new low-cost RF built-in self-test measurement for system-on-chip transceivers,” IEEE Trans. Instrum. Meas., vol. 55, no. 2, pp. 381–388, Apr. 2006. N. Ahsan, J. Dabrowski, and A. Ouacha, “A self-tuning technique for optimization of dual band LNA,” in Proc. Eur. Conf. Wirel. Technol., Oct. 2008, pp. 178–181. H. Chauhan, Y. Choi, M. Onabajo, I.-S. Jung, and Y.-B. Kim, “Accurate and efficient on-chip spectral analysis for built-in testing and calibration approaches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 497–506, Mar. 2014. Y. Choi, C-H Chang et al., “A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers,” Circuits and Systems MWSCAS, 2014 IEEE 57th, pp.599,602, 3-6 Aug. 2014
This work was supported by IDEC.
ISOCC 2015 Chip Design Contest
