phase noise and amplitude issues of a wide-band vco utilizing a ...
Phase Noise and Amplitude Issues of a Wide-Band VCO Utilizing a Switched Tuning Resonator Ali Fard M¨alardalen University, Dept. of Computer Science and Electronics, V¨aster˚as, P.O. Box 883 SE-721 23, Sweden Abstract— A 3.5-5.3 GHz, low phase noise CMOS VCO with switched tuning for multi-standard radios is presented in this paper. Design of low phase noise and small amplitude variations across the operating frequency is shown to be important aspects in wide-band VCOs. An analytic expression for the output amplitude of the VCO is derived as a function of the switched capacitor resonator Q. The linear-time variant model was used for prediction of the phase noise and for deciding a proper tank current to achieve the minimum phase noise and amplitude variations across the frequency range. The results are verified in a fully integrated 0.18µm VCO with measured phase noise levels of less than -115 dBc/Hz at 1 MHz offset from the carrier while dissipating 6 mW of power.
I. I NTRODUCTION The explosive development in wireless communication over the past decade has resulted in increasing demands for transceivers operating in frequency ranges from 0.9 to 6 GHz. Much attention is dedicated to integrate entire systems on a single chip so as to yield compact and economical solutions. Although this is cost effective, most of these transceivers are only capable of satisfying one specific communication standard. For a flexible system, it is desirable to support multiple radio standards operating over a wide frequency range with minimal amounts of duplicate hardware. In such systems, the Voltage Controlled Oscillator (VCO) is identified as one of the limiting factors in tuning range, silicon area, power consumption and the primary source of noise. In this paper two important performance aspects, phase noise and amplitude variations, of a wide-band VCO employing a switched capacitor resonator is investigated. Analysis on the output amplitude as a function of the circuit parameters is carried out. The linear-time variant model [1] is adopted for prediction of the phase noise performance in the 1/f 2 region. Based on these results the circuit is optimized for small amplitude variations and low phase noise performance. Finally the measured results are verified and confirmed with the analysis on a fully integrated 3.5-5.3 GHz VCO implemented in a standard 0.18µm CMOS process. II. G ENERAL O SCILLATOR D ESIGN C ONSIDERATIONS In LC-type resonator based oscillators, active devices are used to generate a negative resistance to cancel the losses and providing the conditions for oscillation. There are some generally important trade-offs in deciding the transconductance cell for a given LC-tank quality factor (Q). Previous research [2] shows that if the negative resistance is too large it may contribute with excess thermal noise and thus deteriorate the
0-7803-8834-8/05/$20.00 ©2005 IEEE.
Fig. 1.
Simplified VCO circuit schematic with a discrete switched tuning.
phase noise. The thermal noise is in fact becoming one of the main issues in modern wireless applications, especially in high data rate communications (such as 802.11 a/g) where the channel bandwidth is increased to satisfy the restrictions. These requirements puts high demands on the VCO phase noise performance at high frequency offsets (i.e. 1/f 2 region) where the noise is dominated by the tank Q and the oscillation amplitude. In [2] it is shown that for a given transconductance cell an optimum in phase noise is achieved as long as the output amplitude is a linear function of the tank current and Q. Once this minimum region is passed, further increments in tank current only results in increased thermal noise of the actives which in turn deteriorates the phase noise. Now, considering a wide-band VCO, a different challenge is present since the transconductance cell may not easily be optimized, due to the variations of Q across the frequency range. III. W IDE -BAND VCO D ESIGN The VCO topology, depicted in Fig. 1, is realized in a 0.18µm CMOS process. It consists of a two-turn circular inductor, MOS accumulation varactors and a binary weighted switched capacitor array (SCA) for frequency tuning. The cross-coupled NMOS and PMOS transistor pairs in positive feedback provide a negative resistance which compensate for the tank resistive losses. A simple current mirror is used for biasing purpose and sets the current in the resonator. The VCO is targeted for high data rate multi-band transceivers in the 5 GHz band (such as 802.11a) and operating at the double frequency of the 2.4 GHz ISM-band (802.11 b/g). In order to achieve a carrier signal for the 2.4 GHz band, the idea is to utilize the high frequency divide-by-two circuits that are normally implemented in a frequency synthesizer [3]. By using this technique, quadrature signals may be obtained, depending on the topology of the frequency divider, and
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Cmin =
Fig. 2.
1 2n−1 C
+
1
−1
2n−1 Cd
,
(3)
where Cd is the drain parasitic capacitance of the switches during their off-state. Once these two boundaries are defined, we may design the switches controlling the capacitors. For a given process and overdrive voltage the sizes of the switches are found by combining (2) and (3), which gives the maximum tolerable parasitics for a given tuning range for each switch,
Circuit schematic of the differential SCA.
nevertheless lowering the phase noise (ideally) by 6 dB. Due to the wide tuning restrictions for the VCO, both discrete and continues tuning is employed here. This approach increases the tuning range, while ensuring a low sensitivity to noise on the tuning path. However, this technique brings two major design aspects that significantly affects the VCO performance. First, the on-state resistance of the digitally controlled switches are degrading the overall Q of the resonator. Second, the parasitic capacitance from the switches during their off-state reduces the maximum achievable oscillating frequency which is devastating in low supply voltage designs and as will be shown here, also has negative impact on the amplitude. As for the SCA, the differential tuning scheme [4], depicted in Fig. 2, is implemented for the coarse tuning. IV. R ESONATOR D ESIGN AND P REDICTION OF THE O UTPUT A MPLITUDE Using the SCA for main frequency tuning affects the output amplitude levels across the frequency range. Since the VCO is designed to operate in the current limited region [2], the output amplitude is roughly given by 4 (1) Vo = · Ibias · RT AN K π where Ibias is the resonator current and RT AN K the equivalent resonance impedance. Using (1) the output amplitude may be attained, however, we need to find an expression for the tank Q. It is well-known that the inductor Q has the dominant role in the overall tank Q and needs to be optimized carefully. In this implementation the Q of the inductor is only improved as the frequency is raised within the range of 3-6 GHz, ranging between 5-8 (simulated). However, at lower operation frequency (3.5-4.5 GHz) a large number of capacitors with their belonging control switches are active which has some impact on the Q. First, we need to gain some understanding for how to design the SCA to achieve a certain tuning range. The minimum operation frequency is√given by the maximum capacitance according to f0 = 1/2π LCmax . Since the varactors gain is usually set by the demands on the frequency synthesizer loop, we assume here that a fixed gain is desired within the entire tuning range. Thereby we may ignore the varactors and the parasitic capacitance involved and express the maximum capacitance Cmax contributions from the SCA as, (2) Cmax = (2n − 1) · C, where C is the resolution capacitance. In the same manner the minimum capacitance Cmin is,
Cd =
Cmax · Cmin . (2n − 1)(Cmax − Cmin )
(4)
By using the simple equations for the inductor QL = ω0 ·L/Rs and perform an impedance transformation and define the losses as a parallel resistance with the inductor given by RL = Q2 · Rs . The same approach may be used for expressing a single switched capacitor element using QC = 1/(ω0 ·Ron ·C) and the equivalent parallel resistance of RC = Q2 · Ron . Now suppose that the binary weighted SCA consist of n-elements that are all active, then the equivalent parallel resistance RT AN K of the resonator may be expressed as RT AN K =
QL · ω0 · L · QC 2 · Ron (2n − 1) · QL · ω0 · L + QC 2 Ron
(5)
By combining (1) and (5) the output amplitude of the oscillator for a given Ibias is achieved, for the extreme conditions where either all switches are on or off. Moreover, using (5) the significant contributions to degradation of RT AN K in a switched resonator is obtained. It also shows how the tuning range of a switched resonator may be traded for small amplitude variations. Now considering the variations of QL , that are strongly frequency dependent, and the overall RT AN K the trade-offs involved for design of the SCA are highlighted. In order to achieve a wide tuning range of 2 GHz, the entire frequency band is divided in smaller bands, by using n = 6. For a fixed varactor gain and tuning range the capacitance overlap for coverage of process variations mainly determines n and C. As shown in (5) n has an important impact on the relative RT AN K variations determining the amplitude variations across the tuning range. For instance, for a Ibias , if a tuning of 50% is desired, using optimally sized switches with 30% capacitance overlap, a ratio of two between minimum and maximum output amplitude should be expected. Thus in order to reduce the amplitude variations for a given tuning range, the capacitance overlap safety margin or the number of elements should be reduced together with the parasitics. Furthermore, a balance between reduced capacitance overlap and varactors Cmax /Cmin ratio should be considered for reduction of relative amplitude changes, while ensuring sufficient coverage for process related variation. V. P HASE N OISE IN 1/f 2 REGION In this section, we concentrate on the 1/f 2 phase noise of the VCO, while assuming that the previous discussions and issues for reducing the amplitude variations are considered. The linear-time variant (LTV) model [1] is adopted here for the prediction of phase noise of the VCO. Central in the
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LTV model is the impulse sensitive function (ISF), which is a measure of the phase perturbation caused by an impulse injected into the circuit at any time during an oscillation period. The ISF is a dimension less periodic function that describes the conversion of noise sources to an excess phase at output of the oscillator. In [1] extensive analysis shows that the phase noise of an oscillator in the 1/f 2 region may be given by, 2 in · Γ2rms ∆f , (6) L(∆ω) = 10 log 2 2qmax ∆ω 2 where i¯2n /∆f is the total mean square noise current spectral density per hertz of the noise sources present, qmax is the maximum charge swing across the equivalent capacitance in the output node, ∆ω is the offset angular frequency from the carrier, Γrms is the rms value of the ISF (Γ). The ISF may be obtained numerically by using time domain simulations. However, in [5] a closed-form expression for the ISF associated with the tank resistance (ΓR,N ) was derived under very ideal circumstances, sin ω0 t , (7) ΓR,N = N where N is the number of phases in the oscillator (N = 2 for a differential). Using the well-known expression for the noise contributions of the effective tank resistance, given by i2n,tank
=
4kT
(8) ∆f RT AN K where k is the Boltzmanns constant and T is the temperature, we may find the closed formulation for the phase noise caused by RT AN K [5]. Combining Eq. (6)-(8) we may express the phase noise generated by RT AN K for a given frequency and oscillation amplitude. Ideally, the main noise contributions in 1/f 2 region is dominated by the tank generated noise. However, in practice, the transconductance cell also contribute with significant amount of noise. The noise power density of the transistors
i2n,device ∆f
may be modelled as,
i2n,device ∆f
=
i2d,nmos ∆f
+
i2d,pmos ∆f
(9)
i2
where d,mos is the channel induced noise of the MOS tran∆f sistors. These noise sources may be described by, i2d,mos
= 4kT γgm , (10) ∆f where γ is the device noise coefficient. In general the active noise sources are cyclostationary due to the time-variant nature of the oscillator. Therefore [1] defines an effective ISF that both contains the stationary and the time duration of the presence of the noise source given by, Γrms,ef f (φ) = Γrms (φ) · α(φ)
(11)
where α(φ) represents the cyclostationary noise function. In order to simplify the analysis the tail current transistor is
replaced with an ideal current source, and the total noise contribution is calculated using the above derived equations. For the cyclostationary noise sources, time domain simulation may be performed by injecting a perturbation into the oscillator over a single oscillation cycle and measuring the excess phase shift. The amount of charge injected must be carefully determined in such a manner so that the linearity assumption of the system is satisfied. The results obtained using the LTVmodel may easily be verified with the spectreRF simulations, where it is also possible to find the noise contributions NL from each element in the circuit. By taking into account all the noise contributions, the phase noise may be expressed as the ratio between the noise power and oscillation amplitude, NL L(∆ω) = 10 log . (12) Vo2 /2 As suggested in [5], combining Eq. (6) and (12), we may find the noise contribution of a certain noise component according to, i2n 2 ∆f · Γrms . (13) NL = 4C 2 ∆ω 2 The above derivation is used for verification of the calculated noise sources with spectreRF simulations. Finally, it is possible to determine the biasing conditions and sizing of the actives for proper oscillation across the entire frequency band, with regards on the tank Q variations. It was observed that the lowest phase noise performance could be achieved by finding a ratio between the PMOS and NMOS transistors that minimized their relative noise contributions and also satisfying the startup conditions. Furthermore, in order to minimize the relative amplitude variations, the bias current was chosen so that the VCO is operated in the current-limited region [2] for a large frequency range and in the ”weak” voltage limited region only at the top frequency band. This is satisfied for a tank current of 4 mA from 1.5 V supply voltage, and a PMOS to NMOS ratio of approximately 3. Under these bias conditions the relative noise contributions from the tank are near 44%, the NMOS pair contributions are 20%, and the PMOS pair contribute with almost 36% of the total noise at 1 MHz offset at 5 GHz carrier frequency. The calculated phase noise levels are -118 - -121 dBc/Hz at 1 MHz offset along the frequency range. These calculations agree within 2 dBc/Hz to the complete schematic simulations including buffers and the tail current mirror. VI. M EASUREMENTS Measurements on the prototype circuits have been performed on a gold plated FR4 PCB to which the die, depicted in Fig. 3, is wire-bonded to. The frequency characteristics and output power was measured using a Rhode & Schwarz FSEM30 spectrum analyzer and for the phase noise measurements a PN9000 system was used. The VCO is able to operate within 1.8 GHz frequency band, ranging between 3.5 to 5.3 GHz. The output power was as predicted in simulations increased as the bias current was increased up to 6 mA. Several phase noise measurements were performed at different carrier frequencies all indicating that the optimum bias point
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Fig. 3.
Fig. 4.
Chip photo of the 0.85 x 0.55 mm 0.18µm CMOS VCO.
Fig. 5.
Measured phase noise at 4.5 GHz.
Fig. 6.
Measured phase noise at 5.3 GHz.
Measured phase noise from 3.8 GHz carrier consuming 6 mW.
is around 3.5-4 mA from 1.5 V supply, which are in good agreement with the calculations and simulations. As for the output amplitude, the lowest variations was obtained for a tank current larger than 5 mA. Meanwhile for this bias current the phase noise was slightly degraded at the top frequency band and only marginally improved at frequencies below 4.5 GHz, since the VCO is operated in the voltage-limited region at the top frequency band. One other significant source for the degradation of phase noise at the top frequency band for large bias currents, could be tracked to the AM-PM conversion, indicating that there is still a strong impact from the varactors. This effect is less dominant on the lower operation frequencies since additional MIM capacitors, by means of the SCA, reduces the gain of the varactors and also the oscillation amplitude. Thus, as a compromise a bias current of 4 mA was chosen, providing with acceptable phase noise levels and amplitude variations of ≈ 40% across the tuning range. Figure 4, 5 and 6 shows the entire single-sideband phase noise for a 3.8, 4.5 and 5.3 GHz carrier respectively. The phase noise at 1 MHz offset is -115 dBc/Hz or less across the operation frequency. These measurements agree within 3 dBc to the schematic simulations. VII. C ONCLUSIONS A highly flexible wide-band CMOS VCO, utilizing switched tuning was presented. The implementation aspects, in particular amplitude and phase noise, was analyzed and verified against simulations. It highlights the important issues and trade-offs for the design of wide-band VCOs. Moreover, discussions on proper the tank current for reduction of amplitude variations and low phase noise has been addressed. The results were demonstrated in a 6 mW VCO with 1.8 GHz tuning range, displaying phase noise levels of less than -115 dBc/Hz at 1 MHz offset, suited for high data rate multi-standard radios.
VIII. ACKNOWLEDGMENT This study is supported by Acreo AB within the SoCWare program and funded partially by NorFA. The author is grateful to Note Norrt¨alje AB for the bonding and to Rohde & Schwarz for providing with a spectrum analyzer. A special thanks to Dr. H. Sj¨oland, F. Tillman and N. Troedsson, Dept. of Electroscience, Lund University for their help with the phase noise measurements and to Dr. P. Andreani, Technical University of Denmark, for fruitful and inspiring conversations on VCOs. R EFERENCES [1] A. Hajimiri and T.H. Lee, A General Theory of Phase Noise in Electrical Oscillators, IEEE Journal of Solid-State Circuits, Vol. 33, No. 2 February 1998. [2] D. Ham and A. Hajimiri, Concepts and Methods in Optimization of Integrated LC VCOs, IEEE Journal of Solid-State Circuits, Vol. 36, No. 6 June 2001. ˚ [3] A. Fard, T. Johnson and D. Aberg Design of a Dual-Band 5/2.4 GHz CMOS VCO for 802.11 a/b/g WLAN Transceivers, Proc. of IEEE Asia-Pacific Conf. on Circuits and Systems, Dec 2004, Taiwan [4] H. Sj¨oland, Improved Switched Tuning of Differential CMOS VCOs, IEEE Transactions on Circuits and Systems, Analog and Digital Signal Processing, Vol. 49, No. 5. May 2002 [5] P. Andreani and X. Wang, On the phase-noise and phase-error performances of multiphase LC CMOS VCOs, IEEE Journal of Solid-State Circuits, Vol. 39, no. 11 November 2004.
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I. I NTRODUCTION The explosive development in wireless communication over the past decade has resulted in increasing demands for transceivers operating in frequency ranges from 0.9 to 6 GHz. Much attention is dedicated to integrate entire systems on a single chip so as to yield compact and economical solutions. Although this is cost effective, most of these transceivers are only capable of satisfying one specific communication standard. For a flexible system, it is desirable to support multiple radio standards operating over a wide frequency range with minimal amounts of duplicate hardware. In such systems, the Voltage Controlled Oscillator (VCO) is identified as one of the limiting factors in tuning range, silicon area, power consumption and the primary source of noise. In this paper two important performance aspects, phase noise and amplitude variations, of a wide-band VCO employing a switched capacitor resonator is investigated. Analysis on the output amplitude as a function of the circuit parameters is carried out. The linear-time variant model [1] is adopted for prediction of the phase noise performance in the 1/f 2 region. Based on these results the circuit is optimized for small amplitude variations and low phase noise performance. Finally the measured results are verified and confirmed with the analysis on a fully integrated 3.5-5.3 GHz VCO implemented in a standard 0.18µm CMOS process. II. G ENERAL O SCILLATOR D ESIGN C ONSIDERATIONS In LC-type resonator based oscillators, active devices are used to generate a negative resistance to cancel the losses and providing the conditions for oscillation. There are some generally important trade-offs in deciding the transconductance cell for a given LC-tank quality factor (Q). Previous research [2] shows that if the negative resistance is too large it may contribute with excess thermal noise and thus deteriorate the
0-7803-8834-8/05/$20.00 ©2005 IEEE.
Fig. 1.
Simplified VCO circuit schematic with a discrete switched tuning.
phase noise. The thermal noise is in fact becoming one of the main issues in modern wireless applications, especially in high data rate communications (such as 802.11 a/g) where the channel bandwidth is increased to satisfy the restrictions. These requirements puts high demands on the VCO phase noise performance at high frequency offsets (i.e. 1/f 2 region) where the noise is dominated by the tank Q and the oscillation amplitude. In [2] it is shown that for a given transconductance cell an optimum in phase noise is achieved as long as the output amplitude is a linear function of the tank current and Q. Once this minimum region is passed, further increments in tank current only results in increased thermal noise of the actives which in turn deteriorates the phase noise. Now, considering a wide-band VCO, a different challenge is present since the transconductance cell may not easily be optimized, due to the variations of Q across the frequency range. III. W IDE -BAND VCO D ESIGN The VCO topology, depicted in Fig. 1, is realized in a 0.18µm CMOS process. It consists of a two-turn circular inductor, MOS accumulation varactors and a binary weighted switched capacitor array (SCA) for frequency tuning. The cross-coupled NMOS and PMOS transistor pairs in positive feedback provide a negative resistance which compensate for the tank resistive losses. A simple current mirror is used for biasing purpose and sets the current in the resonator. The VCO is targeted for high data rate multi-band transceivers in the 5 GHz band (such as 802.11a) and operating at the double frequency of the 2.4 GHz ISM-band (802.11 b/g). In order to achieve a carrier signal for the 2.4 GHz band, the idea is to utilize the high frequency divide-by-two circuits that are normally implemented in a frequency synthesizer [3]. By using this technique, quadrature signals may be obtained, depending on the topology of the frequency divider, and
2691
Cmin =
Fig. 2.
1 2n−1 C
+
1
−1
2n−1 Cd
,
(3)
where Cd is the drain parasitic capacitance of the switches during their off-state. Once these two boundaries are defined, we may design the switches controlling the capacitors. For a given process and overdrive voltage the sizes of the switches are found by combining (2) and (3), which gives the maximum tolerable parasitics for a given tuning range for each switch,
Circuit schematic of the differential SCA.
nevertheless lowering the phase noise (ideally) by 6 dB. Due to the wide tuning restrictions for the VCO, both discrete and continues tuning is employed here. This approach increases the tuning range, while ensuring a low sensitivity to noise on the tuning path. However, this technique brings two major design aspects that significantly affects the VCO performance. First, the on-state resistance of the digitally controlled switches are degrading the overall Q of the resonator. Second, the parasitic capacitance from the switches during their off-state reduces the maximum achievable oscillating frequency which is devastating in low supply voltage designs and as will be shown here, also has negative impact on the amplitude. As for the SCA, the differential tuning scheme [4], depicted in Fig. 2, is implemented for the coarse tuning. IV. R ESONATOR D ESIGN AND P REDICTION OF THE O UTPUT A MPLITUDE Using the SCA for main frequency tuning affects the output amplitude levels across the frequency range. Since the VCO is designed to operate in the current limited region [2], the output amplitude is roughly given by 4 (1) Vo = · Ibias · RT AN K π where Ibias is the resonator current and RT AN K the equivalent resonance impedance. Using (1) the output amplitude may be attained, however, we need to find an expression for the tank Q. It is well-known that the inductor Q has the dominant role in the overall tank Q and needs to be optimized carefully. In this implementation the Q of the inductor is only improved as the frequency is raised within the range of 3-6 GHz, ranging between 5-8 (simulated). However, at lower operation frequency (3.5-4.5 GHz) a large number of capacitors with their belonging control switches are active which has some impact on the Q. First, we need to gain some understanding for how to design the SCA to achieve a certain tuning range. The minimum operation frequency is√given by the maximum capacitance according to f0 = 1/2π LCmax . Since the varactors gain is usually set by the demands on the frequency synthesizer loop, we assume here that a fixed gain is desired within the entire tuning range. Thereby we may ignore the varactors and the parasitic capacitance involved and express the maximum capacitance Cmax contributions from the SCA as, (2) Cmax = (2n − 1) · C, where C is the resolution capacitance. In the same manner the minimum capacitance Cmin is,
Cd =
Cmax · Cmin . (2n − 1)(Cmax − Cmin )
(4)
By using the simple equations for the inductor QL = ω0 ·L/Rs and perform an impedance transformation and define the losses as a parallel resistance with the inductor given by RL = Q2 · Rs . The same approach may be used for expressing a single switched capacitor element using QC = 1/(ω0 ·Ron ·C) and the equivalent parallel resistance of RC = Q2 · Ron . Now suppose that the binary weighted SCA consist of n-elements that are all active, then the equivalent parallel resistance RT AN K of the resonator may be expressed as RT AN K =
QL · ω0 · L · QC 2 · Ron (2n − 1) · QL · ω0 · L + QC 2 Ron
(5)
By combining (1) and (5) the output amplitude of the oscillator for a given Ibias is achieved, for the extreme conditions where either all switches are on or off. Moreover, using (5) the significant contributions to degradation of RT AN K in a switched resonator is obtained. It also shows how the tuning range of a switched resonator may be traded for small amplitude variations. Now considering the variations of QL , that are strongly frequency dependent, and the overall RT AN K the trade-offs involved for design of the SCA are highlighted. In order to achieve a wide tuning range of 2 GHz, the entire frequency band is divided in smaller bands, by using n = 6. For a fixed varactor gain and tuning range the capacitance overlap for coverage of process variations mainly determines n and C. As shown in (5) n has an important impact on the relative RT AN K variations determining the amplitude variations across the tuning range. For instance, for a Ibias , if a tuning of 50% is desired, using optimally sized switches with 30% capacitance overlap, a ratio of two between minimum and maximum output amplitude should be expected. Thus in order to reduce the amplitude variations for a given tuning range, the capacitance overlap safety margin or the number of elements should be reduced together with the parasitics. Furthermore, a balance between reduced capacitance overlap and varactors Cmax /Cmin ratio should be considered for reduction of relative amplitude changes, while ensuring sufficient coverage for process related variation. V. P HASE N OISE IN 1/f 2 REGION In this section, we concentrate on the 1/f 2 phase noise of the VCO, while assuming that the previous discussions and issues for reducing the amplitude variations are considered. The linear-time variant (LTV) model [1] is adopted here for the prediction of phase noise of the VCO. Central in the
2692
LTV model is the impulse sensitive function (ISF), which is a measure of the phase perturbation caused by an impulse injected into the circuit at any time during an oscillation period. The ISF is a dimension less periodic function that describes the conversion of noise sources to an excess phase at output of the oscillator. In [1] extensive analysis shows that the phase noise of an oscillator in the 1/f 2 region may be given by, 2 in · Γ2rms ∆f , (6) L(∆ω) = 10 log 2 2qmax ∆ω 2 where i¯2n /∆f is the total mean square noise current spectral density per hertz of the noise sources present, qmax is the maximum charge swing across the equivalent capacitance in the output node, ∆ω is the offset angular frequency from the carrier, Γrms is the rms value of the ISF (Γ). The ISF may be obtained numerically by using time domain simulations. However, in [5] a closed-form expression for the ISF associated with the tank resistance (ΓR,N ) was derived under very ideal circumstances, sin ω0 t , (7) ΓR,N = N where N is the number of phases in the oscillator (N = 2 for a differential). Using the well-known expression for the noise contributions of the effective tank resistance, given by i2n,tank
=
4kT
(8) ∆f RT AN K where k is the Boltzmanns constant and T is the temperature, we may find the closed formulation for the phase noise caused by RT AN K [5]. Combining Eq. (6)-(8) we may express the phase noise generated by RT AN K for a given frequency and oscillation amplitude. Ideally, the main noise contributions in 1/f 2 region is dominated by the tank generated noise. However, in practice, the transconductance cell also contribute with significant amount of noise. The noise power density of the transistors
i2n,device ∆f
may be modelled as,
i2n,device ∆f
=
i2d,nmos ∆f
+
i2d,pmos ∆f
(9)
i2
where d,mos is the channel induced noise of the MOS tran∆f sistors. These noise sources may be described by, i2d,mos
= 4kT γgm , (10) ∆f where γ is the device noise coefficient. In general the active noise sources are cyclostationary due to the time-variant nature of the oscillator. Therefore [1] defines an effective ISF that both contains the stationary and the time duration of the presence of the noise source given by, Γrms,ef f (φ) = Γrms (φ) · α(φ)
(11)
where α(φ) represents the cyclostationary noise function. In order to simplify the analysis the tail current transistor is
replaced with an ideal current source, and the total noise contribution is calculated using the above derived equations. For the cyclostationary noise sources, time domain simulation may be performed by injecting a perturbation into the oscillator over a single oscillation cycle and measuring the excess phase shift. The amount of charge injected must be carefully determined in such a manner so that the linearity assumption of the system is satisfied. The results obtained using the LTVmodel may easily be verified with the spectreRF simulations, where it is also possible to find the noise contributions NL from each element in the circuit. By taking into account all the noise contributions, the phase noise may be expressed as the ratio between the noise power and oscillation amplitude, NL L(∆ω) = 10 log . (12) Vo2 /2 As suggested in [5], combining Eq. (6) and (12), we may find the noise contribution of a certain noise component according to, i2n 2 ∆f · Γrms . (13) NL = 4C 2 ∆ω 2 The above derivation is used for verification of the calculated noise sources with spectreRF simulations. Finally, it is possible to determine the biasing conditions and sizing of the actives for proper oscillation across the entire frequency band, with regards on the tank Q variations. It was observed that the lowest phase noise performance could be achieved by finding a ratio between the PMOS and NMOS transistors that minimized their relative noise contributions and also satisfying the startup conditions. Furthermore, in order to minimize the relative amplitude variations, the bias current was chosen so that the VCO is operated in the current-limited region [2] for a large frequency range and in the ”weak” voltage limited region only at the top frequency band. This is satisfied for a tank current of 4 mA from 1.5 V supply voltage, and a PMOS to NMOS ratio of approximately 3. Under these bias conditions the relative noise contributions from the tank are near 44%, the NMOS pair contributions are 20%, and the PMOS pair contribute with almost 36% of the total noise at 1 MHz offset at 5 GHz carrier frequency. The calculated phase noise levels are -118 - -121 dBc/Hz at 1 MHz offset along the frequency range. These calculations agree within 2 dBc/Hz to the complete schematic simulations including buffers and the tail current mirror. VI. M EASUREMENTS Measurements on the prototype circuits have been performed on a gold plated FR4 PCB to which the die, depicted in Fig. 3, is wire-bonded to. The frequency characteristics and output power was measured using a Rhode & Schwarz FSEM30 spectrum analyzer and for the phase noise measurements a PN9000 system was used. The VCO is able to operate within 1.8 GHz frequency band, ranging between 3.5 to 5.3 GHz. The output power was as predicted in simulations increased as the bias current was increased up to 6 mA. Several phase noise measurements were performed at different carrier frequencies all indicating that the optimum bias point
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Fig. 3.
Fig. 4.
Chip photo of the 0.85 x 0.55 mm 0.18µm CMOS VCO.
Fig. 5.
Measured phase noise at 4.5 GHz.
Fig. 6.
Measured phase noise at 5.3 GHz.
Measured phase noise from 3.8 GHz carrier consuming 6 mW.
is around 3.5-4 mA from 1.5 V supply, which are in good agreement with the calculations and simulations. As for the output amplitude, the lowest variations was obtained for a tank current larger than 5 mA. Meanwhile for this bias current the phase noise was slightly degraded at the top frequency band and only marginally improved at frequencies below 4.5 GHz, since the VCO is operated in the voltage-limited region at the top frequency band. One other significant source for the degradation of phase noise at the top frequency band for large bias currents, could be tracked to the AM-PM conversion, indicating that there is still a strong impact from the varactors. This effect is less dominant on the lower operation frequencies since additional MIM capacitors, by means of the SCA, reduces the gain of the varactors and also the oscillation amplitude. Thus, as a compromise a bias current of 4 mA was chosen, providing with acceptable phase noise levels and amplitude variations of ≈ 40% across the tuning range. Figure 4, 5 and 6 shows the entire single-sideband phase noise for a 3.8, 4.5 and 5.3 GHz carrier respectively. The phase noise at 1 MHz offset is -115 dBc/Hz or less across the operation frequency. These measurements agree within 3 dBc to the schematic simulations. VII. C ONCLUSIONS A highly flexible wide-band CMOS VCO, utilizing switched tuning was presented. The implementation aspects, in particular amplitude and phase noise, was analyzed and verified against simulations. It highlights the important issues and trade-offs for the design of wide-band VCOs. Moreover, discussions on proper the tank current for reduction of amplitude variations and low phase noise has been addressed. The results were demonstrated in a 6 mW VCO with 1.8 GHz tuning range, displaying phase noise levels of less than -115 dBc/Hz at 1 MHz offset, suited for high data rate multi-standard radios.
VIII. ACKNOWLEDGMENT This study is supported by Acreo AB within the SoCWare program and funded partially by NorFA. The author is grateful to Note Norrt¨alje AB for the bonding and to Rohde & Schwarz for providing with a spectrum analyzer. A special thanks to Dr. H. Sj¨oland, F. Tillman and N. Troedsson, Dept. of Electroscience, Lund University for their help with the phase noise measurements and to Dr. P. Andreani, Technical University of Denmark, for fruitful and inspiring conversations on VCOs. R EFERENCES [1] A. Hajimiri and T.H. Lee, A General Theory of Phase Noise in Electrical Oscillators, IEEE Journal of Solid-State Circuits, Vol. 33, No. 2 February 1998. [2] D. Ham and A. Hajimiri, Concepts and Methods in Optimization of Integrated LC VCOs, IEEE Journal of Solid-State Circuits, Vol. 36, No. 6 June 2001. ˚ [3] A. Fard, T. Johnson and D. Aberg Design of a Dual-Band 5/2.4 GHz CMOS VCO for 802.11 a/b/g WLAN Transceivers, Proc. of IEEE Asia-Pacific Conf. on Circuits and Systems, Dec 2004, Taiwan [4] H. Sj¨oland, Improved Switched Tuning of Differential CMOS VCOs, IEEE Transactions on Circuits and Systems, Analog and Digital Signal Processing, Vol. 49, No. 5. May 2002 [5] P. Andreani and X. Wang, On the phase-noise and phase-error performances of multiphase LC CMOS VCOs, IEEE Journal of Solid-State Circuits, Vol. 39, no. 11 November 2004.
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