Phase noise in a back-gate biased low-voltage VCO - ifi
Phase Noise in a Back-Gate Biased Low-Voltage VCO Mehdi H . Kazemeini, M. Jamal Deen, and Susan Naseh Department of Electrical and Computer Engineering, CRL 226 McMasterUniversity, Hamilton, Ontario, Canada, L8S 4K1 E-mail: [email protected]
ABSTRACT The phase noise in an ultra low-power and low-voltage CMOS voltage controlled oscillator (VCO) has been measured and modelled for supply voltage VDD from 1.8 V down to 80 mV with various body bias voltages V B The ~ VCO is a fully integrated ring oscillator designed in a 0.18pm CMOS technology. In this design, the frequency can be controlled by VBp The effects of scaling VDD together with the effect of VBs on the phase noise are examined experimentally and theoretically. It has been observed that the phase noise at VDD>0.5 V is dominated by the upconverted l/f noise. But the low frequency noise disappears when VDDdecreases below 0.5 V. Application of forward body bias voltages from 0 to 0.6 V also provides a practical method to suppress the low frequency noise being upconverted to phase noise.
WpM0s/WNM0s=3.39. This size adjustment was chosen from simulations in order to obtain a symmetrical voltage transfer characteristic at supply voltage VDD=1.8 V. C, in Fig. 1 is not an extra component. It represents an effective loading capacitance on each node, due to the gate and parasitic capacitances of each pair of inverters. The frequency of the VCO is controlled by both body bias voltages applied to BP and BN separately, and also by the supply voltage.VDD. The range of VDD is from 80mV to a maximum of 1.W. and the body bias voltage varies from 0 to 0.6V in the forward direction and from 0 to l.5V in the reverse direction. Phase noise measurements (noise power per hertz) were performcd with two different spectrum analyzers. HP8594E was used for VDD>O.SV (strong inversion) with various VBr AgilemE4440A was used for VDD
ABSTRACT The phase noise in an ultra low-power and low-voltage CMOS voltage controlled oscillator (VCO) has been measured and modelled for supply voltage VDD from 1.8 V down to 80 mV with various body bias voltages V B The ~ VCO is a fully integrated ring oscillator designed in a 0.18pm CMOS technology. In this design, the frequency can be controlled by VBp The effects of scaling VDD together with the effect of VBs on the phase noise are examined experimentally and theoretically. It has been observed that the phase noise at VDD>0.5 V is dominated by the upconverted l/f noise. But the low frequency noise disappears when VDDdecreases below 0.5 V. Application of forward body bias voltages from 0 to 0.6 V also provides a practical method to suppress the low frequency noise being upconverted to phase noise.
WpM0s/WNM0s=3.39. This size adjustment was chosen from simulations in order to obtain a symmetrical voltage transfer characteristic at supply voltage VDD=1.8 V. C, in Fig. 1 is not an extra component. It represents an effective loading capacitance on each node, due to the gate and parasitic capacitances of each pair of inverters. The frequency of the VCO is controlled by both body bias voltages applied to BP and BN separately, and also by the supply voltage.VDD. The range of VDD is from 80mV to a maximum of 1.W. and the body bias voltage varies from 0 to 0.6V in the forward direction and from 0 to l.5V in the reverse direction. Phase noise measurements (noise power per hertz) were performcd with two different spectrum analyzers. HP8594E was used for VDD>O.SV (strong inversion) with various VBr AgilemE4440A was used for VDD
