Programming Algorithms for Multilevel Phase ... - Semantic Scholar
Programming Algorithms for Multilevel Phase-Change Memory N. Papandreou∗ , H. Pozidis∗ , A. Pantazi∗ , A. Sebastian∗ , M. Breitwisch† , C. Lam† and E. Eleftheriou∗ Research – Zurich, CH-8803 Ruschlikon, Switzerland, email: [email protected] T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY 10598
BL
BL
Phase-change memory (PCM) has emerged recently as a new nonvolatile solid-state memory technology with the potential to play a broad role in the entire storage hierarchy due to its universal characteristics spanning from memoryto storage-centric requirements [1]. Multilevel cell (MLC) storage is a crucial feature for increasing the memory capacity and thus enhancing the cost-per-bit competitiveness of PCM technology. Low-latency programming is a requirement in memory-type applications, i.e., DRAM replacement or caching. Furthermore, high endurance in terms of supported programming cycles is an enabling feature in both memorycaching as well as enterprise-storage applications. Finally, embedded applications necessitate low overall energy consumption, which is dominated by the write operation. Some of the above-listed requirements are at least partially conflicting, thus careful design of the programming algorithm is important in achieving a good balance of attributes depending on the intended application. Process and material variability issues cause variations in the bottom electrode contact size and the active memory element across arrays of cells. As a result, the same programming pulse applied to an ensemble of cells gives rise to different temperature profiles within the active storage element in each cell, and thus different resulting resistances. Therefore, single-pulse programming is in general not a viable option for MLC storage because the resulting resistance distributions can be broad. The most common solution is to employ iterative programming strategies, in which a sequence of write-andverify (WAV) steps is used in a feedback loop in order to
PCM Storage Element
PCE BL
WL
S/L GND
c-GST a-GST
W/L WL WL<M>
S
D
(a) 10
10
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ON
Threshold Switching
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from SET from RESET
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1 Voltage (V)
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I. I NTRODUCTION
BL
WL
log10(R) (Ω)
Abstract— Phase-change memory (PCM) has emerged as one among the most promising technologies for next-generation nonvolatile solid-state memory. Multilevel storage, namely storage of non-binary information in a memory cell, is a key factor for reducing the total cost-per-bit and thus increasing the competitiveness of PCM technology in the nonvolatile memory market. In this paper, we present a family of advanced programming schemes for multilevel storage in PCM. The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energyper-bit and cell storage capacity. Experimental results from PCM test-arrays are presented to validate the proposed programming schemes. In addition, the reliability issues of multilevel PCM in terms of resistance drift and read noise are discussed.
Current (A)
∗ IBM † IBM
1.5
3.5 0
from RESET from SET 0.5
1
1.5 2 Vg (V)
2.5
3
(c)
Fig. 1. PCM cell characteristics: (a) schematic of the memory array and cell, (b) I-V characteristic showing threshold switching and snap-back, (c) programming curve starting from either the RESET or the SET state; here the programming current is controlled by the voltage at the gate of the FET.
minimize the error between the programmed and a specified target resistance level [2]. MLC storage is then achieved by accurately programming the PCM cell to multiple intermediate resistance levels between the RESET (high resistance) and SET (low resistance) states. II. PCM P ROGRAMMING C HARACTERISTICS Fig. 1(a) shows a circuit schematic and TEM picture of a PCM cell that consists of the active phase-change element (PCE), sandwiched between a top and bottom electrode, and a FET as the selection device in a memory array structure. Fig. 1(b) shows the current-voltage (I-V) characteristic when the PCM cell is programmed at RESET and SET state. From RESET, the current increases with the voltage following a nonlinear law. When a critical voltage is reached, a characteristic voltage drop (snap-back) is observed and the cell switches rapidly to a highly conductive state, which is called dynamic ON state. This phenomenon is known as threshold switching and is fundamental in enabling the programming of the memory cell from a highly resistive state to a low resistive one [3]. From SET, the I-V characteristic follows a highly conductive path. Therefore, cell programming, i.e., phase switching, is achieved in the ON regime via appropriate Joule heating and quenching, whereas cell read-out is performed in the socalled OFF regime, i.e., at a bias voltage well below the
(a)
40
Vprog(k) Adaptive PCM programming cell algorithm
Percentage of Cells (%)
RTARGET R(k)
e(k)
(b)
0 4.5
Switching: LPS RPS
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RTARGET
6 10
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LPS 10
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5.5 log(R) [Ω]
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error margin
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Fig. 3. Histogram of test-array resistance after programming in 16 resistance levels using the hybrid programming scheme.
1
1.5 2 Vg (Volt)
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Fig. 2. Iterative programming: (a) schematic illustrating the basic iterative programming concept, (b) hybrid programming scheme exploiting both left (LPS) and right (RPS) programming slopes.
STD - cycles
Resistance (Ohm)
10
7
1
10
20
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Fig. 4.
threshold switching voltage in order to avoid disturbance of the GST phase. For multilevel storage, the programming space is defined by the characteristic programming curve, which quantifies the change of the cell resistance as a function of the programming current or voltage. Fig. 1(c) shows the typical programming curve obtained with rectangular programming pulses of increasing amplitude, when programming starts from the RESET or the SET state. III. M ULTILEVEL P ROGRAMMING S CHEMES Conventionally, MLC programming starts with a RESET pulse and then the active memory element is progressively crystallized with a series of pulses of increasing current in the partial-SET regime (down-going slope of the programming curve) [4]. It should be noted that by partial-SET pulses the resistance of the cell may only be decreased; in order to increase the resistance new amorphous volume needs to be created, thus melting has to be invoked. Alternatively, programming may start with a SET pulse and then melting pulses of varying amplitude in the partial-RESET regime (upgoing slope of the programming curve) are used to increase or decrease the resistance [5]. A novel iterative programming scheme that uses both partial-SET and partial-RESET pulses is depicted in Fig. 2. Operation starts from the partial-SET regime and either terminates there if the target resistance is reached, or switches to the partial-RESET regime if the programmed resistance drops below the target level. Switching is effectively enabled by the U-shape of the programming curve and is realized by applying an appropriate current or voltage pulse that shifts the programming sequence to the up-going right slope. The
LPS
RPS
HYBRID
1
Normalized average power (a.u.)
10
30
Comparison of iterative programming schemes.
method combines the low energy dissipation of the partialSET regime (voltage/current pulses of low amplitude) with the bi-directional flexibility of the partial-RESET regime, where resistance can be either increased or decreased due to renewed melting. Additionally, a favorable tradeoff between programming latency (convergence in a few steps in the left-slope) and robustness of convergence (utilization of both programming regimes for resilience to variability) is achieved. This method has been demonstrated experimentally to achieve a high density of target levels and tight distributions of programmed resistances, as shown in Fig. 3. A comparison of the proposed hybrid iterative scheme with the above-mentioned conventional programming strategies has also been performed; results are shown in Fig. 4 in terms of the standard deviation in the average number of algorithm iterations, which indicates a scheme’s robustness to cell variability, and normalized average power dissipation. It can be seen that the new hybrid scheme performs favorably in comparison to the conventional schemes in both metrics. Given a three-terminal access device, such as a FET in Fig. 5(a), the programming current flowing to the cell can be controlled by the word-line (WL) and/or the bit-line (BL) voltage. Fig. 5(b) shows a three-dimensional programming surface for a PCM cell obtained by biasing the FET access device at different gate voltages and simultaneously varying the drain voltage. By proper selection of a small set of biasing conditions, e.g., gate voltages for a FET, a new multipletrajectory and multi-level current-control algorithm can be realized for MLC programming (Fig. 5(c-d)). The proposed method effectively splits the total programming window into
2.5
(b)
constant Vg
2 Id (mA)
BL
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Fig. 5. Multi-trajectory current control: (a) schematic of the PCM cell and characteristics of the access device showing different current control options, (b) 3-D PCM cell programming surface, (c) programming curves with Vd as a variable and Vg as a parameter showing the concept of multiple trajectories, (d) schematic illustrating a possible implementation of the proposed scheme.
Fig. 6. Two-dimensional programming: I-V curves corresponding to different cell states programmed using either (a) the left or (b) the right slope of the programming curve, (c) normalized cell resistance as a function of the equivalent amorphous volume in the left and right slopes, (d) illustration of 16-levels storage.
regions, each of which is covered by a different programming trajectory; finally, the target resistance levels are allocated to the different programming regions. Among the characteristics of this method are an adjustable programming current/voltage window per target level, which affects the resolution of the iterative algorithm, and an efficient target level allocation, which among others reduces the number of over-shooting events as a result of effective current limitation in each trajectory. Due to the more efficient current control, the proposed method also exhibits faster speed of convergence in comparison to conventional schemes. In PCM cells, as the active memory element is in the crystalline phase after device processing, it is mainly the volume and topology of the amorphous phase that determines the state of the cell in MLC storage [6], [7]. Analysis of experimental I-V measurements for different cell states (Figs. 6(a-b)) shows that the effective amorphous thickness (assumed proportional to the volume) in the active element depends on the type of the programming pulse, i.e., partial-SET or partial-RESET pulse (Fig. 6(c)). A two-dimensional (2-D) programming scheme in which the cell state is defined not only by the resistance value, but also by the type of the programming pulse employed has been devised. Experimental results in Fig. 6(d) show the ability of the 2-D scheme to store 8 levels in each of two programming regimes (partial-SET or partial-RESET) and to retrieve 16 levels of information using an appropriate read-out scheme, thus doubling the PCM cell storage capacity. The programming schemes described above rely on data converters and digital logic blocks for implementation. This leads to significant latency and power consumption. An analog iterative programming scheme has been conceived that addresses these issues. The essential idea is to implement the measurement of the current error and the subsequent
corrections to the amplitude of the write pulse in the analog domain. The programming waveform applied to the cell is a repetition of a pulse form consisting of a low-amplitude part that demarcates the read phase and a high-amplitude part used for programming (Fig. 7). During the read phase the error with respect to the target current is calculated and then integrated to produce the corrected output that will be applied during the subsequent write phase. This process continues until the current error is within an acceptable margin. A proof-ofconcept experiment was performed using discrete electronic components to achieve 16 distinct resistance levels (Fig. 8). Depending on implementation, the proposed analog iterative programming scheme may achieve significant savings in power dissipation as well as latency compared with conventional digital schemes. V(t)
read part
Write Offset Signal
write part Vw(k+1)
+ + V(t)
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PCM CELL
IREF t
Vdd tgst ua Vg
(a)
I(t)
Write Offset Signal + Write Enable Signal
Read Enable Signal
Write Enable Signal
Read Enable Signal Integrator (c)
Fig. 7. Analog iterative programming concept: (a) pulse waveform comprising read and write phases, (b) schematic illustrating a possible implementation of the scheme, (c) analog waveforms used in (b).
(a)
Vdd Offset Signal
Write Enable Signal
Read Enable Signal
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Write Enable
Vdd Offset
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Fig. 8. Analog iterative programming experiment: (a) schematic showing an implementation using discrete components, (b-c) oscilloscope traces showing the voltage signals during the write phase, (d) histogram of programmed cell resistances at algorithm’s termination.
IV. R ESISTANCE D RIFT AND N OISE
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Resistance drift (Fig. 9) is a characteristic phenomenon observed in phase-change memory cells, which manifests itself as a steady increase in the electrical resistance of the stored cell-state over time [8]. The RESET state exhibits more drift than the SET state, thus drift may not pose a problem to binary PCM storage as the margin between resistance levels increases with time. However, drift adversely affects the reliability of MLC storage in PCM, because the distance between adjacent levels is small and stochastic fluctuations of the resistance are more likely to cause level overlap over time. As it has been shown in Section III, experimental results on test arrays verified that the proposed MLC schemes are able to produce tight and dense resistance distributions. However, additional signal processing, coding and materials research will be required to effectively address the issue of resistance drift. Noise during reading of PCM cells is an additional impairment affecting the reliability of stored levels. Read noise is of low frequency (1/f γ ) nature, as shown in Fig. 10, and occasionally exhibits random telegraph signal steps of moderate amplitude, which may appear in all cell states [9]. These phenomena have implications for the optimal placement of target levels for reliable MLC storage and may offer key clues as to the origin of noise in PCM technology.
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4
10 FREQUENCY (Hz)
5
10
Write Part: Final Cycle
(c)
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6 5 4
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1 2 log(t)
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Fig. 9. Evolution of the resistance with time (in log-log scale) for five different PCM cells each of which is programmed in different resistance levels.
Fig. 10. Power spectral density of the readback current signal from a PCM cell programmed in three distinct levels showing power-law behavior.
V. C ONCLUSIONS Iterative write-and-verify algorithms are one viable route to multilevel cell storage in phase-change memory as they effectively combat cell variability. A catalog of such programming schemes has been presented that lead to tight packing of resistance levels, while simultaneously achieving low latency, low energy/bit, and high robustness to cell variability. The performance of these schemes has been demonstrated by experimental results on test memory arrays. It has been argued that the reliability of multilevel-cell storage in phase-change memory is adversely affected by resistance drift and cell read noise, which need to be addressed by a consorted effort in new materials, coding and signal-processing research. ACKNOWLEDGMENTS We acknowledge the support of the entire PCM team at IBM. We especially thank U. Egger at IBM Zurich Research Laboratory for helping bring up the characterization setup. R EFERENCES [1] S. Raoux et al., “Phase-change random access memory: A scalable technology,” IBM J. Res. Dev., vol. 52, no. 4/5, pp. 465–479, 2008. [2] T. Nirschl et al., “Write strategies for 2 and 4-bit multi-level phase-change memory,” in IEDM Tech. Dig., 2007, pp. 461–464. [3] Redaelli, A. Pirovano, F. Pellizzer, A. Lacaita, D. Ielmini, and R. Bez, “Electronic switching effect and phase-change transition in chalcogenide materials,” IEEE Electron Dev. Lett., vol. 25, no. 10, pp. 684–686, 2004. [4] F. Bedeschi et al., “A bipolar-selected phase change memory featuring multi-level cell storage,” IEEE J. Solid-State Circ., vol. 44, no. 1, pp. 217–227, Jan. 2009. [5] I. Karpov and S. Kostylev, “SET to RESET programming in phase change memories,” IEEE Elect. Dev. Lett., vol. 27, pp. 808–810, Oct. 2006. [6] A. Itri, D. Ielmini, A. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories,” in Proc. IEEE IRPS, 2004, pp. 209–215. [7] N. Papandreou, A. Pantazi, A. Sebastian, E. Eleftheriou, M. Breitwisch, C. Lam, and H. Pozidis, “Estimation of amorphous fraction in multilevel phase-change memory cells,” in Proc. ESSDERC, 2009, pp. 209–212. [8] A. Pirovano, A. Lacaita, F. Pellizzer, S. Kostylev, A. Benvenuti, and R. Bez, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 714–719, May 2004. [9] P. Fantini, G. Beneventi, A. Calderoni, L. Larcher, P. Pavan, and F. Pellizzer, “Characterization and modelling of low-frequency noise in PCM devices,” in IEDM Tech. Dig., 2008, pp. 219–222.
BL
BL
Phase-change memory (PCM) has emerged recently as a new nonvolatile solid-state memory technology with the potential to play a broad role in the entire storage hierarchy due to its universal characteristics spanning from memoryto storage-centric requirements [1]. Multilevel cell (MLC) storage is a crucial feature for increasing the memory capacity and thus enhancing the cost-per-bit competitiveness of PCM technology. Low-latency programming is a requirement in memory-type applications, i.e., DRAM replacement or caching. Furthermore, high endurance in terms of supported programming cycles is an enabling feature in both memorycaching as well as enterprise-storage applications. Finally, embedded applications necessitate low overall energy consumption, which is dominated by the write operation. Some of the above-listed requirements are at least partially conflicting, thus careful design of the programming algorithm is important in achieving a good balance of attributes depending on the intended application. Process and material variability issues cause variations in the bottom electrode contact size and the active memory element across arrays of cells. As a result, the same programming pulse applied to an ensemble of cells gives rise to different temperature profiles within the active storage element in each cell, and thus different resulting resistances. Therefore, single-pulse programming is in general not a viable option for MLC storage because the resulting resistance distributions can be broad. The most common solution is to employ iterative programming strategies, in which a sequence of write-andverify (WAV) steps is used in a feedback loop in order to
PCM Storage Element
PCE BL
WL
S/L GND
c-GST a-GST
W/L WL WL<M>
S
D
(a) 10
10
7
-4
ON
Threshold Switching
6.5
-5
6
10
10
-6
-7
5.5 5 4.5
10
-8
from SET from RESET
OFF 10
4
-9
0
0.5
1 Voltage (V)
(b)
I. I NTRODUCTION
BL
WL
log10(R) (Ω)
Abstract— Phase-change memory (PCM) has emerged as one among the most promising technologies for next-generation nonvolatile solid-state memory. Multilevel storage, namely storage of non-binary information in a memory cell, is a key factor for reducing the total cost-per-bit and thus increasing the competitiveness of PCM technology in the nonvolatile memory market. In this paper, we present a family of advanced programming schemes for multilevel storage in PCM. The proposed schemes are based on iterative write-and-verify algorithms that exploit the unique programming characteristics of PCM in order to achieve significant improvements in resistance-level packing density, robustness to cell variability, programming latency, energyper-bit and cell storage capacity. Experimental results from PCM test-arrays are presented to validate the proposed programming schemes. In addition, the reliability issues of multilevel PCM in terms of resistance drift and read noise are discussed.
Current (A)
∗ IBM † IBM
1.5
3.5 0
from RESET from SET 0.5
1
1.5 2 Vg (V)
2.5
3
(c)
Fig. 1. PCM cell characteristics: (a) schematic of the memory array and cell, (b) I-V characteristic showing threshold switching and snap-back, (c) programming curve starting from either the RESET or the SET state; here the programming current is controlled by the voltage at the gate of the FET.
minimize the error between the programmed and a specified target resistance level [2]. MLC storage is then achieved by accurately programming the PCM cell to multiple intermediate resistance levels between the RESET (high resistance) and SET (low resistance) states. II. PCM P ROGRAMMING C HARACTERISTICS Fig. 1(a) shows a circuit schematic and TEM picture of a PCM cell that consists of the active phase-change element (PCE), sandwiched between a top and bottom electrode, and a FET as the selection device in a memory array structure. Fig. 1(b) shows the current-voltage (I-V) characteristic when the PCM cell is programmed at RESET and SET state. From RESET, the current increases with the voltage following a nonlinear law. When a critical voltage is reached, a characteristic voltage drop (snap-back) is observed and the cell switches rapidly to a highly conductive state, which is called dynamic ON state. This phenomenon is known as threshold switching and is fundamental in enabling the programming of the memory cell from a highly resistive state to a low resistive one [3]. From SET, the I-V characteristic follows a highly conductive path. Therefore, cell programming, i.e., phase switching, is achieved in the ON regime via appropriate Joule heating and quenching, whereas cell read-out is performed in the socalled OFF regime, i.e., at a bias voltage well below the
(a)
40
Vprog(k) Adaptive PCM programming cell algorithm
Percentage of Cells (%)
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Fig. 3. Histogram of test-array resistance after programming in 16 resistance levels using the hybrid programming scheme.
1
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2.5
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Fig. 2. Iterative programming: (a) schematic illustrating the basic iterative programming concept, (b) hybrid programming scheme exploiting both left (LPS) and right (RPS) programming slopes.
STD - cycles
Resistance (Ohm)
10
7
1
10
20
1
Fig. 4.
threshold switching voltage in order to avoid disturbance of the GST phase. For multilevel storage, the programming space is defined by the characteristic programming curve, which quantifies the change of the cell resistance as a function of the programming current or voltage. Fig. 1(c) shows the typical programming curve obtained with rectangular programming pulses of increasing amplitude, when programming starts from the RESET or the SET state. III. M ULTILEVEL P ROGRAMMING S CHEMES Conventionally, MLC programming starts with a RESET pulse and then the active memory element is progressively crystallized with a series of pulses of increasing current in the partial-SET regime (down-going slope of the programming curve) [4]. It should be noted that by partial-SET pulses the resistance of the cell may only be decreased; in order to increase the resistance new amorphous volume needs to be created, thus melting has to be invoked. Alternatively, programming may start with a SET pulse and then melting pulses of varying amplitude in the partial-RESET regime (upgoing slope of the programming curve) are used to increase or decrease the resistance [5]. A novel iterative programming scheme that uses both partial-SET and partial-RESET pulses is depicted in Fig. 2. Operation starts from the partial-SET regime and either terminates there if the target resistance is reached, or switches to the partial-RESET regime if the programmed resistance drops below the target level. Switching is effectively enabled by the U-shape of the programming curve and is realized by applying an appropriate current or voltage pulse that shifts the programming sequence to the up-going right slope. The
LPS
RPS
HYBRID
1
Normalized average power (a.u.)
10
30
Comparison of iterative programming schemes.
method combines the low energy dissipation of the partialSET regime (voltage/current pulses of low amplitude) with the bi-directional flexibility of the partial-RESET regime, where resistance can be either increased or decreased due to renewed melting. Additionally, a favorable tradeoff between programming latency (convergence in a few steps in the left-slope) and robustness of convergence (utilization of both programming regimes for resilience to variability) is achieved. This method has been demonstrated experimentally to achieve a high density of target levels and tight distributions of programmed resistances, as shown in Fig. 3. A comparison of the proposed hybrid iterative scheme with the above-mentioned conventional programming strategies has also been performed; results are shown in Fig. 4 in terms of the standard deviation in the average number of algorithm iterations, which indicates a scheme’s robustness to cell variability, and normalized average power dissipation. It can be seen that the new hybrid scheme performs favorably in comparison to the conventional schemes in both metrics. Given a three-terminal access device, such as a FET in Fig. 5(a), the programming current flowing to the cell can be controlled by the word-line (WL) and/or the bit-line (BL) voltage. Fig. 5(b) shows a three-dimensional programming surface for a PCM cell obtained by biasing the FET access device at different gate voltages and simultaneously varying the drain voltage. By proper selection of a small set of biasing conditions, e.g., gate voltages for a FET, a new multipletrajectory and multi-level current-control algorithm can be realized for MLC programming (Fig. 5(c-d)). The proposed method effectively splits the total programming window into
2.5
(b)
constant Vg
2 Id (mA)
BL
8
1.5 1 0.5
Icell
PCE
0 0
1
2 Vd (V)
3
4
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2 Id (mA)
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log(R) (Ohm)
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SEL(RREF) PCE Vg1
WL
READ UNIT
VgN 2
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Fig. 5. Multi-trajectory current control: (a) schematic of the PCM cell and characteristics of the access device showing different current control options, (b) 3-D PCM cell programming surface, (c) programming curves with Vd as a variable and Vg as a parameter showing the concept of multiple trajectories, (d) schematic illustrating a possible implementation of the proposed scheme.
Fig. 6. Two-dimensional programming: I-V curves corresponding to different cell states programmed using either (a) the left or (b) the right slope of the programming curve, (c) normalized cell resistance as a function of the equivalent amorphous volume in the left and right slopes, (d) illustration of 16-levels storage.
regions, each of which is covered by a different programming trajectory; finally, the target resistance levels are allocated to the different programming regions. Among the characteristics of this method are an adjustable programming current/voltage window per target level, which affects the resolution of the iterative algorithm, and an efficient target level allocation, which among others reduces the number of over-shooting events as a result of effective current limitation in each trajectory. Due to the more efficient current control, the proposed method also exhibits faster speed of convergence in comparison to conventional schemes. In PCM cells, as the active memory element is in the crystalline phase after device processing, it is mainly the volume and topology of the amorphous phase that determines the state of the cell in MLC storage [6], [7]. Analysis of experimental I-V measurements for different cell states (Figs. 6(a-b)) shows that the effective amorphous thickness (assumed proportional to the volume) in the active element depends on the type of the programming pulse, i.e., partial-SET or partial-RESET pulse (Fig. 6(c)). A two-dimensional (2-D) programming scheme in which the cell state is defined not only by the resistance value, but also by the type of the programming pulse employed has been devised. Experimental results in Fig. 6(d) show the ability of the 2-D scheme to store 8 levels in each of two programming regimes (partial-SET or partial-RESET) and to retrieve 16 levels of information using an appropriate read-out scheme, thus doubling the PCM cell storage capacity. The programming schemes described above rely on data converters and digital logic blocks for implementation. This leads to significant latency and power consumption. An analog iterative programming scheme has been conceived that addresses these issues. The essential idea is to implement the measurement of the current error and the subsequent
corrections to the amplitude of the write pulse in the analog domain. The programming waveform applied to the cell is a repetition of a pulse form consisting of a low-amplitude part that demarcates the read phase and a high-amplitude part used for programming (Fig. 7). During the read phase the error with respect to the target current is calculated and then integrated to produce the corrected output that will be applied during the subsequent write phase. This process continues until the current error is within an acceptable margin. A proof-ofconcept experiment was performed using discrete electronic components to achieve 16 distinct resistance levels (Fig. 8). Depending on implementation, the proposed analog iterative programming scheme may achieve significant savings in power dissipation as well as latency compared with conventional digital schemes. V(t)
read part
Write Offset Signal
write part Vw(k+1)
+ + V(t)
Vw(k)
Vr(k)
(b)
Vw(k+2)
Vr(k+1)
PCM CELL
IREF t
Vdd tgst ua Vg
(a)
I(t)
Write Offset Signal + Write Enable Signal
Read Enable Signal
Write Enable Signal
Read Enable Signal Integrator (c)
Fig. 7. Analog iterative programming concept: (a) pulse waveform comprising read and write phases, (b) schematic illustrating a possible implementation of the scheme, (c) analog waveforms used in (b).
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Read Enable Signal
+ +
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R=102 kOhm R=116 kOhm R=121 kOhm
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+ REF
Vdd
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PSD (A2/Hz)
10 Vg Signal
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Write Part: First Cycle
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Write Enable
Vdd Offset
Vg
γ=1.09 −19
10
−20
10 Vdd
−21
10
2
10
Fig. 8. Analog iterative programming experiment: (a) schematic showing an implementation using discrete components, (b-c) oscilloscope traces showing the voltage signals during the write phase, (d) histogram of programmed cell resistances at algorithm’s termination.
IV. R ESISTANCE D RIFT AND N OISE
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Resistance drift (Fig. 9) is a characteristic phenomenon observed in phase-change memory cells, which manifests itself as a steady increase in the electrical resistance of the stored cell-state over time [8]. The RESET state exhibits more drift than the SET state, thus drift may not pose a problem to binary PCM storage as the margin between resistance levels increases with time. However, drift adversely affects the reliability of MLC storage in PCM, because the distance between adjacent levels is small and stochastic fluctuations of the resistance are more likely to cause level overlap over time. As it has been shown in Section III, experimental results on test arrays verified that the proposed MLC schemes are able to produce tight and dense resistance distributions. However, additional signal processing, coding and materials research will be required to effectively address the issue of resistance drift. Noise during reading of PCM cells is an additional impairment affecting the reliability of stored levels. Read noise is of low frequency (1/f γ ) nature, as shown in Fig. 10, and occasionally exhibits random telegraph signal steps of moderate amplitude, which may appear in all cell states [9]. These phenomena have implications for the optimal placement of target levels for reliable MLC storage and may offer key clues as to the origin of noise in PCM technology.
6
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10 FREQUENCY (Hz)
5
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Write Part: Final Cycle
(c)
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6 5 4
0
1 2 log(t)
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Fig. 9. Evolution of the resistance with time (in log-log scale) for five different PCM cells each of which is programmed in different resistance levels.
Fig. 10. Power spectral density of the readback current signal from a PCM cell programmed in three distinct levels showing power-law behavior.
V. C ONCLUSIONS Iterative write-and-verify algorithms are one viable route to multilevel cell storage in phase-change memory as they effectively combat cell variability. A catalog of such programming schemes has been presented that lead to tight packing of resistance levels, while simultaneously achieving low latency, low energy/bit, and high robustness to cell variability. The performance of these schemes has been demonstrated by experimental results on test memory arrays. It has been argued that the reliability of multilevel-cell storage in phase-change memory is adversely affected by resistance drift and cell read noise, which need to be addressed by a consorted effort in new materials, coding and signal-processing research. ACKNOWLEDGMENTS We acknowledge the support of the entire PCM team at IBM. We especially thank U. Egger at IBM Zurich Research Laboratory for helping bring up the characterization setup. R EFERENCES [1] S. Raoux et al., “Phase-change random access memory: A scalable technology,” IBM J. Res. Dev., vol. 52, no. 4/5, pp. 465–479, 2008. [2] T. Nirschl et al., “Write strategies for 2 and 4-bit multi-level phase-change memory,” in IEDM Tech. Dig., 2007, pp. 461–464. [3] Redaelli, A. Pirovano, F. Pellizzer, A. Lacaita, D. Ielmini, and R. Bez, “Electronic switching effect and phase-change transition in chalcogenide materials,” IEEE Electron Dev. Lett., vol. 25, no. 10, pp. 684–686, 2004. [4] F. Bedeschi et al., “A bipolar-selected phase change memory featuring multi-level cell storage,” IEEE J. Solid-State Circ., vol. 44, no. 1, pp. 217–227, Jan. 2009. [5] I. Karpov and S. Kostylev, “SET to RESET programming in phase change memories,” IEEE Elect. Dev. Lett., vol. 27, pp. 808–810, Oct. 2006. [6] A. Itri, D. Ielmini, A. Lacaita, A. Pirovano, F. Pellizzer, and R. Bez, “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories,” in Proc. IEEE IRPS, 2004, pp. 209–215. [7] N. Papandreou, A. Pantazi, A. Sebastian, E. Eleftheriou, M. Breitwisch, C. Lam, and H. Pozidis, “Estimation of amorphous fraction in multilevel phase-change memory cells,” in Proc. ESSDERC, 2009, pp. 209–212. [8] A. Pirovano, A. Lacaita, F. Pellizzer, S. Kostylev, A. Benvenuti, and R. Bez, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 714–719, May 2004. [9] P. Fantini, G. Beneventi, A. Calderoni, L. Larcher, P. Pavan, and F. Pellizzer, “Characterization and modelling of low-frequency noise in PCM devices,” in IEDM Tech. Dig., 2008, pp. 219–222.
