Reduce Energy Requirements by Coupling a Poly
Reduce Energy Requirements by Coupling a PolyPhase Pre-filter and CIC Filter in High-Performance Sigma-Delta A/D Converters fredric j harris Electrical and Computer Engineering Department San Diego State University, San Diego, CA 92182, USA [email protected]
INTRODUCTION The CIC filter has gained wide acceptance as a process that efficiently performs a common multirate signal processing task; that of increasing or decreasing the sample rate of a time sequence without use of multipliers. The CIC is the core building block, for instance, in the down-sampling or up-sampling process in digital down converters (DDC) and digital up-converters (DUC) respectively [1]. The attraction of the CIC is twofold: first the resampling operation is embedded in the filter between the multiple integrator stages and the multiple derivative filter stages. The second is that the filtering is performed with only registers and adders; there being no multipliers in the CIC filter chain. These same attributes have motivated us to similarly apply the CIC filter to the task of bandwidth and sample rate reduction of the time series formed at the output of a 1-bit sigma-delta analog-to-digital converter. We can easily recognize that the CIC is not the only filter structure that can perform the filtering task on the output of a 1-bit sigma delta converter. In fact every FIR filter processing a 1-bit data sequence can be implemented
DESIGN OF FILTER FREQUENCY RESPONSE We now examine a FIR filter implementation of a CIC like impulse response and then embed an M-to-1 resampler in the FIR filter as is done in the CIC conversion to the Hogenauer filter implementation [2]. As a specific example we consider a 5stage CIC filter supporting 16-to-1 down sampling with an output sample rate 8-times the desired alias free bandwidth with 120 dB dynamic range. Figure shows the amplitude normalized impulse and frequency responses of this CIC filter. Impulse Response, 5-Stage 16-to-1 Down Sample, CIC Filter 1
Amplitude
Keywords—CIC Filter, Coupled Polyphase & CIC Filters
without multipliers. This is because the data samples being limited to plus one or minus one, can at most; change the sign of the coefficients, but not their size, as they are added to the filter’s accumulator. The CIC filter does not take advantage of the fact that the input samples are limited to plus or minus one. We now examine a number of FIR filter architectures that use the unique pair of bipolar input values to implement multiply free filters. We also present design considerations that assure these FIR filters have comparable performance and computational workload as the CIC filter. We show how we can couple the two filters, the multiply free binary input FIR filter with the multiply free CIC filter to achieve an overall reduction in processing requirement. Finally we compare two options performing a typical filtering and sample rate reduction task.
76 Tap Normalized to Unity Peak Amplitude
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Time Index 0
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70
Frequency Response: Alias Free Unit BW Pass-Band and Alias Band Masks 0
Log Mag (dB)
Abstract— The CIC filter is often used as a decimating filter to simultaneously reduce bandwidth and sample rate of the time series obtained at the output of a 1-bit Sigma-Delta converter. The conventional motivation for using the CIC is that the filtering is performed with only registers and adders, there being no multipliers in the CIC filter chain. We note that every FIR filter processing the output of a 1-bit sigma delta converter can also be implemented without multipliers. The CIC filter does not take advantage of the fact that the input samples are limited to two input levels. It is possible to design FIR filters using the two level input signal to form efficient multiply free filters that compare favorably with the CIC filter. We present here a partition of the filter and down sampling task into a cascade of a polyphase pre-filter that performs a first bandwidth and sample rate reduction without multiplies followed by a reduced sample rate CIC filter performing the second bandwidth and sample rate reduction. Operating the second filter as a CIC at a reduced output rate reduces its workload and the bit width required by its accumulators.
Folding Frequency
-20
Alias Mask
-40
Alias Mask
Alias Mask
-60 -80 -100 -120 0
5
10
15
Frequency
20
25
30
Figure 1. Impulse and Frequency Response: 5-Stage, 16-to-1 Down Sample, 120 dB Alias Free CIC Filter
We design the FIR filter using the Remez algorithm with multiple stop bands aligned with the alias mask frequencies and with multiple don’t-care bands between the design stop band
Roots, 80-Tap Polyphase Filter
0.5 5 79
0
-0.5
-1
-1 0
0.5
Log Mag (dB)
-0.1 -0.2 -1.5 0.1 0 -0.1 -0.2 -1.5
-1
-0.5
0 Frequency
5 0
FIR FILTER ARCHITECTURE
79
H1 ( z ) h(n) z n 15
4
H 2 ( z ) h(r nM) z ( r nM ) 16
4
r 0
n 0
5
5 0.5
H0 (z)
1
H1 (z)
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H15(z)
80
Frequency Response: Alias Free Unit BW Pass-Band and Alias Band Masks Log Mag (dB)
0
Y(16n)
H2 (z)
......
Amplitude
x(n)
80 Taps Normalized to Unity Peak Amplitude
0.6
(2)
r 0 n 0
Impulse Response, 80-Tap, 16-to-1 Down Sample FIR Filter 1
(1)
n 0
Figure 2. Roots of 16-to-1 Resampling 80 tap FIR and of 5-Stage CIC Filter
0.8
1.5
There are numerous architectural options that can be used to implement the 80-tap 16-to-1 down sampling FIR filter. We will discuss the two most obvious options. The first option is the conventional M-path polyphase filter formed by a mapping the prototype filter to a partial sum filter. The Z-transform of the prototype low pass filter is shown in (1) and the partial sum version is shown in (2). The inner sum of (2) performs the 5 sums per input sample that match the 5-sums performed by the 5 integrators of the 5-path CIC filter. Figs. 5 and 6 show the architecture of the polyphase partition of (2). We note that the summation shown in Fig. 5 performs the outer sums of (2) while the summations shown in Fig. 6 performs the inner sums of (2).
5 5
1
Figure 4. Pass Band Frequency Responses: 80 tap FIR and 5-Stage CIC
5
-0.5
0.5
z r h(r nM) z nM
5
-1
1
-1 -0.5 0 0.5 1 1.5 Passband Detail,16-to-1 Downsample, 5-Stage CIC Filter
75
5 -0.5
Passband Detail, 16-to-1 Downsample, 80-Tap FIR Filter
0
5
0 5
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Roots, 5-Stage 16-to-1, CIC Filter 5 5 5 1 5 5
1 0.5
Log Mag (dB)
frequencies. There are a number of useful techniques to design a good candidate FIR filter. We will present only one of these. We note that the CIC filter positions 5-repeated zeros on the unit circle centered at the images of the 15 multiples of the output sample rate, [±8, ±16, ±24,…, 64]. The number of roots sum to 75, which lead in turn, to a CIC filter impulse response with 76 coefficients. Knowing that the 5-integrators in the 5stage CIC implementation perform 5-adds per input sample we select the length of the FIR filter to be 80-taps, which in its 16to-1 down sample implementation will also require 5-adds per input sample. The resulting 80-tap FIR filter will have 79 zeros. Many of these zeros will be uniformly distributed on the unit circle in the unit-width alias free mask intervals centered on the multiples of the output sample rate while others will be reciprocally symmetric about the unit circle near the pass band frequency to affect an equal ripple, approximately flat, pass band. Fig. 2 shows the roots of the 80-tap FIR filter and of the 5-stage CIC filter. Figure 3 shows the impulse and frequency response of the 80-tap FIR filter Here we see the don’t care spectral intervals corresponding to the CIC spectral side lobes as well as the equal ripple stop band responses in the alias mask intervals due to the Remez filter design distributed zeros. It is worth comparing the time and frequency responses shown in Figs. 1 and 3. Figure 4 presents a zoom to the spectral main lobe of the FIR and CIC filters to show and compare pass band frequency responses.
Figure 5. Polyphase Partition of 80-tap, 16-to-1 Down Sample Filter
Folding Frequency
-20
Alias Mask
-40
Alias Mask
Alias Mask
x(n) r
-60
-1
z
-1
z
-1
z
-1
z
-80
Hr(0)
-100 -120 0
5
10
15
20
25
hr(1)
hr(2)
hr(3)
hr(4)
30
Frequency Figure 3. Impulse and Frequency Response: 80-Tap, 16-to-1 Down-Sample, 120 dB Alias Free FIR Filter
Figure 6. 5-Tap Delay Line Implementation of r-th Polyphase Filter Path
yr(n)
The operation of the polyphase filter shown in Figs 5 and 6 proceeds as follows. Sixteen successive binary input samples are
z-1 hr(4)
z-1
hr(3)
z-1
z-1 hr(0)
hr(1)
hr(2)
yr(n)
xr(n) Figure 7. Dual Filter Implementation of r-th Polyphase Filter Path
We note that the right most adder of Fig 7 is in fact the path accumulator of Fig. 5 performing the outer sum of (2). We also note that the outputs of the earlier accumulators in the path eventually arrive at the output accumulator where they are combined to form the final output. We can save the replicated processing elements in each path by combining their separate same position path accumulators in a single accumulator as done in the right most accumulator. This final configuration is shown in Fig.8 [3]. Here we see that all 16 paths are embedded in this single structure with the commutator, formerly delivering inputs to successive paths, now delivering the weights of those paths from local tables to the five multiply and accumulate processors. We liken the successive commutator weights being selected to interact with successive input samples to the multibarrel Gatling gun. Here the selected, and about to be active weights, rolling like the barrels of Gatling gun into position ready to service the next incoming input sample. Every 16 input samples, the table pointers reset to the bottom address and the accumulators reset after shifting their partial sums to the registers on their right. Partia l Sum Accumulators -1
-1
z
h15(3)
h r(0)
....
....
h15(4)
h r(1) h0(1) h1(1)
....
h r(3) h0(3) h1(3)
h15(2)
h15(1)
h15(0)
h r(2) h0(2) h1(2)
h0(0) h1(0)
x(n) Figure 8. M-Path Partial Sum Accumulator Polyphase Filter
CIC 1-Bit 16-to-1 s(n) 4-to-1 Main Lobe Polyphase CIC Filter ADC fS FIR Filter fS fS Com pensate fS 2 fBW 2 fBW 128 fBW 8 fBW
s(t)
Figure 9. Block Diagram of Cascade FIR and CIC Filter Chain for a 64-to-1 Bandwidth and Sample Rate Reduction of an Oversampled by 128 ADC
Figure 10 shows, for purpose of comparison, the impulse responses and the frequency responses of the 16-to-1 resampling CIC filter and FIR filter which can each perform their filtering tasks with 5-adds per input sample. We note that the FIR filter exhibits higher spectral side-lobes than does the CIC filter. At first glance this might be a matter of concern in that we may imagine that it doesn’t offer sufficient spectral suppression of the shaped out-of-band quantizing noise formed by the modulator. We will show that looks are deceiving; the side-lobes reside in the spectral don’t care regions and within reasonable limits, we really don’t care that the first side love is down 40 dB rather than 65 dB. This is because when these side lobes fold into the filter main lobe we will find then dwarfed by the main lobe response level down only 10 dB. We only have concern about the filter’s frequency response in the regions which alias into baseband, the frequency intervals highlighted by the alias masks of Fig. 10. Time Aligned Impulse Response of 16-to-1 Filters 1 0.8
80-Tap FIR Filter
0.6
76-Tap CIC Filter
0.4 0.2 0 -0.2
z-1
-1
z
....
h r(4) h0(4) h1(4)
....
z
y(16n)
We now present a simulation of the cascade FIR and CIC system proposed in this paper. A block diagram of this system is shown in Fig. 9. The system uses the multiply free FIR filter operating on the binary samples formed by the 1-bit sigma-delta converter as a pre-filter to perform an initial 16-to-1 sample rate and bandwidth reduction. The preprocessed signal is then further bandwidth and sample rate reduced 4-to-1 by a CIC filter operating at the reduced rate. In this operating mode, the CIC requires fewer stages, shorter integrator bit width, and less severe main lobe correction than would have been required had the CIC been tasked to perform the full 64-to-1 bandwidth and sample rate reduction.
Amplitude
The primary alternate realization of the filter shown in Fig. 6 is its dual filter. The dual filter is obtained by replacing each node by a summing junction, each summing junction by a node, and reversing direction of the path connections. The dual of Fig. 6 is shown in Fig. 7. In the dual filter, rather than save the data samples for later use, we form the product of each sample with each weight the sample will eventually access, and then store the products and the partial sums of those products in the registers between the adders. Of course the products are simply adds due to the binary inputs to the filter.
SIMULATION: CASCADE FIR AND CIC
Log Magnitude (dB)
delivered by the input commutator to the 16 successive paths of the filter. Each input is accepted by its 5-tap path filter which performs the 5-sums per input sample as shown in Fig. 6. The sums in Fig.6 are performed in the shared accumulator partition of Figs. 5 and 6 require an 80 tap tapped delay line to hold the 80 binary input samples. This delay line is required because each input sample contributes to 5 successive output samples and is stored so it can be accessed to contribute to the next 4 output samples.
Time Index 0
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Polyphase and CIC Filter Frequency Responses Folding Frequency Alias Mask
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CIC
CIC
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-5
0
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Frequency
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Figure 10. Compare Impulse and Frequency Responses of FIR and CIC Filters
Figure 11 presents the spectrum obtained from the 1-bit, 3-rd order modulator that has processed a comb of input sinusoids that span the normalized two sided bandwidth of 0.833 1. The top subplot shows the spectrum over a frequency span of ±16 with an overlay of the FIR filter frequency response. The This is the ratio 20/48, the high end audio ±20 kHz bandwidth sampled at the Audio Engineering Society recommended sample rate of 48 kHz. 1
next two subplots zoom in to the input signal pass band with frequency spans of ±4 and ±1 respectively. Figure 12 presents the signal spectra at the input and output of the FIR filter with the output spectrum shown at sample rate equal to the input rate, 128, and then down sampled 16-to-1 to output rate of 8. Spectrum, 3-rd Order 1-bit - Converter, fs=128 0
CONCLUSION AND CLOSING COMMENTS
Spectrum, FIR Filter
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Figure 11. Spectra of 3-rd Order, 1-Bit, Modulator Output and FIR Filter at Sample Rate 128, Displayed with Frequency Spans of ±16, ±4 and ±1
dB
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Spectrum, 3-rd Order 1-bit - Converter, fs=128 Spectrum, FIR Filter Span, 16
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Spectrum, FIR Filter Output Following 16-to-1 Down Sample fs=8 4-Stage 4-to-1 CIC Filter Span, 4
dB
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Figure 12. Spectra of FIR Filter and Input and Output of FIR Filter at Sample Rate 128, and at Down Sampled Rate 8 with Display Spans of ±16 and ±4
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Spectrum, FIR Filter Down Sampled 16-to-1, fs=8 4-stage,4-to-1 CIC
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In this paper, we commented on the wide acceptance of the CIC filter as obvious filter choice to reduce the bandwidth and sample rate of an input series because the filtering could be performed without multipliers. We readily accept the advantage of the CIC for many applications in spite of the disadvantage of the need for very wide bit-width accumulators operating at full sample rate [4] and the need to correct for the pass band spectral droop due to the main lobe frequency response [5]. This often is a trade worth making. We suggested that the trade may not be wise when we use the CIC filter to process the output of a 1bit modulator. The multiply free filter option carries little weight when the input sequence is a 1-bit data stream because any FIR filter processing this stream would also be multiply free. We presented one FIR filter design option with multiple stop band intervals interleaved with multiple don’t care bands, quite similar to the spectral response of the K-stage CIC filter and demonstrated that such a FIR filter design matched the workload as the CIC designed for the same level of spectral performance. We then examined a few FIR filter architectures with embedded down samplers that could efficiently implement the multiply free filter. We showed that the partial sum accumulator filter model, the dual of the M-path single stage, Gatling gun like interpolator proved to be a very efficient implementation of the multiply free version of the FIR filter. We demonstrated simulation results of a cascade multiply free 16-path filter and a multiply free 4-stage CIC filter. The FIR filter did not require a droop gain correction and reduced the sample rate so that the following CIC could operate at reduced speed and reduced gain, hence reduced accumulator bit width. We believe the processing advantages for filtering the output of 1-bit modulators with cascade FIR and CIC are important and deserve the attention of the DSP community.
4
Spectrum, 4-Stage CIC Output Following 4-to-1 Down Sample fs=2 Span, 1 Bandwidth
REFERENCES
-100 -1
design of the resampling FIR filter so that rather than designed pass band to be an equal-ripple approximation to unity gain, it could just as easily incorporate the sin(x)/x correction. The MATLAB version of the remez (or firpm) algorithm permits arbitrary pass band target values.
0.8
1
Figure 13. Spectra of FIR Filter at Input and Output of 4-Stage 4-to-1 Down Sample CIC Filter at Sample Rate 8 and at Down-Sampled Rate 2, with Display Spans of ±4 and ±1
Figure 13 presents the signal spectra at the input and output of the 4-stage, 4-to-1 down sample CIC filter with the output spectrum shown at sample rate equal to the input rate, 8, and then down sampled 4-to-1 to the output rate of 2. In the lower two subplots we can barely see the spectral droop over the signal frequency span due to the curvature of the four stage CIC filter. The standard sin(x)/x compensator can easily be applied to correct this distortion. Alternatively we have the option to alter the
[1] Ravi Kishore Kodali, Seeta Rami Reddy Kondapalli, and Lakshmi Boppana, “DDC and DUC Filters in SDR Platforms”, Conference on Advances in Communication and Control Systems 2013, CAC2S 2013, 6-8 April 2013, pp. 203-208. [2] Eugene Hogenauer, "An Economical Class of Digital Filters For Decimation and Interpolation," IEEE Trans. Acoust. Speech and Signal Proc., Vol. ASSP 29, April 1981, pp. 155-162. [3] fred harris, “Multirate Signal Processing for Communication Systems”, Prentice-Hall, April 2004. [4] fred harris, Elettra Venosa, Xiaofei Chen, and Markku Renfors, “Cascade Linear Phase Half-Band Filters Implement the Most Efficient Digital Down Converter”, Analog Integrated Circuits and Signal Processing, Vol. 73, No. 2, 2012, pp. 531-543. [5] Gordana Jovanovic Dolecek and fred harris, “Design of CIC Compensator Filter in a Digital Receiver”, 2008 International Symposium on Communications and Information Technologies, ISCIT 2008, 21-23 October 2008, pp.638-64
INTRODUCTION The CIC filter has gained wide acceptance as a process that efficiently performs a common multirate signal processing task; that of increasing or decreasing the sample rate of a time sequence without use of multipliers. The CIC is the core building block, for instance, in the down-sampling or up-sampling process in digital down converters (DDC) and digital up-converters (DUC) respectively [1]. The attraction of the CIC is twofold: first the resampling operation is embedded in the filter between the multiple integrator stages and the multiple derivative filter stages. The second is that the filtering is performed with only registers and adders; there being no multipliers in the CIC filter chain. These same attributes have motivated us to similarly apply the CIC filter to the task of bandwidth and sample rate reduction of the time series formed at the output of a 1-bit sigma-delta analog-to-digital converter. We can easily recognize that the CIC is not the only filter structure that can perform the filtering task on the output of a 1-bit sigma delta converter. In fact every FIR filter processing a 1-bit data sequence can be implemented
DESIGN OF FILTER FREQUENCY RESPONSE We now examine a FIR filter implementation of a CIC like impulse response and then embed an M-to-1 resampler in the FIR filter as is done in the CIC conversion to the Hogenauer filter implementation [2]. As a specific example we consider a 5stage CIC filter supporting 16-to-1 down sampling with an output sample rate 8-times the desired alias free bandwidth with 120 dB dynamic range. Figure shows the amplitude normalized impulse and frequency responses of this CIC filter. Impulse Response, 5-Stage 16-to-1 Down Sample, CIC Filter 1
Amplitude
Keywords—CIC Filter, Coupled Polyphase & CIC Filters
without multipliers. This is because the data samples being limited to plus one or minus one, can at most; change the sign of the coefficients, but not their size, as they are added to the filter’s accumulator. The CIC filter does not take advantage of the fact that the input samples are limited to plus or minus one. We now examine a number of FIR filter architectures that use the unique pair of bipolar input values to implement multiply free filters. We also present design considerations that assure these FIR filters have comparable performance and computational workload as the CIC filter. We show how we can couple the two filters, the multiply free binary input FIR filter with the multiply free CIC filter to achieve an overall reduction in processing requirement. Finally we compare two options performing a typical filtering and sample rate reduction task.
76 Tap Normalized to Unity Peak Amplitude
0.8 0.6 0.4 0.2 0 -0.2
Time Index 0
10
20
30
40
50
60
70
Frequency Response: Alias Free Unit BW Pass-Band and Alias Band Masks 0
Log Mag (dB)
Abstract— The CIC filter is often used as a decimating filter to simultaneously reduce bandwidth and sample rate of the time series obtained at the output of a 1-bit Sigma-Delta converter. The conventional motivation for using the CIC is that the filtering is performed with only registers and adders, there being no multipliers in the CIC filter chain. We note that every FIR filter processing the output of a 1-bit sigma delta converter can also be implemented without multipliers. The CIC filter does not take advantage of the fact that the input samples are limited to two input levels. It is possible to design FIR filters using the two level input signal to form efficient multiply free filters that compare favorably with the CIC filter. We present here a partition of the filter and down sampling task into a cascade of a polyphase pre-filter that performs a first bandwidth and sample rate reduction without multiplies followed by a reduced sample rate CIC filter performing the second bandwidth and sample rate reduction. Operating the second filter as a CIC at a reduced output rate reduces its workload and the bit width required by its accumulators.
Folding Frequency
-20
Alias Mask
-40
Alias Mask
Alias Mask
-60 -80 -100 -120 0
5
10
15
Frequency
20
25
30
Figure 1. Impulse and Frequency Response: 5-Stage, 16-to-1 Down Sample, 120 dB Alias Free CIC Filter
We design the FIR filter using the Remez algorithm with multiple stop bands aligned with the alias mask frequencies and with multiple don’t-care bands between the design stop band
Roots, 80-Tap Polyphase Filter
0.5 5 79
0
-0.5
-1
-1 0
0.5
Log Mag (dB)
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-1
-0.5
0 Frequency
5 0
FIR FILTER ARCHITECTURE
79
H1 ( z ) h(n) z n 15
4
H 2 ( z ) h(r nM) z ( r nM ) 16
4
r 0
n 0
5
5 0.5
H0 (z)
1
H1 (z)
0.4 0.2 0 -0.2
Time Index 0
10
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30
40
50
60
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H15(z)
80
Frequency Response: Alias Free Unit BW Pass-Band and Alias Band Masks Log Mag (dB)
0
Y(16n)
H2 (z)
......
Amplitude
x(n)
80 Taps Normalized to Unity Peak Amplitude
0.6
(2)
r 0 n 0
Impulse Response, 80-Tap, 16-to-1 Down Sample FIR Filter 1
(1)
n 0
Figure 2. Roots of 16-to-1 Resampling 80 tap FIR and of 5-Stage CIC Filter
0.8
1.5
There are numerous architectural options that can be used to implement the 80-tap 16-to-1 down sampling FIR filter. We will discuss the two most obvious options. The first option is the conventional M-path polyphase filter formed by a mapping the prototype filter to a partial sum filter. The Z-transform of the prototype low pass filter is shown in (1) and the partial sum version is shown in (2). The inner sum of (2) performs the 5 sums per input sample that match the 5-sums performed by the 5 integrators of the 5-path CIC filter. Figs. 5 and 6 show the architecture of the polyphase partition of (2). We note that the summation shown in Fig. 5 performs the outer sums of (2) while the summations shown in Fig. 6 performs the inner sums of (2).
5 5
1
Figure 4. Pass Band Frequency Responses: 80 tap FIR and 5-Stage CIC
5
-0.5
0.5
z r h(r nM) z nM
5
-1
1
-1 -0.5 0 0.5 1 1.5 Passband Detail,16-to-1 Downsample, 5-Stage CIC Filter
75
5 -0.5
Passband Detail, 16-to-1 Downsample, 80-Tap FIR Filter
0
5
0 5
-0.5
-1
0.1
Roots, 5-Stage 16-to-1, CIC Filter 5 5 5 1 5 5
1 0.5
Log Mag (dB)
frequencies. There are a number of useful techniques to design a good candidate FIR filter. We will present only one of these. We note that the CIC filter positions 5-repeated zeros on the unit circle centered at the images of the 15 multiples of the output sample rate, [±8, ±16, ±24,…, 64]. The number of roots sum to 75, which lead in turn, to a CIC filter impulse response with 76 coefficients. Knowing that the 5-integrators in the 5stage CIC implementation perform 5-adds per input sample we select the length of the FIR filter to be 80-taps, which in its 16to-1 down sample implementation will also require 5-adds per input sample. The resulting 80-tap FIR filter will have 79 zeros. Many of these zeros will be uniformly distributed on the unit circle in the unit-width alias free mask intervals centered on the multiples of the output sample rate while others will be reciprocally symmetric about the unit circle near the pass band frequency to affect an equal ripple, approximately flat, pass band. Fig. 2 shows the roots of the 80-tap FIR filter and of the 5-stage CIC filter. Figure 3 shows the impulse and frequency response of the 80-tap FIR filter Here we see the don’t care spectral intervals corresponding to the CIC spectral side lobes as well as the equal ripple stop band responses in the alias mask intervals due to the Remez filter design distributed zeros. It is worth comparing the time and frequency responses shown in Figs. 1 and 3. Figure 4 presents a zoom to the spectral main lobe of the FIR and CIC filters to show and compare pass band frequency responses.
Figure 5. Polyphase Partition of 80-tap, 16-to-1 Down Sample Filter
Folding Frequency
-20
Alias Mask
-40
Alias Mask
Alias Mask
x(n) r
-60
-1
z
-1
z
-1
z
-1
z
-80
Hr(0)
-100 -120 0
5
10
15
20
25
hr(1)
hr(2)
hr(3)
hr(4)
30
Frequency Figure 3. Impulse and Frequency Response: 80-Tap, 16-to-1 Down-Sample, 120 dB Alias Free FIR Filter
Figure 6. 5-Tap Delay Line Implementation of r-th Polyphase Filter Path
yr(n)
The operation of the polyphase filter shown in Figs 5 and 6 proceeds as follows. Sixteen successive binary input samples are
z-1 hr(4)
z-1
hr(3)
z-1
z-1 hr(0)
hr(1)
hr(2)
yr(n)
xr(n) Figure 7. Dual Filter Implementation of r-th Polyphase Filter Path
We note that the right most adder of Fig 7 is in fact the path accumulator of Fig. 5 performing the outer sum of (2). We also note that the outputs of the earlier accumulators in the path eventually arrive at the output accumulator where they are combined to form the final output. We can save the replicated processing elements in each path by combining their separate same position path accumulators in a single accumulator as done in the right most accumulator. This final configuration is shown in Fig.8 [3]. Here we see that all 16 paths are embedded in this single structure with the commutator, formerly delivering inputs to successive paths, now delivering the weights of those paths from local tables to the five multiply and accumulate processors. We liken the successive commutator weights being selected to interact with successive input samples to the multibarrel Gatling gun. Here the selected, and about to be active weights, rolling like the barrels of Gatling gun into position ready to service the next incoming input sample. Every 16 input samples, the table pointers reset to the bottom address and the accumulators reset after shifting their partial sums to the registers on their right. Partia l Sum Accumulators -1
-1
z
h15(3)
h r(0)
....
....
h15(4)
h r(1) h0(1) h1(1)
....
h r(3) h0(3) h1(3)
h15(2)
h15(1)
h15(0)
h r(2) h0(2) h1(2)
h0(0) h1(0)
x(n) Figure 8. M-Path Partial Sum Accumulator Polyphase Filter
CIC 1-Bit 16-to-1 s(n) 4-to-1 Main Lobe Polyphase CIC Filter ADC fS FIR Filter fS fS Com pensate fS 2 fBW 2 fBW 128 fBW 8 fBW
s(t)
Figure 9. Block Diagram of Cascade FIR and CIC Filter Chain for a 64-to-1 Bandwidth and Sample Rate Reduction of an Oversampled by 128 ADC
Figure 10 shows, for purpose of comparison, the impulse responses and the frequency responses of the 16-to-1 resampling CIC filter and FIR filter which can each perform their filtering tasks with 5-adds per input sample. We note that the FIR filter exhibits higher spectral side-lobes than does the CIC filter. At first glance this might be a matter of concern in that we may imagine that it doesn’t offer sufficient spectral suppression of the shaped out-of-band quantizing noise formed by the modulator. We will show that looks are deceiving; the side-lobes reside in the spectral don’t care regions and within reasonable limits, we really don’t care that the first side love is down 40 dB rather than 65 dB. This is because when these side lobes fold into the filter main lobe we will find then dwarfed by the main lobe response level down only 10 dB. We only have concern about the filter’s frequency response in the regions which alias into baseband, the frequency intervals highlighted by the alias masks of Fig. 10. Time Aligned Impulse Response of 16-to-1 Filters 1 0.8
80-Tap FIR Filter
0.6
76-Tap CIC Filter
0.4 0.2 0 -0.2
z-1
-1
z
....
h r(4) h0(4) h1(4)
....
z
y(16n)
We now present a simulation of the cascade FIR and CIC system proposed in this paper. A block diagram of this system is shown in Fig. 9. The system uses the multiply free FIR filter operating on the binary samples formed by the 1-bit sigma-delta converter as a pre-filter to perform an initial 16-to-1 sample rate and bandwidth reduction. The preprocessed signal is then further bandwidth and sample rate reduced 4-to-1 by a CIC filter operating at the reduced rate. In this operating mode, the CIC requires fewer stages, shorter integrator bit width, and less severe main lobe correction than would have been required had the CIC been tasked to perform the full 64-to-1 bandwidth and sample rate reduction.
Amplitude
The primary alternate realization of the filter shown in Fig. 6 is its dual filter. The dual filter is obtained by replacing each node by a summing junction, each summing junction by a node, and reversing direction of the path connections. The dual of Fig. 6 is shown in Fig. 7. In the dual filter, rather than save the data samples for later use, we form the product of each sample with each weight the sample will eventually access, and then store the products and the partial sums of those products in the registers between the adders. Of course the products are simply adds due to the binary inputs to the filter.
SIMULATION: CASCADE FIR AND CIC
Log Magnitude (dB)
delivered by the input commutator to the 16 successive paths of the filter. Each input is accepted by its 5-tap path filter which performs the 5-sums per input sample as shown in Fig. 6. The sums in Fig.6 are performed in the shared accumulator partition of Figs. 5 and 6 require an 80 tap tapped delay line to hold the 80 binary input samples. This delay line is required because each input sample contributes to 5 successive output samples and is stored so it can be accessed to contribute to the next 4 output samples.
Time Index 0
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Polyphase and CIC Filter Frequency Responses Folding Frequency Alias Mask
0 -20 -40
FIR
-60 -80 -100
FIR
CIC
CIC
-120 -140
-5
0
5
10
15
Frequency
20
25
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35
40
Figure 10. Compare Impulse and Frequency Responses of FIR and CIC Filters
Figure 11 presents the spectrum obtained from the 1-bit, 3-rd order modulator that has processed a comb of input sinusoids that span the normalized two sided bandwidth of 0.833 1. The top subplot shows the spectrum over a frequency span of ±16 with an overlay of the FIR filter frequency response. The This is the ratio 20/48, the high end audio ±20 kHz bandwidth sampled at the Audio Engineering Society recommended sample rate of 48 kHz. 1
next two subplots zoom in to the input signal pass band with frequency spans of ±4 and ±1 respectively. Figure 12 presents the signal spectra at the input and output of the FIR filter with the output spectrum shown at sample rate equal to the input rate, 128, and then down sampled 16-to-1 to output rate of 8. Spectrum, 3-rd Order 1-bit - Converter, fs=128 0
CONCLUSION AND CLOSING COMMENTS
Spectrum, FIR Filter
dB
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BW=0.833
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0
Frequency
0.2
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1
Figure 11. Spectra of 3-rd Order, 1-Bit, Modulator Output and FIR Filter at Sample Rate 128, Displayed with Frequency Spans of ±16, ±4 and ±1
dB
0
Spectrum, 3-rd Order 1-bit - Converter, fs=128 Spectrum, FIR Filter Span, 16
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Spectrum, FIR Filter Output Prior to 16-to-1 Down Sample fs=128 Span, 16
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Spectrum, FIR Filter Output Following 16-to-1 Down Sample fs=8 4-Stage 4-to-1 CIC Filter Span, 4
dB
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-100 -4
-3
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-1
0
1
Frequency
2
3
4
Figure 12. Spectra of FIR Filter and Input and Output of FIR Filter at Sample Rate 128, and at Down Sampled Rate 8 with Display Spans of ±16 and ±4
dB
0
Spectrum, FIR Filter Down Sampled 16-to-1, fs=8 4-stage,4-to-1 CIC
Span, 4
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-100 -4
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Spectrum, 4-Stage CIC Prior to 4-to-1 Down Sample fs=8 0
Alias Mask
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Alias Mask
Span, 4
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In this paper, we commented on the wide acceptance of the CIC filter as obvious filter choice to reduce the bandwidth and sample rate of an input series because the filtering could be performed without multipliers. We readily accept the advantage of the CIC for many applications in spite of the disadvantage of the need for very wide bit-width accumulators operating at full sample rate [4] and the need to correct for the pass band spectral droop due to the main lobe frequency response [5]. This often is a trade worth making. We suggested that the trade may not be wise when we use the CIC filter to process the output of a 1bit modulator. The multiply free filter option carries little weight when the input sequence is a 1-bit data stream because any FIR filter processing this stream would also be multiply free. We presented one FIR filter design option with multiple stop band intervals interleaved with multiple don’t care bands, quite similar to the spectral response of the K-stage CIC filter and demonstrated that such a FIR filter design matched the workload as the CIC designed for the same level of spectral performance. We then examined a few FIR filter architectures with embedded down samplers that could efficiently implement the multiply free filter. We showed that the partial sum accumulator filter model, the dual of the M-path single stage, Gatling gun like interpolator proved to be a very efficient implementation of the multiply free version of the FIR filter. We demonstrated simulation results of a cascade multiply free 16-path filter and a multiply free 4-stage CIC filter. The FIR filter did not require a droop gain correction and reduced the sample rate so that the following CIC could operate at reduced speed and reduced gain, hence reduced accumulator bit width. We believe the processing advantages for filtering the output of 1-bit modulators with cascade FIR and CIC are important and deserve the attention of the DSP community.
4
Spectrum, 4-Stage CIC Output Following 4-to-1 Down Sample fs=2 Span, 1 Bandwidth
REFERENCES
-100 -1
design of the resampling FIR filter so that rather than designed pass band to be an equal-ripple approximation to unity gain, it could just as easily incorporate the sin(x)/x correction. The MATLAB version of the remez (or firpm) algorithm permits arbitrary pass band target values.
0.8
1
Figure 13. Spectra of FIR Filter at Input and Output of 4-Stage 4-to-1 Down Sample CIC Filter at Sample Rate 8 and at Down-Sampled Rate 2, with Display Spans of ±4 and ±1
Figure 13 presents the signal spectra at the input and output of the 4-stage, 4-to-1 down sample CIC filter with the output spectrum shown at sample rate equal to the input rate, 8, and then down sampled 4-to-1 to the output rate of 2. In the lower two subplots we can barely see the spectral droop over the signal frequency span due to the curvature of the four stage CIC filter. The standard sin(x)/x compensator can easily be applied to correct this distortion. Alternatively we have the option to alter the
[1] Ravi Kishore Kodali, Seeta Rami Reddy Kondapalli, and Lakshmi Boppana, “DDC and DUC Filters in SDR Platforms”, Conference on Advances in Communication and Control Systems 2013, CAC2S 2013, 6-8 April 2013, pp. 203-208. [2] Eugene Hogenauer, "An Economical Class of Digital Filters For Decimation and Interpolation," IEEE Trans. Acoust. Speech and Signal Proc., Vol. ASSP 29, April 1981, pp. 155-162. [3] fred harris, “Multirate Signal Processing for Communication Systems”, Prentice-Hall, April 2004. [4] fred harris, Elettra Venosa, Xiaofei Chen, and Markku Renfors, “Cascade Linear Phase Half-Band Filters Implement the Most Efficient Digital Down Converter”, Analog Integrated Circuits and Signal Processing, Vol. 73, No. 2, 2012, pp. 531-543. [5] Gordana Jovanovic Dolecek and fred harris, “Design of CIC Compensator Filter in a Digital Receiver”, 2008 International Symposium on Communications and Information Technologies, ISCIT 2008, 21-23 October 2008, pp.638-64
