Robust Decentralized Voltage Control of DC-DC Converters with ...
Robust Decentralized Voltage Control of DC-DC Converters with Applications to Power Sharing and Ripple Sharing
arXiv:1604.03573v1 [math.OC] 12 Apr 2016
Mayank Baranwal1,a , Srinivasa M. Salapaka1,b and Murti V. Salapaka2,c Abstract— This paper addresses the problem of output voltage regulation for multiple DC-DC converters connected to a grid, and prescribes a robust scheme for sharing power among different sources. Also it develops a method for sharing 120 Hz ripple among DC power sources in a prescribed proportion, which accommodates the different capabilities of DC power sources to sustain the ripple. We present a decentralized control architecture, where a nested (inner-outer) control design is used at every converter. An interesting aspect of the proposed design is that the analysis and design of the entire multi-converter system can be done using an equivalent single converter system, where the multi-converter system inherits the performance and robustness achieved by a design for the single-converter system. Another key aspect of this work is that the voltage regulation problem is addressed as a disturbance-rejection problem, where unknown load current is viewed as an external signal, and thus, no prior information is required on the nominal loading conditions. The control design is obtained using robust optimalcontrol framework. Case studies presented show the enhanced performance of prescribed optimal controllers.
I. INTRODUCTION In power network topologies, especially in microgrids [1], multiple DC power sources connected in parallel (see Figure 1), each interfaced with DC-DC converter, provide power at their common output, the DC-link, at a regulated voltage; this power can directly feed DC loads or be used by an inverter to interface with AC loads . Voltage controllers form an integral component of DC-DC converters in such systems. A paralleled architecture for multiple power sources is preferred since it enables higher output power, higher reliability and ease of use [2]. Here two main control architectures are adopted - (1) master-slave control, where the voltage regulation error from the master converter is utilized to provide an error signal to all the parallel connected converters [2], [3], (2) decentralized control, where each converter utilizes an independent and variable voltage reference depending on the output of each unit [4], [5]. Irrespective of the control framework, controllers at each converter are to be designed such that the voltage at the DClink is regulated at a prescribed setpoint. Another important control objective is to ensure that the DC sources provide power in a prescribed proportion, which may be dictated by their power ratings or external economic criteria. The main challenges arise from the uncertainties in the size and the schedules of loads, the complexity of a coupled multiconverter network, the uncertainties in the model parameters 1 Department of Mechanical Science and Engineering, University of Illinois at Urbana-Champaign, IL 61801, USA 2 Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA a [email protected], b [email protected] c [email protected]
Fig. 1: A schematic of a microgrid. An array of DC sources provide power for AC loads. Power sources provide power at DC-link, their common output bus, at a voltage that is regulated to a setpoint. The control system at the respective DC-DC converter that interfaces with a source is responsible for regulating the voltage at he DC-link. An inverter that connects to the DC-link converts the total current from the sources at the regulated voltage to alternating current (AC) at its output to satisfy the power demands of the AC loads. This paper describes an approach for control design of the multiple converters systems associated with power transfer from sources to the DC-link (shown by the dotted line).
at each converter, and the adverse effects of interfacing DC power sources with AC loads, such as the 120 Hz ripple that has to be provided by the DC sources. Problems related to robust and optimal design of converter controllers have received recent attention. In [6], a linearmatrix-inequality (LMI) based robust control design for boost converters has resulted in significant improvements over conventional PID-based controllers. Use of H∞ framework in context of inverter systems has also been studied in [7]–[9]. While the issue of current sharing is extensively studied [4], [10]–[12], most methods assume a single power source. A systematic control design that addresses all the challenges and objectives for the multi-converter control is still lacking. In this paper, we develop a control architecture that addresses the following primary objectives for multi-converter control - (1) voltage regulation at the DC-link while guaranteeing robustness of the closed-loop system performance to load and parametric uncertainties, (2) prescribed power sharing among a number of parallel converters, (3) controlling the tradeoff between 120 Hz ripple on the total current provided by the power sources and the ripple on the DC-link voltage, and (4) 120 Hz DC output ripple sharing among converters. The tradeoffs with 120 Hz ripple in objectives
(3) and (4) result from a direct consequence of interfacing DC-power sources with AC loads (see Figure 1). If we assume negligible power losses at the inverter and the load bus, the power provided by power sources at the DC-link should equal to the power consumed by the AC loads, that is, V¯ I¯ V i = (V¯ sin ω ¯ t)(I¯ sin(¯ ω t + φ)) = (cos φ + cos(2¯ ω t + φ). 2 Since the instantaneous power has a 2¯ ω = 120 Hz ripple, the P current i = ik at the DC-link has to provide for this 120 Hz component. The total ripple demand posed by the ACgrid side is met partly by the ripple current sourced by a capacitor iC which reduces the magnitude of the ripple current to be provided by the DC source via the converters. However, greater the ripple magnitude in the capacitor current greater will be the ripple in the capacitor voltage, thus adversely affecting voltage regulation. Therefore a compromise has to be reached in the allowable ripple in the capacitor current and the ripple provided by the DC sources. The control scheme presented in the article provides a “knob” to adjust the relative ratio of how the 120 Hz ripple is shared between the two quantities - the sourced current i and the output voltage V . Moreover in a scenario where multiple and different types of DC sources are employed, it is often the case that the tolerance to ripple varies. Here it becomes important to allocate greater percentage of ripple load to tolerant DC sources while reducing the ripple load on vulnerable DC sources. The article presents a controller synthesis procedure where the 120 Hz ripple on the current i can be shared among the paralleled DC sources (ik ) in a pre-specified proportion. An important aspect of the proposed control architecture is that it is decentralized and addresses all the objectives simultaneously. Moreover we show that for the control approach described in the paper, the control design and the closed-loop analysis of the multi-converter system can be completely characterized in terms of an appropriate single-converter system; thereby significantly reducing the complexity in addressing multi-converter systems. This architecture exploits structural features of the paralleled multi-converter system, which results in a modular and yet coordinated control design. For instance, it exploits that the voltage regulation objective is common to all the converters, and that the differences in demands on different converters are mainly in terms of their output currents; accordingly at each converter, it employs a nested (outer-voltage inner-current) control structure [13], where the outer loop is responsible for robust voltage regulation and the inner loop for shaping the currents. The structure of control for each inner-loop is so chosen that the entire closed-loop multi converter system can be reduced to an equivalent single-converter system in terms of the transfer function from the desired regulation setpoint Vdes to the voltage V . Furthermore, for the outer-control design, the load current is treated as an external disturbance and the voltage regulation problem is cast as a disturbance rejection problem in an optimal control setting. This design, besides achieving the voltage-regulation objective, provides robustness to deviations from the structural assumptions in the control design. Note that this viewpoint is in contrast to typical methods in existing literature, where voltage regulation in presence of unknown loads is addressed either using
adaptive control [14], or by letting the voltage droop in a controlled manner. II. M ODELING OF CONVERTERS In this section, we provide dynamic models for DC-DC converters, which convert a source of direct current (DC) from one voltage level to another. The models presented below depict dynamics for signals that are averaged over a switch cycle. A schematic of the Boost converter is shown in Fig. 2(a). A dynamic model (averaged over switching cycles) is given by, C V˙ (t) = (1−d(t))iL (t)−iload ,
Li˙L (t) = −(1−d(t))V (t)+Vg ,
where d(t) represents the duty-cycle (or the proportion of ON duration) at time t, which by defining d0 (t) = 1 − d(t) Vg and D0 = Vdes can be rewritten as Li˙L (t) = −d0 (t)V (t) + Vg , | {z } u ˜ (t):=Vg −u(t)
C V˙ (t) = (D0 + dˆ0 )iL (t) − iload . | {z } ≈D 0
Here Vdes represents the desired output voltage and dˆ = d0 (t) − D0 is typically very small, which allows for a linear approximation around the nominal duty-cycle, D = 1 − D0 given by, L
diL (t) =u ˜(t), dt
C
dV (t) ≈ D0 iL (t) − iload . dt
Fig. 2(b) depicts the circuit schematic of a buck converter with an ideal switch. The averaged model of a buck converter is given by, L
diL (t) = −V (t) + d(t)Vg , dt | {z }
C
dV (t) = iL (t) − iload . dt
u ˜ (t):=−V (t)+u(t)
The electronic circuit of a buck-boost converter is shown in Fig. 2(c). As in case of a boost converter, we define des nominal duty-cycle, D = VdesV−V = 1 − D0 . A linear g approximation of the above dynamical equations yields, Li˙L (t) = V (t) + d(t)(Vg − V (t)), | {z }
C V˙ (t) ≈ −D0 iL (t) − iload
u ˜ (t):=V (t)+u(t)
III. C ONTROL FRAMEWORK FOR A SINGLE - CONVERTER In this section, we describe the inner-current outer-voltage control architecture for a single DC-DC converter. The key objectives of the control design are - (1) voltage regulation in presence of uncertain loads, and (2) 120 Hz ripple sharing control between iL and iC . We first consider the case of a boost converter control design, the dynamics of which is given by iL (s) =
1 (Vg (s) − u(s)), sL
V (s) =
1 (D0 iL (s) − iload (s)), sC (1)
and the corresponding block-diagram representation of above set of equations is shown in Fig. 3, the control objectives are to design u (equivalently u ˜) such that voltage regulation error Vdes − V is made small irrespective of load disturbances iload and variations in parameters L and C, and achieve a prescribed tradeoff between |iL (j2π120)| and |iC (j2π120)|. These two objectives are achieved using a nested innercurrent outer-voltage control architecture, shown in Fig. 4
(a) (b) (c) Fig. 2: Circuit representing (a) Boost converter, (b)Buck converter, and (c) Buck-Boost converter. Note that iload includes both the nominal load current, as well as ripple current. The converters are assumed to operate in continuous-conduction-mode (CCM). Boost converters step up the voltage at the output, while buck converters step down the voltage. A buck-boost converter can achieve both the objectives.
Fig. 3: Block diagram representation of a boost-type converter. The control signal u ˜ is converted to an equivalent PWM signal to command the gate of the transistor acting as a switch. 1 1 (here Gc = sL and Gv = sC ). The voltage controller Kv generates a current reference for the current controller Kc . The current controller Kc is designed to achieve a high closed inner-loop bandwidth with ripple control as an objective, whereas the voltage controller Kv is designed to achieve a relatively lower closed outer-loop bandwidth with DC (zero frequency) voltage regulation as its primary objective. We assume that the quantities - output voltage V and inductor current iL are available for measurement. Design of the outer-loop controller: For a given controller Kc for the inner-loop, the closed outer-loop signals of interest are given by (see Figure 4)
Vdes − V
=
iL
=
iref
=
SVdes + Gv Sd + T n ˜ c Kv SVdes + 1 T d − Kv G ˜ c Sn G D0 Kv (SVdes + Gv Sd) − Kv Sn,
(2) (3) (4)
where d denotes the load current iload (shown as disturbance ˜c to the plant), n denotes the voltage measurement noise, G represents the closed inner-loop transfer function from iref to iL , and T (s) and S(s) are closed-loop complementary sensitivity and sensitivity transfer functions respectively, described by, T (s)
=
S(s)
=
˜ c Kv )−1 (Gv D0 G ˜ c Kv ), (I + Gv D0 G 0 ˜ −1 (I + Gv D Gc Kv ) .
(5)
The voltage-regulation objective, as evident from Eq. 2,
frequencies where disturbance d is prominent. However this implies that the effect of d on the inductor current iL (see Eq. 3) is larger since |T (jω)| is larger in those frequencies (from Eq. 5). Therefore there is a fundamental trade-off between voltage regulation and minimizing effects of disturbances (or load current iload ) in iL . Also to diminish the effect of noise on voltage regulation, the control design should be such that the closed-loop map T rolls of at frequencies beyond the disturbance bandwidth. Furthermore low iref is ensured if Kv S can be made small. The controller Kv is obtained by casting these multiple objectives in the following optimal control problem [15],
Ws S
min Wu Kv S Kv ∈K Wt T
design. Exogenous signals Vdes and iload represent the desired output voltage and disturbance, respectively. The quantities V and iL represent the available measurements.
requires designing Kv such that |S(jω)| is small at the
,
(6)
∞
where the weights Ws , Wt and Wu are chosen to reflect the design specifications of robustness to disturbances and parametric uncertainties, tracking bandwidth, and saturation limits on the control signal. For example, the weight function Ws (jω) is chosen to be large in frequency range [0, ωBW ] to ensure a small tracking error e = Vdes − V in this frequency range. The weight function Wt (jω) is designed as a high-pass filter to ensure that T (jω) is small at high frequencies to provide mitigation to measurement noise. The design of constant Wu entails ensuring that the control effort lies within saturation limits. The resulting controller is robust to disturbances up to ωBW , which accounts for variations in load disturbances as well as parametric uncertainties. Design of the inner-loop controller: The outer-loop con˜ c . Here we trol design assumed the inner closed-loop G propose an inner-loop control design that results in a second˜ c , thereby ensuring a relatively loworder transfer function G order optimal controller Kv . The main objective for designing the inner-loop controller Kc is to decide the trade-off between the 120 Hz ripple on the voltage V (equivalently on the capacitor current ic ) and the output current i (equivalently iL ) of the converter. Accordingly, we design Kc such that ˜ c (s) = G
Fig. 4: Block diagram representation of the inner-outer control
ω ˜ s+ω ˜
s2 + 2ζ1 ω0 s + ω02 s2 + 2ζ2 ω0 s + ω02
,
(7)
where ω0 = 2π120 rad/s. ω ˜ , ζ1 , ζ2 are design parameters. Here the parameter ω ˜ > ω0 is simply chosen to implement a low-pass filter that attenuates undesirable frequency content ˜ c , there is a in iL beyond ω ˜ . Note that in this design of G notch at ω0 = 120 Hz, the size of this notch is determined by the ratio ζζ21 (see Figure 5). Lower values of this ratio correspond to larger notches, which in turn imply smaller 120 ˜ c represents the inner closedHz component in iL , since G loop transfer function from iref to iL . Furthermore since iC = iload − iL , this in turn implies higher ripples in iC . Thus the ratio ζζ21 can be appropriately designed to achieve a specified
tradeoff between 120 Hz ripple on iC and iL . The stabilizing
˜ c for Fig. 5: Bode magnitude plots of the closed-loop plant G
Fig. 6: Control framework for a many-converters system. Note that
various ζ1 values. ω ˜ is chosen to be 600π rad/s. Note that a relatively larger value of ω ˜ is in accordance with choosing a fast inner-current controller.
in the proposed implementation, we adopt the same outer controller for different converters, i.e., Kv1 = Kv2 = .... = Kvm = Kv .
second-order controller Kc that yields the above closed-loop ˜ c is explicitly given by, plant G
duty-cycle Dn = 1 − Dn0 . Then by appropriately designing individual inner-loop parameters, we can design the nominal closed inner-loop plant to be given by
Kc = L˜ ω
s2 + 2ζ1 ω0 s + ω02 , (s2 + 2ζ2 ω0 s + 2(ζ2 − ζ1 )ω0 ω ˜ + ω02 )
(8)
˜ c,n (s) = G
ω ˜ s+ω ˜
s2 + 2ζ1,n ω0 s + ω02 s2 + 2ζ2,n ω0 s + ω02
,
(9)
which is again a low-order (second-order) controller design. Extension to buck and buck-boost converters: The extension of the proposed control design to Buck and BuckBoost DC-DC converters is easily explained after noting that their averaged models are structurally identical to Boost converters, except that the dependence of duty cycles on the control signal u or constant parameter D0 are different. The differences in how duty cycles depend on u(t) do not matter from the control design viewpoint since duty cycles for pulse-width modulation are obtained only after obtaining the control designs (that use the averaged models).
ζ1,n determines the tradeoff of 120 Hz ζP 2,n ripple between i = k ik and the capacitor current iC . Note that for the cumulative closed inner-loop plant in Figure 7 ˜ c,n (s), we require closed to behave as the nominal plant G inner-loop maps toP sum up to the nominal closed inner0 ˜ 0 ˜ loop plant, that is k γk Dk Gck = Dn Gc,n . Accordingly we design Kck in each inner loop such that
IV. E XTENSION TO A SYSTEM OF PARALLEL
where ζ1 are appropriately chosen to reflect the relative tradeoff of 120 Hz ripple among converter current outputs ik . Explicit design of such Kck exists and is analogous to the design in (8), which was obtained for the same structure of the inner-closed loop in the single-converter case. The parameters γk are designed to apportion power among the power sources, since DC gains of individual closed inner˜ ck D0 are equal to γk D0 since G ˜ c (j0) = 1 loop plants γk G k k k by design for all k. We make these design specifications more precise and bring out the equivalence of the control design for the single and multiple converter systems in the following theorem.
CONVERTERS
In this section we develop a decentralized control framework that achieves voltage regulation, power-sharing, and ripple-sharing among a system of parallel boost converters sharing a common load. A. Control framework for a system of parallel boost converters Fig. 6 represents a decentralized inner-outer control framework for a system of m parallel connected converters. Here we have incorporated a constant gain parameter γk at the inner-loop of kth converter, the choice of which dictates power sharing as will be shown below. After noting that the voltage-regulation objective is common to all outer controllers, in our architecture, we impose the same outercontroller for all the converters, i.e., Kv1 = Kv2 = .... = Kvm = Kv . This enables a significant reduction in complexity of the control design for the multi-converter system as will be shown below. First, with this assumption of Kvk = Kv , the general decentralized architecture in Figure 6 can be simplified as in Figure 7. This implies that Kv can be computed by solving H∞ -optimization problem (as discussed in the previous section) similar to the single converter case by assuming an available design for the summed closed inner-loop map ˜ c,n (the nominal closed inner-loop plant) and a nominal G
where the ratio
˜ c (s) = G k
ω ˜ s+ω ˜
(k)
s2 + 2ζ1 ω0 s + ω02 s2 + 2ζ2,n ω0 s + ω02
! ,
(10)
(k)
Fig. 7: A multiple-converters system with shaped inner plants. Note ˜ c share the same denominator as G ˜ c,n . that the shaped plants G k
Theorem 1: Consider the single-converter system in Fig˜ c,n (s) ure 4 with inductance L, D0 = Dn0 and G˜c = G as given in (9); and the multi-converter system described ˜ c (s) are given by (10), in 6 and 7 where G k P Figures P 0 ˜ 0 ˜ k γk Dk Gck = Dn Gc,n , and k γk = 1, γk > 0 for 1 ≤ k ≤ m. 1. [Performance Equivalence]: Any outer-loop controller Kv that stabilizes the single-converter system yields identical performance when applied to the multi-converter system; more precisely, for the same exogenous inputs - theP reference Vdes , the load disturbance iload , and noise n = k γk nk , Dn0 the steady-state regulated signals (Vdes − V, u ˜, V ) for the L single-converter system are the same as the regulated signals P D0 (Vdes − V, k k u ˜k , V ) for the multi-converter system. Lk (k) 2. [Power Sharing]: If the parameters γk , and ζ1 , 1 ≤ k ≤ m 0 P (k) αk Dn m are chosen such that γk = D and αk ζ1 = ζ1,n , 0 k
and ω ˜ = 2π300rad/s. The outer-controller Kv is obtained by solving the stacked H∞ optimization problem (see Eq. 6) [15] with the weighting functions: Ws = 0.5s+2π50 s+0.06π50 , s+2π40 Wu = 0.9, and Wt = 0.05s+2π80 . The resulting reduced fifth-order controller Kv is given by: Kv =
0.256(s + 113.9)(s + 0.001)2 (s2 + 4.05e4s + 5.65e8) (s + 9.56)(s2 + 0.002s + 4.8e − 6)(s2 + 9606s + 8.8e7)
The load resistance is R = 24Ω, and the ripple current is Iripple = 0.2 sin(2π120t)A. B. 120 Hz ripple sharing between iL and iC Fig. 9 shows the effect of ζ1 for 120 Hz ripple current sharing between inductor current iL and capacitor current iC . Clearly, smaller values of ζ1 impart notch-like effects at 120 Hz, thereby reducing the magnitudes of 120 Hz ripple in inductor currents. The model and controller parameters are chosen as before.
k=1
then the output current at the DC-link get divided in the ratio m P α1 : α2 : .... : αm , where 0 ≤ αk ≤ 1, and αk = 1; k=1
more precisely the steady-state zero-frequency components |i1 (j0)| : |i2 (j0)| : · · · : |im (j0)| are in the same proportion as α1 : α2 : .... : αm . (k) 3. [Ripple Sharing]: If further the parameters ζ1 are chosen m P (k) β ζ such that ζ1 = kαk1,n , where βk = 1, and 0 ≤ βk ≤ k=1
1, ∀k ∈ {1, .., m}, then, the proposed design distributes the load current ripple (at 120Hz) in the ratio β1 : β2 : ... : βm ; more precisely the steady-state 120 Hz-frequency components |i1 (j2π120)| : |i2 (j2π120)| : · · · : |im (j2π120)| are in the same proportion as β1 : β2 : ... : βm . Proof: see appendix V. CASE STUDIES: SIMULATIONS In this section, we report simulation case studies, which use non-ideal components (such as diodes with non-zero breakdown voltage, IGBT switches, stray capacitances, parametric uncertainties) and switched level implementation to include nonlinearities associated with real-world experiments. A. Voltage regulation in presence of parametric uncertainties Conventional proportional-integral (PI) based control designs exhibit satisfactory performance when the actual system parameters (L and C) lie ‘close’ to nominal system parameters. However, a slight deviation from the nominal values of L and C may result in rapid degradation in the tracking performance. This issue becomes even more critical for a disturbance rejection framework, where a controller is designed without the knowledge of the uncertain load. The H∞ robust control framework, where we seek an optimizing controller with guaranteed margins of robustness to modeling uncertainties will be adopted. Fig. 8a shows the tracking performance of a boost converter for a 20% uncertainty in both L and C values. The controller is designed for a boost converter with nominal L = 2.4mH and C = 400µF, while the actual system parameters are chosen as L = 2mH and C = 500µF. The input source voltage Vg and the output desired voltage Vdes are chosen to be 12V and 24V, respectively. The design parameters for the innercontroller Kc are: damping ratios ζ1 = 3.2 and ζ2 = 4.5,
Fig. 9: Bode plots of inner-shaped plants G˜c and inductor currents for different ζ1 . While the average (or DC) current remains the same as desired, the smaller values of ζ1 result in relatively smaller magnitudes of 120 Hz ripple in inductor currents.
C. Average current sharing between two converters Fig. 8b shows the average current sharing between two different converters with inputs Vg1 = 12V and Vg2 = 10V, respectively for two scenarios - (1) α1 = 0.5, α2 = 0.5, and (2) α1 = 0.7, α2 = 0.3. The other model and system parameters are chosen as before. D. Average 120 Hz ripple sharing between two converters Fig. 8c shows the average 120 Hz ripple sharing between the two converters for two scenarios - (1) β1 = 0.5, β2 = 0.5, and (2) β1 = 0.7, β2 = 0.3. The other model and system parameters are chosen as before. Note that the converters are tuned for equal average current sharing, i.e. α1 = 0.5, α2 = 0.5. Thus all the objectives of the control synthesis procedure: robust voltage regulation, load power demand shared in a prescribed ratio, and the ripple current shared in a prescribed ratio are simultaneously met by our design. APPENDIX E. Proof of Theorem 1: Performance Equivalence Proof: Let Sn and Tn denote the sensitivity and complementary sensitivity transfer functions of the singleconverter system, respectively (as described in (5)). For any converter k in the multi-converter system in Fig. 7, we have ˜ c Kv (Vdes − V − n). However from Figs. ik = γk Dk0 G k
(a) (b) (c) Fig. 8: (a)Voltage regulation in presence of modeling uncertainties and 120 Hz ripple at the output. The inner-outer controller regulates the output voltage to the desired voltage, Vdes = 24V. (b) Average current (power) sharing between two converters in the ratios 1 : 1 and 7 : 3. (c) ω0 average ripple sharing between two converters in the ratios 1 : 1 and 7 : 3.
(6) and (7), we observe that V = Gv P 0 ˜ 0 ˜ k γk Dk Gck = Dn Gc,n yields
m P
ik − d . Thus
(11)
γk ˜ c Kv (Vdes − V − n). (12) Gc Kc Sk iref = sLk γk G k Gck | k {z k } ˜c G k
Thus, using
P
k
˜ c,n , we have ˜ c = Dn0 G γk Dk0 G k
0 X D0 k ˜ c,n Kv (Vdes − V − n) = Dn u ˜, u ˜k = sDn0 G Lk L
(13)
k
which establishes the required equivalence. F. Proof of Theorem 1: Power Sharing Proof: Note that from Fig. (7), we have ˜ c (s)iref (s). ik (s) = γk Dk0 G k
(14)
˜ c (j0)| = 1 and with the Thus, using the fact that |G k given choice of the parameter γ =P (αk Dn0 /Dk0 ), we obtain k P (|ik (j0)|/ k |ik (j0)|) = (γk Dk0 / k γk Dk0 ) = αk . Thus, the steady-state zero-frequency component of the output current at the DC-link gets divided in the ratio α1 : α2 : .... : αm . G. Proof of Theorem 1: 120 Hz ripple sharing ˜ c (jω0 )| = Proof: From (14) and observing that |G k (k) ζ ω ˜ 1 , the ratio of 120 Hz ripple magnitude in jω0 + ω ˜ ζ2,n m P 0 steady-state is given by |ik (jω0 )|/ |ik (jω0 )| = k0 =1 m P (k) (k0 ) γk Dk0 ζ1 / . Substituting γk Dk = αk Dn0 γk0 Dk0 0 ζ1 0 k =1 m m P P (k) and αk ζ1 = ζ1,n yields |ik (jω0 )|/ |ik0 (jω0 )| k=1 k0 =1 (k) = αk ζ1 /ζ1,n . But, by our choice of the damping
parameters,
(k)
ζ1
=
(βk ζ1,n /αk ),
m P
|ik0 (jω0 )|
=
βk . Thus, the ripple
currents get divided in the ratios, β1 : β2 : ... : βm .
which is equivalent to the map Vdes − V in (2) for a single1 converter system. Similarly, let Gck = denote the innersLk plant in the kth converter, then from Fig. (6), it can be shown that u ˜k =
|ik (jω0 )|/
k0 =1
k=1
Vdes − V = Sn Vdes + Gv Sn d + Tn n,
yields
R EFERENCES [1] N. Hatziargyriou, H. Asano, R. Iravani, and C. Marnay, “Microgrids,” Power and Energy Magazine, IEEE, vol. 5, no. 4, pp. 78–94, 2007. [2] V. J. Thottuvelil and G. C. Verghese, “Analysis and control design of paralleled dc/dc converters with current sharing,” in Applied Power Electronics Conference and Exposition, 1997. APEC’97 Conference Proceedings 1997., Twelfth Annual, vol. 2. IEEE, 1997, pp. 638– 646. [3] D. Sha, Z. Guo, and X. Liao, “Cross-feedback output-current-sharing control for input-series-output-parallel modular dc–dc converters,” Power Electronics, IEEE Transactions on, vol. 25, no. 11, pp. 2762– 2771, 2010. [4] Y. Panov, J. Rajagopalan, and F. C. Lee, “Analysis and design of n paralleled dc-dc converters with master-slave current-sharing control,” in Applied Power Electronics Conference and Exposition, 1997. APEC’97 Conference Proceedings 1997., Twelfth Annual, vol. 1. IEEE, 1997, pp. 436–442. [5] J. M. Guerrero, J. Matas, L. G. de Vicu˜na, M. Castilla, and J. Miret, “Decentralized control for parallel operation of distributed generation inverters using resistive output impedance,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 2, pp. 994–1004, 2007. [6] C. Olalla, R. Leyva, A. El Aroudi, P. Garces, and I. Queinnec, “Lmi robust control design for boost pwm converters,” IET Power Electronics, vol. 3, no. 1, pp. 75–85, 2010. [7] G. Weiss, Q.-C. Zhong, T. C. Green, and J. Liang, “H repetitive control of dc-ac converters in microgrids,” Power Electronics, IEEE Transactions on, vol. 19, no. 1, pp. 219–230, 2004. [8] T. Hornik and Q.-C. Zhong, “A current-control strategy for voltagesource inverters in microgrids based on and repetitive control,” Power Electronics, IEEE Transactions on, vol. 26, no. 3, pp. 943–952, 2011. [9] S. Salapaka, B. Johnson, B. Lundstrom, S. Kim, S. Collyer, and M. Salapaka, “Viability and analysis of implementing only voltagepower droop for parallel inverter systems,” in Decision and Control (CDC), 2014 IEEE 53rd Annual Conference on. IEEE, 2014, pp. 3246–3251. [10] D. J. Ashley, L. J. Hitchcock, and M. J. Johnson, “Current share circuit for dc to dc converters,” May 28 1996, uS Patent 5,521,809. [11] I. Batarseh, H. Al-Atrash, and K. Rustom, “Method and system for balancing power distribution in dc to dc power conversion,” Jan. 12 2010, uS Patent 7,646,116. [12] R.-H. Wu, T. Kohama, Y. Kodera, T. Ninomiya, and F. Ihara, “Loadcurrent-sharing control for parallel operation of dc-to-dc converters,” in Power Electronics Specialists Conference, 1993. PESC’93 Record., 24th Annual IEEE. IEEE, 1993, pp. 101–107. [13] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. Springer Science & Business Media, 2007. [14] S. Oucheriah and L. Guo, “Pwm-based adaptive sliding-mode control for boost dc–dc converters,” Industrial Electronics, IEEE Transactions on, vol. 60, no. 8, pp. 3291–3294, 2013. [15] S. Skogestad and I. Postlethwaite, Multivariable feedback control: analysis and design. Wiley New York, 2007, vol. 2.
arXiv:1604.03573v1 [math.OC] 12 Apr 2016
Mayank Baranwal1,a , Srinivasa M. Salapaka1,b and Murti V. Salapaka2,c Abstract— This paper addresses the problem of output voltage regulation for multiple DC-DC converters connected to a grid, and prescribes a robust scheme for sharing power among different sources. Also it develops a method for sharing 120 Hz ripple among DC power sources in a prescribed proportion, which accommodates the different capabilities of DC power sources to sustain the ripple. We present a decentralized control architecture, where a nested (inner-outer) control design is used at every converter. An interesting aspect of the proposed design is that the analysis and design of the entire multi-converter system can be done using an equivalent single converter system, where the multi-converter system inherits the performance and robustness achieved by a design for the single-converter system. Another key aspect of this work is that the voltage regulation problem is addressed as a disturbance-rejection problem, where unknown load current is viewed as an external signal, and thus, no prior information is required on the nominal loading conditions. The control design is obtained using robust optimalcontrol framework. Case studies presented show the enhanced performance of prescribed optimal controllers.
I. INTRODUCTION In power network topologies, especially in microgrids [1], multiple DC power sources connected in parallel (see Figure 1), each interfaced with DC-DC converter, provide power at their common output, the DC-link, at a regulated voltage; this power can directly feed DC loads or be used by an inverter to interface with AC loads . Voltage controllers form an integral component of DC-DC converters in such systems. A paralleled architecture for multiple power sources is preferred since it enables higher output power, higher reliability and ease of use [2]. Here two main control architectures are adopted - (1) master-slave control, where the voltage regulation error from the master converter is utilized to provide an error signal to all the parallel connected converters [2], [3], (2) decentralized control, where each converter utilizes an independent and variable voltage reference depending on the output of each unit [4], [5]. Irrespective of the control framework, controllers at each converter are to be designed such that the voltage at the DClink is regulated at a prescribed setpoint. Another important control objective is to ensure that the DC sources provide power in a prescribed proportion, which may be dictated by their power ratings or external economic criteria. The main challenges arise from the uncertainties in the size and the schedules of loads, the complexity of a coupled multiconverter network, the uncertainties in the model parameters 1 Department of Mechanical Science and Engineering, University of Illinois at Urbana-Champaign, IL 61801, USA 2 Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA a [email protected], b [email protected] c [email protected]
Fig. 1: A schematic of a microgrid. An array of DC sources provide power for AC loads. Power sources provide power at DC-link, their common output bus, at a voltage that is regulated to a setpoint. The control system at the respective DC-DC converter that interfaces with a source is responsible for regulating the voltage at he DC-link. An inverter that connects to the DC-link converts the total current from the sources at the regulated voltage to alternating current (AC) at its output to satisfy the power demands of the AC loads. This paper describes an approach for control design of the multiple converters systems associated with power transfer from sources to the DC-link (shown by the dotted line).
at each converter, and the adverse effects of interfacing DC power sources with AC loads, such as the 120 Hz ripple that has to be provided by the DC sources. Problems related to robust and optimal design of converter controllers have received recent attention. In [6], a linearmatrix-inequality (LMI) based robust control design for boost converters has resulted in significant improvements over conventional PID-based controllers. Use of H∞ framework in context of inverter systems has also been studied in [7]–[9]. While the issue of current sharing is extensively studied [4], [10]–[12], most methods assume a single power source. A systematic control design that addresses all the challenges and objectives for the multi-converter control is still lacking. In this paper, we develop a control architecture that addresses the following primary objectives for multi-converter control - (1) voltage regulation at the DC-link while guaranteeing robustness of the closed-loop system performance to load and parametric uncertainties, (2) prescribed power sharing among a number of parallel converters, (3) controlling the tradeoff between 120 Hz ripple on the total current provided by the power sources and the ripple on the DC-link voltage, and (4) 120 Hz DC output ripple sharing among converters. The tradeoffs with 120 Hz ripple in objectives
(3) and (4) result from a direct consequence of interfacing DC-power sources with AC loads (see Figure 1). If we assume negligible power losses at the inverter and the load bus, the power provided by power sources at the DC-link should equal to the power consumed by the AC loads, that is, V¯ I¯ V i = (V¯ sin ω ¯ t)(I¯ sin(¯ ω t + φ)) = (cos φ + cos(2¯ ω t + φ). 2 Since the instantaneous power has a 2¯ ω = 120 Hz ripple, the P current i = ik at the DC-link has to provide for this 120 Hz component. The total ripple demand posed by the ACgrid side is met partly by the ripple current sourced by a capacitor iC which reduces the magnitude of the ripple current to be provided by the DC source via the converters. However, greater the ripple magnitude in the capacitor current greater will be the ripple in the capacitor voltage, thus adversely affecting voltage regulation. Therefore a compromise has to be reached in the allowable ripple in the capacitor current and the ripple provided by the DC sources. The control scheme presented in the article provides a “knob” to adjust the relative ratio of how the 120 Hz ripple is shared between the two quantities - the sourced current i and the output voltage V . Moreover in a scenario where multiple and different types of DC sources are employed, it is often the case that the tolerance to ripple varies. Here it becomes important to allocate greater percentage of ripple load to tolerant DC sources while reducing the ripple load on vulnerable DC sources. The article presents a controller synthesis procedure where the 120 Hz ripple on the current i can be shared among the paralleled DC sources (ik ) in a pre-specified proportion. An important aspect of the proposed control architecture is that it is decentralized and addresses all the objectives simultaneously. Moreover we show that for the control approach described in the paper, the control design and the closed-loop analysis of the multi-converter system can be completely characterized in terms of an appropriate single-converter system; thereby significantly reducing the complexity in addressing multi-converter systems. This architecture exploits structural features of the paralleled multi-converter system, which results in a modular and yet coordinated control design. For instance, it exploits that the voltage regulation objective is common to all the converters, and that the differences in demands on different converters are mainly in terms of their output currents; accordingly at each converter, it employs a nested (outer-voltage inner-current) control structure [13], where the outer loop is responsible for robust voltage regulation and the inner loop for shaping the currents. The structure of control for each inner-loop is so chosen that the entire closed-loop multi converter system can be reduced to an equivalent single-converter system in terms of the transfer function from the desired regulation setpoint Vdes to the voltage V . Furthermore, for the outer-control design, the load current is treated as an external disturbance and the voltage regulation problem is cast as a disturbance rejection problem in an optimal control setting. This design, besides achieving the voltage-regulation objective, provides robustness to deviations from the structural assumptions in the control design. Note that this viewpoint is in contrast to typical methods in existing literature, where voltage regulation in presence of unknown loads is addressed either using
adaptive control [14], or by letting the voltage droop in a controlled manner. II. M ODELING OF CONVERTERS In this section, we provide dynamic models for DC-DC converters, which convert a source of direct current (DC) from one voltage level to another. The models presented below depict dynamics for signals that are averaged over a switch cycle. A schematic of the Boost converter is shown in Fig. 2(a). A dynamic model (averaged over switching cycles) is given by, C V˙ (t) = (1−d(t))iL (t)−iload ,
Li˙L (t) = −(1−d(t))V (t)+Vg ,
where d(t) represents the duty-cycle (or the proportion of ON duration) at time t, which by defining d0 (t) = 1 − d(t) Vg and D0 = Vdes can be rewritten as Li˙L (t) = −d0 (t)V (t) + Vg , | {z } u ˜ (t):=Vg −u(t)
C V˙ (t) = (D0 + dˆ0 )iL (t) − iload . | {z } ≈D 0
Here Vdes represents the desired output voltage and dˆ = d0 (t) − D0 is typically very small, which allows for a linear approximation around the nominal duty-cycle, D = 1 − D0 given by, L
diL (t) =u ˜(t), dt
C
dV (t) ≈ D0 iL (t) − iload . dt
Fig. 2(b) depicts the circuit schematic of a buck converter with an ideal switch. The averaged model of a buck converter is given by, L
diL (t) = −V (t) + d(t)Vg , dt | {z }
C
dV (t) = iL (t) − iload . dt
u ˜ (t):=−V (t)+u(t)
The electronic circuit of a buck-boost converter is shown in Fig. 2(c). As in case of a boost converter, we define des nominal duty-cycle, D = VdesV−V = 1 − D0 . A linear g approximation of the above dynamical equations yields, Li˙L (t) = V (t) + d(t)(Vg − V (t)), | {z }
C V˙ (t) ≈ −D0 iL (t) − iload
u ˜ (t):=V (t)+u(t)
III. C ONTROL FRAMEWORK FOR A SINGLE - CONVERTER In this section, we describe the inner-current outer-voltage control architecture for a single DC-DC converter. The key objectives of the control design are - (1) voltage regulation in presence of uncertain loads, and (2) 120 Hz ripple sharing control between iL and iC . We first consider the case of a boost converter control design, the dynamics of which is given by iL (s) =
1 (Vg (s) − u(s)), sL
V (s) =
1 (D0 iL (s) − iload (s)), sC (1)
and the corresponding block-diagram representation of above set of equations is shown in Fig. 3, the control objectives are to design u (equivalently u ˜) such that voltage regulation error Vdes − V is made small irrespective of load disturbances iload and variations in parameters L and C, and achieve a prescribed tradeoff between |iL (j2π120)| and |iC (j2π120)|. These two objectives are achieved using a nested innercurrent outer-voltage control architecture, shown in Fig. 4
(a) (b) (c) Fig. 2: Circuit representing (a) Boost converter, (b)Buck converter, and (c) Buck-Boost converter. Note that iload includes both the nominal load current, as well as ripple current. The converters are assumed to operate in continuous-conduction-mode (CCM). Boost converters step up the voltage at the output, while buck converters step down the voltage. A buck-boost converter can achieve both the objectives.
Fig. 3: Block diagram representation of a boost-type converter. The control signal u ˜ is converted to an equivalent PWM signal to command the gate of the transistor acting as a switch. 1 1 (here Gc = sL and Gv = sC ). The voltage controller Kv generates a current reference for the current controller Kc . The current controller Kc is designed to achieve a high closed inner-loop bandwidth with ripple control as an objective, whereas the voltage controller Kv is designed to achieve a relatively lower closed outer-loop bandwidth with DC (zero frequency) voltage regulation as its primary objective. We assume that the quantities - output voltage V and inductor current iL are available for measurement. Design of the outer-loop controller: For a given controller Kc for the inner-loop, the closed outer-loop signals of interest are given by (see Figure 4)
Vdes − V
=
iL
=
iref
=
SVdes + Gv Sd + T n ˜ c Kv SVdes + 1 T d − Kv G ˜ c Sn G D0 Kv (SVdes + Gv Sd) − Kv Sn,
(2) (3) (4)
where d denotes the load current iload (shown as disturbance ˜c to the plant), n denotes the voltage measurement noise, G represents the closed inner-loop transfer function from iref to iL , and T (s) and S(s) are closed-loop complementary sensitivity and sensitivity transfer functions respectively, described by, T (s)
=
S(s)
=
˜ c Kv )−1 (Gv D0 G ˜ c Kv ), (I + Gv D0 G 0 ˜ −1 (I + Gv D Gc Kv ) .
(5)
The voltage-regulation objective, as evident from Eq. 2,
frequencies where disturbance d is prominent. However this implies that the effect of d on the inductor current iL (see Eq. 3) is larger since |T (jω)| is larger in those frequencies (from Eq. 5). Therefore there is a fundamental trade-off between voltage regulation and minimizing effects of disturbances (or load current iload ) in iL . Also to diminish the effect of noise on voltage regulation, the control design should be such that the closed-loop map T rolls of at frequencies beyond the disturbance bandwidth. Furthermore low iref is ensured if Kv S can be made small. The controller Kv is obtained by casting these multiple objectives in the following optimal control problem [15],
Ws S
min Wu Kv S Kv ∈K Wt T
design. Exogenous signals Vdes and iload represent the desired output voltage and disturbance, respectively. The quantities V and iL represent the available measurements.
requires designing Kv such that |S(jω)| is small at the
,
(6)
∞
where the weights Ws , Wt and Wu are chosen to reflect the design specifications of robustness to disturbances and parametric uncertainties, tracking bandwidth, and saturation limits on the control signal. For example, the weight function Ws (jω) is chosen to be large in frequency range [0, ωBW ] to ensure a small tracking error e = Vdes − V in this frequency range. The weight function Wt (jω) is designed as a high-pass filter to ensure that T (jω) is small at high frequencies to provide mitigation to measurement noise. The design of constant Wu entails ensuring that the control effort lies within saturation limits. The resulting controller is robust to disturbances up to ωBW , which accounts for variations in load disturbances as well as parametric uncertainties. Design of the inner-loop controller: The outer-loop con˜ c . Here we trol design assumed the inner closed-loop G propose an inner-loop control design that results in a second˜ c , thereby ensuring a relatively loworder transfer function G order optimal controller Kv . The main objective for designing the inner-loop controller Kc is to decide the trade-off between the 120 Hz ripple on the voltage V (equivalently on the capacitor current ic ) and the output current i (equivalently iL ) of the converter. Accordingly, we design Kc such that ˜ c (s) = G
Fig. 4: Block diagram representation of the inner-outer control
ω ˜ s+ω ˜
s2 + 2ζ1 ω0 s + ω02 s2 + 2ζ2 ω0 s + ω02
,
(7)
where ω0 = 2π120 rad/s. ω ˜ , ζ1 , ζ2 are design parameters. Here the parameter ω ˜ > ω0 is simply chosen to implement a low-pass filter that attenuates undesirable frequency content ˜ c , there is a in iL beyond ω ˜ . Note that in this design of G notch at ω0 = 120 Hz, the size of this notch is determined by the ratio ζζ21 (see Figure 5). Lower values of this ratio correspond to larger notches, which in turn imply smaller 120 ˜ c represents the inner closedHz component in iL , since G loop transfer function from iref to iL . Furthermore since iC = iload − iL , this in turn implies higher ripples in iC . Thus the ratio ζζ21 can be appropriately designed to achieve a specified
tradeoff between 120 Hz ripple on iC and iL . The stabilizing
˜ c for Fig. 5: Bode magnitude plots of the closed-loop plant G
Fig. 6: Control framework for a many-converters system. Note that
various ζ1 values. ω ˜ is chosen to be 600π rad/s. Note that a relatively larger value of ω ˜ is in accordance with choosing a fast inner-current controller.
in the proposed implementation, we adopt the same outer controller for different converters, i.e., Kv1 = Kv2 = .... = Kvm = Kv .
second-order controller Kc that yields the above closed-loop ˜ c is explicitly given by, plant G
duty-cycle Dn = 1 − Dn0 . Then by appropriately designing individual inner-loop parameters, we can design the nominal closed inner-loop plant to be given by
Kc = L˜ ω
s2 + 2ζ1 ω0 s + ω02 , (s2 + 2ζ2 ω0 s + 2(ζ2 − ζ1 )ω0 ω ˜ + ω02 )
(8)
˜ c,n (s) = G
ω ˜ s+ω ˜
s2 + 2ζ1,n ω0 s + ω02 s2 + 2ζ2,n ω0 s + ω02
,
(9)
which is again a low-order (second-order) controller design. Extension to buck and buck-boost converters: The extension of the proposed control design to Buck and BuckBoost DC-DC converters is easily explained after noting that their averaged models are structurally identical to Boost converters, except that the dependence of duty cycles on the control signal u or constant parameter D0 are different. The differences in how duty cycles depend on u(t) do not matter from the control design viewpoint since duty cycles for pulse-width modulation are obtained only after obtaining the control designs (that use the averaged models).
ζ1,n determines the tradeoff of 120 Hz ζP 2,n ripple between i = k ik and the capacitor current iC . Note that for the cumulative closed inner-loop plant in Figure 7 ˜ c,n (s), we require closed to behave as the nominal plant G inner-loop maps toP sum up to the nominal closed inner0 ˜ 0 ˜ loop plant, that is k γk Dk Gck = Dn Gc,n . Accordingly we design Kck in each inner loop such that
IV. E XTENSION TO A SYSTEM OF PARALLEL
where ζ1 are appropriately chosen to reflect the relative tradeoff of 120 Hz ripple among converter current outputs ik . Explicit design of such Kck exists and is analogous to the design in (8), which was obtained for the same structure of the inner-closed loop in the single-converter case. The parameters γk are designed to apportion power among the power sources, since DC gains of individual closed inner˜ ck D0 are equal to γk D0 since G ˜ c (j0) = 1 loop plants γk G k k k by design for all k. We make these design specifications more precise and bring out the equivalence of the control design for the single and multiple converter systems in the following theorem.
CONVERTERS
In this section we develop a decentralized control framework that achieves voltage regulation, power-sharing, and ripple-sharing among a system of parallel boost converters sharing a common load. A. Control framework for a system of parallel boost converters Fig. 6 represents a decentralized inner-outer control framework for a system of m parallel connected converters. Here we have incorporated a constant gain parameter γk at the inner-loop of kth converter, the choice of which dictates power sharing as will be shown below. After noting that the voltage-regulation objective is common to all outer controllers, in our architecture, we impose the same outercontroller for all the converters, i.e., Kv1 = Kv2 = .... = Kvm = Kv . This enables a significant reduction in complexity of the control design for the multi-converter system as will be shown below. First, with this assumption of Kvk = Kv , the general decentralized architecture in Figure 6 can be simplified as in Figure 7. This implies that Kv can be computed by solving H∞ -optimization problem (as discussed in the previous section) similar to the single converter case by assuming an available design for the summed closed inner-loop map ˜ c,n (the nominal closed inner-loop plant) and a nominal G
where the ratio
˜ c (s) = G k
ω ˜ s+ω ˜
(k)
s2 + 2ζ1 ω0 s + ω02 s2 + 2ζ2,n ω0 s + ω02
! ,
(10)
(k)
Fig. 7: A multiple-converters system with shaped inner plants. Note ˜ c share the same denominator as G ˜ c,n . that the shaped plants G k
Theorem 1: Consider the single-converter system in Fig˜ c,n (s) ure 4 with inductance L, D0 = Dn0 and G˜c = G as given in (9); and the multi-converter system described ˜ c (s) are given by (10), in 6 and 7 where G k P Figures P 0 ˜ 0 ˜ k γk Dk Gck = Dn Gc,n , and k γk = 1, γk > 0 for 1 ≤ k ≤ m. 1. [Performance Equivalence]: Any outer-loop controller Kv that stabilizes the single-converter system yields identical performance when applied to the multi-converter system; more precisely, for the same exogenous inputs - theP reference Vdes , the load disturbance iload , and noise n = k γk nk , Dn0 the steady-state regulated signals (Vdes − V, u ˜, V ) for the L single-converter system are the same as the regulated signals P D0 (Vdes − V, k k u ˜k , V ) for the multi-converter system. Lk (k) 2. [Power Sharing]: If the parameters γk , and ζ1 , 1 ≤ k ≤ m 0 P (k) αk Dn m are chosen such that γk = D and αk ζ1 = ζ1,n , 0 k
and ω ˜ = 2π300rad/s. The outer-controller Kv is obtained by solving the stacked H∞ optimization problem (see Eq. 6) [15] with the weighting functions: Ws = 0.5s+2π50 s+0.06π50 , s+2π40 Wu = 0.9, and Wt = 0.05s+2π80 . The resulting reduced fifth-order controller Kv is given by: Kv =
0.256(s + 113.9)(s + 0.001)2 (s2 + 4.05e4s + 5.65e8) (s + 9.56)(s2 + 0.002s + 4.8e − 6)(s2 + 9606s + 8.8e7)
The load resistance is R = 24Ω, and the ripple current is Iripple = 0.2 sin(2π120t)A. B. 120 Hz ripple sharing between iL and iC Fig. 9 shows the effect of ζ1 for 120 Hz ripple current sharing between inductor current iL and capacitor current iC . Clearly, smaller values of ζ1 impart notch-like effects at 120 Hz, thereby reducing the magnitudes of 120 Hz ripple in inductor currents. The model and controller parameters are chosen as before.
k=1
then the output current at the DC-link get divided in the ratio m P α1 : α2 : .... : αm , where 0 ≤ αk ≤ 1, and αk = 1; k=1
more precisely the steady-state zero-frequency components |i1 (j0)| : |i2 (j0)| : · · · : |im (j0)| are in the same proportion as α1 : α2 : .... : αm . (k) 3. [Ripple Sharing]: If further the parameters ζ1 are chosen m P (k) β ζ such that ζ1 = kαk1,n , where βk = 1, and 0 ≤ βk ≤ k=1
1, ∀k ∈ {1, .., m}, then, the proposed design distributes the load current ripple (at 120Hz) in the ratio β1 : β2 : ... : βm ; more precisely the steady-state 120 Hz-frequency components |i1 (j2π120)| : |i2 (j2π120)| : · · · : |im (j2π120)| are in the same proportion as β1 : β2 : ... : βm . Proof: see appendix V. CASE STUDIES: SIMULATIONS In this section, we report simulation case studies, which use non-ideal components (such as diodes with non-zero breakdown voltage, IGBT switches, stray capacitances, parametric uncertainties) and switched level implementation to include nonlinearities associated with real-world experiments. A. Voltage regulation in presence of parametric uncertainties Conventional proportional-integral (PI) based control designs exhibit satisfactory performance when the actual system parameters (L and C) lie ‘close’ to nominal system parameters. However, a slight deviation from the nominal values of L and C may result in rapid degradation in the tracking performance. This issue becomes even more critical for a disturbance rejection framework, where a controller is designed without the knowledge of the uncertain load. The H∞ robust control framework, where we seek an optimizing controller with guaranteed margins of robustness to modeling uncertainties will be adopted. Fig. 8a shows the tracking performance of a boost converter for a 20% uncertainty in both L and C values. The controller is designed for a boost converter with nominal L = 2.4mH and C = 400µF, while the actual system parameters are chosen as L = 2mH and C = 500µF. The input source voltage Vg and the output desired voltage Vdes are chosen to be 12V and 24V, respectively. The design parameters for the innercontroller Kc are: damping ratios ζ1 = 3.2 and ζ2 = 4.5,
Fig. 9: Bode plots of inner-shaped plants G˜c and inductor currents for different ζ1 . While the average (or DC) current remains the same as desired, the smaller values of ζ1 result in relatively smaller magnitudes of 120 Hz ripple in inductor currents.
C. Average current sharing between two converters Fig. 8b shows the average current sharing between two different converters with inputs Vg1 = 12V and Vg2 = 10V, respectively for two scenarios - (1) α1 = 0.5, α2 = 0.5, and (2) α1 = 0.7, α2 = 0.3. The other model and system parameters are chosen as before. D. Average 120 Hz ripple sharing between two converters Fig. 8c shows the average 120 Hz ripple sharing between the two converters for two scenarios - (1) β1 = 0.5, β2 = 0.5, and (2) β1 = 0.7, β2 = 0.3. The other model and system parameters are chosen as before. Note that the converters are tuned for equal average current sharing, i.e. α1 = 0.5, α2 = 0.5. Thus all the objectives of the control synthesis procedure: robust voltage regulation, load power demand shared in a prescribed ratio, and the ripple current shared in a prescribed ratio are simultaneously met by our design. APPENDIX E. Proof of Theorem 1: Performance Equivalence Proof: Let Sn and Tn denote the sensitivity and complementary sensitivity transfer functions of the singleconverter system, respectively (as described in (5)). For any converter k in the multi-converter system in Fig. 7, we have ˜ c Kv (Vdes − V − n). However from Figs. ik = γk Dk0 G k
(a) (b) (c) Fig. 8: (a)Voltage regulation in presence of modeling uncertainties and 120 Hz ripple at the output. The inner-outer controller regulates the output voltage to the desired voltage, Vdes = 24V. (b) Average current (power) sharing between two converters in the ratios 1 : 1 and 7 : 3. (c) ω0 average ripple sharing between two converters in the ratios 1 : 1 and 7 : 3.
(6) and (7), we observe that V = Gv P 0 ˜ 0 ˜ k γk Dk Gck = Dn Gc,n yields
m P
ik − d . Thus
(11)
γk ˜ c Kv (Vdes − V − n). (12) Gc Kc Sk iref = sLk γk G k Gck | k {z k } ˜c G k
Thus, using
P
k
˜ c,n , we have ˜ c = Dn0 G γk Dk0 G k
0 X D0 k ˜ c,n Kv (Vdes − V − n) = Dn u ˜, u ˜k = sDn0 G Lk L
(13)
k
which establishes the required equivalence. F. Proof of Theorem 1: Power Sharing Proof: Note that from Fig. (7), we have ˜ c (s)iref (s). ik (s) = γk Dk0 G k
(14)
˜ c (j0)| = 1 and with the Thus, using the fact that |G k given choice of the parameter γ =P (αk Dn0 /Dk0 ), we obtain k P (|ik (j0)|/ k |ik (j0)|) = (γk Dk0 / k γk Dk0 ) = αk . Thus, the steady-state zero-frequency component of the output current at the DC-link gets divided in the ratio α1 : α2 : .... : αm . G. Proof of Theorem 1: 120 Hz ripple sharing ˜ c (jω0 )| = Proof: From (14) and observing that |G k (k) ζ ω ˜ 1 , the ratio of 120 Hz ripple magnitude in jω0 + ω ˜ ζ2,n m P 0 steady-state is given by |ik (jω0 )|/ |ik (jω0 )| = k0 =1 m P (k) (k0 ) γk Dk0 ζ1 / . Substituting γk Dk = αk Dn0 γk0 Dk0 0 ζ1 0 k =1 m m P P (k) and αk ζ1 = ζ1,n yields |ik (jω0 )|/ |ik0 (jω0 )| k=1 k0 =1 (k) = αk ζ1 /ζ1,n . But, by our choice of the damping
parameters,
(k)
ζ1
=
(βk ζ1,n /αk ),
m P
|ik0 (jω0 )|
=
βk . Thus, the ripple
currents get divided in the ratios, β1 : β2 : ... : βm .
which is equivalent to the map Vdes − V in (2) for a single1 converter system. Similarly, let Gck = denote the innersLk plant in the kth converter, then from Fig. (6), it can be shown that u ˜k =
|ik (jω0 )|/
k0 =1
k=1
Vdes − V = Sn Vdes + Gv Sn d + Tn n,
yields
R EFERENCES [1] N. Hatziargyriou, H. Asano, R. Iravani, and C. Marnay, “Microgrids,” Power and Energy Magazine, IEEE, vol. 5, no. 4, pp. 78–94, 2007. [2] V. J. Thottuvelil and G. C. Verghese, “Analysis and control design of paralleled dc/dc converters with current sharing,” in Applied Power Electronics Conference and Exposition, 1997. APEC’97 Conference Proceedings 1997., Twelfth Annual, vol. 2. IEEE, 1997, pp. 638– 646. [3] D. Sha, Z. Guo, and X. Liao, “Cross-feedback output-current-sharing control for input-series-output-parallel modular dc–dc converters,” Power Electronics, IEEE Transactions on, vol. 25, no. 11, pp. 2762– 2771, 2010. [4] Y. Panov, J. Rajagopalan, and F. C. Lee, “Analysis and design of n paralleled dc-dc converters with master-slave current-sharing control,” in Applied Power Electronics Conference and Exposition, 1997. APEC’97 Conference Proceedings 1997., Twelfth Annual, vol. 1. IEEE, 1997, pp. 436–442. [5] J. M. Guerrero, J. Matas, L. G. de Vicu˜na, M. Castilla, and J. Miret, “Decentralized control for parallel operation of distributed generation inverters using resistive output impedance,” Industrial Electronics, IEEE Transactions on, vol. 54, no. 2, pp. 994–1004, 2007. [6] C. Olalla, R. Leyva, A. El Aroudi, P. Garces, and I. Queinnec, “Lmi robust control design for boost pwm converters,” IET Power Electronics, vol. 3, no. 1, pp. 75–85, 2010. [7] G. Weiss, Q.-C. Zhong, T. C. Green, and J. Liang, “H repetitive control of dc-ac converters in microgrids,” Power Electronics, IEEE Transactions on, vol. 19, no. 1, pp. 219–230, 2004. [8] T. Hornik and Q.-C. Zhong, “A current-control strategy for voltagesource inverters in microgrids based on and repetitive control,” Power Electronics, IEEE Transactions on, vol. 26, no. 3, pp. 943–952, 2011. [9] S. Salapaka, B. Johnson, B. Lundstrom, S. Kim, S. Collyer, and M. Salapaka, “Viability and analysis of implementing only voltagepower droop for parallel inverter systems,” in Decision and Control (CDC), 2014 IEEE 53rd Annual Conference on. IEEE, 2014, pp. 3246–3251. [10] D. J. Ashley, L. J. Hitchcock, and M. J. Johnson, “Current share circuit for dc to dc converters,” May 28 1996, uS Patent 5,521,809. [11] I. Batarseh, H. Al-Atrash, and K. Rustom, “Method and system for balancing power distribution in dc to dc power conversion,” Jan. 12 2010, uS Patent 7,646,116. [12] R.-H. Wu, T. Kohama, Y. Kodera, T. Ninomiya, and F. Ihara, “Loadcurrent-sharing control for parallel operation of dc-to-dc converters,” in Power Electronics Specialists Conference, 1993. PESC’93 Record., 24th Annual IEEE. IEEE, 1993, pp. 101–107. [13] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. Springer Science & Business Media, 2007. [14] S. Oucheriah and L. Guo, “Pwm-based adaptive sliding-mode control for boost dc–dc converters,” Industrial Electronics, IEEE Transactions on, vol. 60, no. 8, pp. 3291–3294, 2013. [15] S. Skogestad and I. Postlethwaite, Multivariable feedback control: analysis and design. Wiley New York, 2007, vol. 2.
