Sampled-analog Implementation Of Application-specific ... - IEEE Xplore
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 5, NO. 3, AUGUST 1997
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Sampled-Analog Implementation of Application-Specific Fuzzy Controllers U˘gur Cilingiro˘ ¸ glu, Member, IEEE, Banu Pamir, Student Member, IEEE, Z. Sezgin G¨unay, and Fikret D¨ulger
Abstract— Sampled-analog circuit techniques are exploited in an application-specific integrated fuzzy controller design. A circuit library comprising a sample-and-hold amplifier, positive and negative ramp amplifiers, an inference cell, adder, and weighted adder amplifiers, and a divider unit was developed for this purpose. Any expert system of piecewise linear input membership functions, conjunctive rules and singleton output classes can be implemented with this library. The library was implemented in a 1.2 m double-metal double-poly CMOS technology. Test results indicate excellent linearity and accuracy in full 5-V railto-rail operation in all units. A controller of four inputs, 16 rules, and two outputs fabricated with these library units occupies 1.76 mm2 silicon. Test results indicate full functionality. The measured speed, 85 k samples per second, is limited by the unbuffered outputs. Sampling rate can be increased by 50% in those applications where pipelining is permissible. Index Terms—Controller, sampled analog.
I. INTRODUCTION
F
UZZY logic has been developed over the past three decades into a widely applied technique in classification and control engineering. This logic can be implemented in one of the following forms: 1) software simulation, which is highly cost effective if volume production is not demanded, and neither portability nor processing speed is critical; 2) microprocessor or microcontroller implementation, which is most suitable for low-volume production of slow but portable systems; 3) using a field-programmable or reconfigurable fuzzy processor chip, which offers high speed to portable systems in low-volume production; 4) using an application-specific (ASIC) fuzzy processor chip, which offers high speed in a cost-effective way for portable systems in high-volume production [1]. Quite obviously, the last two of these implementation styles require fuzzy-specific chip design. Indeed, numerous simulated or partially integrated architectures have been proposed in the past decade to fulfill this need [2]–[12]. Publications on fully integrated fuzzy-system chips, however, are relatively rare. One of these involves a digital fuzzy-controller [13].
Manuscript received December 5, 1995; revised December 12, 1996. This work was supported in part by the Technology Development Foundation of Turkey and by Ar¸celik A. S.. ¸ The authors are with the ETA Design Center and Department of Electronics ¨ Ayaza˘ga Kamp¨us¨u, and Communication, ˙Istanbul Technical University, ˙ITU Maslak-80626, ˙Istanbul, Turkey. Publisher Item Identifier S 1063-6706(97)04841-8.
This chip can be configured for the modes 4-in/2-out/51-rules and 2-in/1-out/102-rules; it features full programmability of membership functions and rules and offers a 6-b input/output (I/O) resolution and a 4-b internal resolution. Device count is above 680 k and chip size in 1.1- m CMOS is 70.14 mm . Another fully integrated programmable fuzzy controller chip, exploiting sampled analog-circuit techniques for internal processing, is described in [14]. It can be configured for up to eight inputs and four outputs, each transformable into seven classes at most. Rule capacity is 32, precision is 6 b, and chip size in 0.8- m CMOS is 70 mm . The current-based analog ASIC described in [15] is another example of fully integrated fuzzy controller. This chip is mask programmed to a configuration of 2-in/1-out/9-rules with three classes per input or output. Although the exemplar configuration is less sophisticated than those described above, the architecture still reflects the silicon area saved by omitting field programmability: The controller contains only 500 devices and fits into 0.4-mm silicon in 1.2- m CMOS. The chip we describe in this paper is another example of the ASIC approach to fully integrating a fuzzy controller on silicon. However, our approach relies on sampled analogcircuit techniques, which not only naturally provide for analogvoltage representation of I/O variables and, thus, reduce interface complexity, but also lead to a more accurate representation of the algorithm. The accuracy stems from the fact that internal parameters are determined solely by capacitance ratios instead of MOSFET current ratios. The dedicated configuration of this chip is 4-in/2-out/16-rules. It contains a total of 11 input and seven output classes and measures 1.76 mm in 1.2- m CMOS. In Section II, we present architectural features of the controller. The fuzzifier, inference engine, and defuzzifier modules are discussed in Sections III–V, respectively. Implementation and test results are the subject of Section VI. Finally, conclusions are presented in Section VII. II. ARCHITECTURAL FEATURES In a typical fuzzy-controller algorithm, data are processed in three successive computational steps. Namely, fuzzification, inference, and defuzzification. In each step, however, multiple channels of data are treated in parallel. An architectural schematic of a fuzzy controller hardware is shown in Fig. 1. It comprises blocks of three main processor modules marked fuzzifier module, inference module, and defuzzifier module, and two routing matrices interconnecting these three successive
1063–6706/97$10.00 1997 IEEE
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Fig. 1. Architecture of a fuzzy controller.
blocks. In a sampled analog implementation, inclusion of a data-path controller block is also necessary for properly processing and shifting data from input to output. Each fuzzifier module transforms a sampled and held input variable into a degree of membership in one fuzzy input-class. Therefore, one such module is required for each fuzzy input class. In the present implementation, membership functions are assumed to be piecewise linear such as trapezoid, triangle, or ramp. Each inference module calculates the truth value of one fuzzy rule. A fuzzy rule is assumed to be a conjunctive proposition of antecedent terms. Each such term is represented by a degree of membership generated by some fuzzifier module. The truth value is calculated from . Each defuzzifier module generates one crisp output (control) variable from truth values transmitted from the inference block. We adopt the method of weighted-average of singletons for defuzzification, which prescribes
(1)
where, is the singleton value of the output class associated with rule and is the truth value of the same rule. All of the fuzzy variables , , , , and parameter can be represented, without loss of generality, with real numbers in between zero and one. The corresponding electrical variables in the present implementation are voltages defined generally as where is a fuzzy variable and is the supply voltage. III. THE FUZZIFIER MODULE As pointed out in Section II, a fuzzifier module is expected to implement a piecewise linear membership function. Generally, the following three different functions are required: 1) positive ramp; 2) negative ramp; and 3) trapezoid or triangle. As shown in Fig. 2, however, a trapezoidal or triangular membership function can be generated with a pair of
Fig. 2. Generating a trapezoidal or triangular membership function with a pair of positive and negative ramp function.
positive and negative ramp functions follows:
and
as
Since fuzzifier outputs are fed into inference modules, which are supposed to perform a min operation anyway, an can be implemented by feeding a pair of and into the same inference module. Therefore, all membership functions can be realized solely with ramp functions, which are implemented in the present design with the switched-capacitor (SC) voltage amplifier configuration, shown in Fig. 3(a). This amplifier is a derivative of the stray insensitive SC integrator proposed in [16] and is built around a nondifferential resettable core amplifier that has a large negative open-loop gain around a self-reference level between the two rail levels, as depicted in Fig. 3(b). The core amplifier is a PSRR-enhanced version of the operational inverter (OPI), reported in [17]. It mainly consists of three CMOS inverter stages, the first of which is power supplied via source followers to enhance power supply rejection ratio (PSRR) and the third is equipped with a very simple compensation network. In a 1.2- m mainstream technology it merely occupies 46 m 56 m silicon. The amplifier configuration of Fig. 3(a) operates in a twophase nonoverlapping clock scheme. Input and output nodes of OPI are reset to by a feedback switch during the reset phase. In the positive-ramp amplifier configuration, the lower plate of receives input during this phase, while those of and are tied to ground. In the following evaluation phase, the resetting feedback of OPI is removed and, thus, the input node of OPI enters a high-impedance state. However, a closed-loop operation is established via the capacitor while the bottom plate of is tied to ground and that of is
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(a)
(b)
(c)
Fig. 4. The sample-and-hold unit.
(d)
Fig. 3. (a) The amplifier configuration implementing ramp functions V(PR) and V(NR) for fuzzification. (b) The transfer characteristic of the core amplifier OPI. (c) Positive-ramp output versus input voltage. (d) Negative-ramp output versus input voltage.
connected to by
. Output in the evaluation phase is described
for
(2)
where (3) and (4) and , OPI remains Within the input range limited by nonsaturated. Any input voltage outside this range forces . The characteristic OPI output to saturate at 0 V or described by (2) and depicted in Fig. 3(c) is typical of a positive-ramp function. Note that the grade and offset of the and ramp are determined solely by the capacitive ratios , whereas the two saturation levels are determined by rail voltages. The amplifier configuration of Fig. 3(a) is transformed into negative-ramp amplifier by interfacing, as indicated in parentheses. In this case, the output in the evaluation phase is described by for
Fig. 5. An
m-input
inference module.
where and are still defined by (3) and (4), respectively. The resulting versus characteristic is depicted in Fig. 3(c). Again, the gain and offset are determined by the and . capacitive ratios The negative-ramp amplifier is not a sampling amplifier because it generates a valid output in the same evaluation
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(b) Fig. 6. HSPICE transient waveforms of a seven-input inference module. Output waveform is shown in solid line. Input voltages differ by 20 mV in the range. (a) 0–0.12 V. (b) 4.88–5.00 V.
phase as the input is received. For this reason, the controller prior to input variables ( ) are sampled and held as fuzzification. The sample-and-hold units used for this purpose are constructed as a unity-gain zero-offset version of the
positive-ramp amplifier, as shown in Fig. 4. These units also have a rail-to-rail functionality. In summary, a fuzzifier module contains a single noninverting or inverting amplifier for a positive or negative ramp
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Fig. 8. Adder and weighted adder circuit schematic. Fig. 7. Block diagram of the defuzzifier module.
function, but a pair of noninverting and inverting amplifiers for a trapezoidal or triangular function. IV. THE INFERENCE MODULE Fig. 5 shows the circuit diagram of an -input inference module. It is a derivative of the maxnet configuration described in [18]. The circuit comprises identical cells, each assigned to one input. A cell is built around a competition node, e.g., in Cell-1. This node has a pull-down path via NMOS and a pull-up path via a parallel network of PMOS devices placed in series with a PMOS . The gate of each device in the parallel network is controlled by the competition node of another cell. A total of such control paths establish mutually inhibitory connections among all cells so that when all and are on, the module converges to a stable state in which one and only one competition node remains at 0 V and the others are pulled up to a voltage above , where is the absolute value of the PMOS device-threshold voltage. This is guaranteed by ratioing and in such a way that even if a single PMOS device in a parallel pull-up net receives 0 V at its gate, the competitionnode voltage of that cell exceeds . In a stable state, therefore, the parallel pull-up network of the cell of 0-V node voltage is completely cut off, whereas all other cells’ nodes are pulled up by one device in each parallel pull-up net. Having described the stable state of the interconnected competition nodes, we now explain the sequence of operations in the entire inference module and illustrate it with the SPICE transient analysis results, shown in Fig. 6. All inputs , are transferred onto the competition nodes of separate cells via switches during and devices an input phase. Note that since switches and are cut off, competition nodes are not interactive in this phase; they all appear as a purely capacitive load to the fuzzifier modules that generate the inputs. In the following selection phase, all and are turned on to initiate interaction among the competition nodes. A stable state is eventually reached in which the cell that has initially received the lowest input survives with a grounded competition node. All other cells raise their node voltages above . As can be seen from Fig. 5, switches are controlled by competition nodes. Once competition-node voltages have
reached a stable state with only one node having 0 V, only the controlled by that node remains connecting. Obviously, it connects the lowest input voltage among the set of inputs. This voltage is transferred to the output as switches turn on in the final output phase. The output voltage is, therefore, described by
As evidenced by the SPICE transient waveforms shown in Fig. 6(a) and (b) for two extreme input-voltage vectors, the inference module is functional for the entire rail-to-rail input range, hence, fully compatible with the fuzzifier output range. V. THE DEFUZZIFIER MODULE According to (1), defuzzification involves simple addition, weighted addition, and division operations. Each of these is performed by a dedicated unit, as depicted by the block diagram in Fig. 7. The circuit schematic of both types of adders is given in Fig. 8. It is a multiple-input derivative of the sample-andhold architecture shown in Fig. 4. Note that the inputs , arriving from inference modules are received in a reset phase. Output in the following evaluation phase is described by output
(5)
If the capacitors on all input columns are identical, i.e., , , the circuit implements simple addition, i.e., . In order to prevent the adder from saturation, however, this sum should never exceed . An obvious way to comply with this requirement is to select . This would ensure nonsaturation even when all inputs to the adder are at . In a properly designed rule base, however, such an extreme input vector is unlikely to occur because it would imply a controller input condition that fits all rules with 100% truth value. Usually, the maximum possible value of the sum is a fraction of , i.e., , where factor is considerably less than unity. Assuming that has been determined by analyzing the control surface of the controller, it is more reasonable to implement the capacitance ratio in accordance with because this not only results in a
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smaller size for , but also yields an amplified adder output as described by (6) Provided that the weighted addition is also amplified by the same factor , the quotient of the final division operation will not change. Only the precision of division will improve as a result of this amplification. A weighted adder is implemented by sizing input capacitors in accordance with . Output voltage is obtained from (5) as (7) are not greater than unity, this output Since singleton values voltage cannot exceed the adder output voltage given by (6). This also ensures that the weighting adder cannot saturate. A schematic of the divider unit is given in Fig. 9. It comprises a stack of comparators, whose outputs are fed into an output adder, which generates the crisp system output . The adder configuration is exactly like the one shown in Fig. 8. Its input capacitors are sized in accordance with , , which yields from (5) (8) and Each comparator is built with two capacitors and a cascade of two ordinary CMOS inverters, the first of which is resettable. In a reset phase, all these first inverter stages in the entire stack are reset to the logic threshold . In the mean time, bottom plates of all receive the adder signal , which is described by (6). In this phase, the bottom plates of are tied to ground. Note that reset is removed slightly before the switches controlling capacitor bottom plates are turned off. This helps avoid an offset that might otherwise result from charge injection onto the capacitor bottom-plate columns. In the following phase, the weighted adder signal of (7) is imposed on all while all are grounded. The resulting voltage perturbation at the input of an inverter cascade is positive if ; otherwise, a negative perturbation occurs. Assuming that the inverter cascade has a sufficiently high gain, then output from the cascade is described by if
(9)
if
(10)
where, the comparator threshold
is defined by (11)
By selecting capacitance ratios in accordance with (12)
Fig. 9. The divider configuration.
we create equally spaced thresholds in the range zero to one. If exceeds a total of thresholds, then precisely out of comparators transfer a to output adder and, according to (8), the adder responds by generating a system output of (13) where is a quantized representation of . It is obvious that the defuzzifier module computes (1) and presents the outcome as a quantized system-output voltage in full rail-to-rail range with a maximum quantization error . VI. IMPLEMENTATION
AND
TEST RESULTS
The fuzzy controller architecture described in previous sections has been implemented with Austria Mikro Systeme 1.2- m double-poly, double-metal CMOS technology. The test chip, whose photomicrograph is shown in Fig. 10, contains a fully integrated fuzzy controller and also various stand-alone processors for module characterization. Fig. 11 shows the measured transfer characteristics of four stand-alone fuzzifier modules which generate all three fuzzy membership functions of one particular input variable. These traces were obtained by ramping input voltage between 0 and 5 V and sampling it at a rate of 80 k samples per second (corresponding to a master clock frequency of 480 kHz). Targeted corner voltages and are 0.625 and 1.875 V for Fig. 11(a), 1.250 and 1.875 V for Fig. 11(b),
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Fig. 10.
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Photomicrograph of the test chip.
3.125 and 3.750 V for Fig. 11(c), and 2.500 and 4.375 V for Fig. 11(d). Experimental results closely agree with these values and also indicate a very good linearity in almost full rail-to-rail output range.
The minimum-selection ability of a seven-input stand-alone inference module is shown in Fig. 12. The uppermost trace in all three photographs depicts the output voltage. Other traces belong to the three competing input voltages. Four of the
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Fig. 11.
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(b)
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Measured transfer characteristics of four different fuzzifier modules.
seven inputs were tied to 5 V, while the remaining three were set initially to 0, 0.4, and 0.8 V for the case of Fig. 12(a). These three inputs were then sequentially switched to 5 V beginning with the smallest, so that each became a minimum in succession. Initial input voltages were set to 2.1, 2.5, and 2.9 V for the case of Fig. 12(b) and to 3.8, 4.2, and 4.6 V for that of Fig. 12(c). Output traces clearly verify the minimum selection ability of the inference module in the entire rail-to-rail range. A stand-alone divider response is depicted in Fig. 13. The dividend is kept constant at 0.45 V while the divisor is ramped from 0 to 5 V. The output indeed follows the expected hyperbolic dependence on the divisor. As observed on the output trace for small values of the quotient, the divider partially smooths out quantization steps. This is due to the fact that the transfer characteristic of the comparators is somewhat graded due to limited gain, which makes it possible for one or two of the comparators to be only partially saturated. These nonsaturated outputs add analog terms to the final summing operation, which leads to a system-output voltage in between two neighboring quanta. This ability to interpolate is useful because it reduces quantization error. Due to a miscalculation of capacitance ratios, however, all threshold voltages in the entire comparator stack were realized with a 125-mV offset error as a result of which, not only the maximum quantization
error became 250 mV instead of 125 mV, but also the maximum output voltage was limited to 4.75 V because the comparator of the highest index could not be activated at all. The integrated controller implements a proprietary vacuum cleaner expert system developed for Ar¸celik A. S. ¸ It has four input variables which are transformed into a total of three trapezoid and eight ramp-membership functions. The rule base comprises 16 rules with a total of 64 antecedent terms. A total of seven singleton classes are contained in two . The output variables. Both outputs are quantized to adder and weighted adder blocks of the defuzzifier module . No were designed according to a scaling factor adder saturation effect was observable over the entire control surface. Timing is arranged by a data-path controller to have six distinct epochs of equal duration in one inference cycle, as tabulated in Table I. In a control application where pipelining th is permissible, processing can be pipelined by sampling input in fifth epoch instead of seventh, as shown in Table II. This would increase the rate of inference per second by a factor of 3/2. The integrated controller, complete with the data-path controller block, contains 2004 MOSFET’s and 263 poly-to-poly capacitors, and occupies 1.76-mm silicon. An exhaustive functional testing was performed at room temperature by
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TABLE I DATA-PATH CONTROL WITHOUT PIPELINING
TABLE II DATA-PATH CONTROL WITH PIPELINING
scanning the entire four-dimensional input space in 250-mV increments at a rate of 85 k samples per second. Difference between the measured and targeted values of the output voltage remained between 150–400 mV for the entire input space. An experimentally obtained control-surface graph is shown in and represent two of the four inputs variables Fig. 14(a). is an output variable, also measured in volts. in volts. Targeted control surface is depicted in Fig. 14(b). Difference , which we call error surface, between the two surfaces is shown in Fig. 14(c). Considering the number of subcircuits contained and the complexity of interconnectivity involved, it is very difficult to develop an accurate error model for the entirety of the integrated controller data path although possible error sources and their effect on circuit performance are well-documented individually for: 1) OPI-based closed-loop amplifiers such as the sample-and-hold, ramp amplifiers, adders, and weighted adders [17]; 2) extremum selectors such as the inference engine [18]; and 3) SC comparators, such as those used in the divider [19], [20]. The error surface depicted in Fig. 14(c) is indicative of two dominant systematic error sources. One is the quantization error, which, as mentioned previously, is negative due to an error made in capacitance ratio calculation. Theoretically the maximum magnitude of this error is 250 mV. In practice, the magnitude is suppressed by the graded transfer characteristic of divider comparators (as also described previously). This error is present in the background of the entire error surface and becomes dominant over the plateau and , where the second observed for large values of systematic error, which is to be explained next, is negligible.
The second systematic error is responsible for the positive peaks observed on the error surface. This error originates from fuzzifier ramp-amplifiers. Although these amplifiers exhibit very good linearity in a very large segment of the rail-torail output range, the near vicinity of the vertices of their transfer characteristic where the gain segment meets rail levels is inevitably graded. If such an amplifier is biased at or very near the ground-rail vertex, its output voltage exhibits a positive error due to this grading. The error is maximized when the amplifier is biased precisely at the vertex where theoretically the output voltage is expected to be 0 V. For a moderate 4 : 1 grade-ramp amplifier this maximum is about 50 mV. The obvious implication is that an inference module receiving the output of such an amplifier forward to the defuzzifier this error instead of 0 V provided that no smaller voltage is available at any of its other inputs. Any such error reaching the defuzzifier module is treated by the adder and weighted-adder units as a valid truth value as a result of which the output voltages of both of these units exceed the and by some and , expected values respectively. Considering the fact that the weighted adder , output is quantized by the divider into steps of size causes more than a weighted adder output error comparators to be activated if . As a result, the controller output exhibits a positive error of voltage between and where is the integer value of . This error, being inversely proportional to , , which is expected to be effective for small values of is indeed verified by the experimental error surface given in V along Fig. 14(c). Consider, for example, the line
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Fig. 13. Measured response of the divider. Dividend is constant at 0.45 V. Divisor is ramped from 0 to 5 V.
the first of these intervals, 60 mV for the second, and 90 mV for the third. These figures imply an expected positive output error in the ranges 0–250, 250–500, and 500–750 mV, respectively, which is in close agreement with the error observed. In between these three intervals, increases to 1.563 V and reduces the positive error by 50% on the average. High-temperature performance of the controller was tested by reextracting the control surface at 70 C. The maximum absolute deviation in the output voltage with respect to room temperature operation was found to be less than 12.5 mV over the entire control surface. VII. CONCLUSIONS
(b)
This work has explored sampled analog-circuit techniques in application-specific integration of fuzzy controllers. A set of seven subcircuits comprising a sample-and-hold amplifier, positive and negative ramp amplifiers, an inference cell, adder and weighted adder amplifiers, and a divider unit forms a complete library for implementing any fuzzy controller expert system with piecewise linear input membership functions, conjunctive rules, and singleton output classes. The chip size of a fully integrated controller including a data-path controller (but excluding the pads) can be estimated in mm for a typical 1.2- m CMOS technology from Size
(c) Fig. 12. The measured performance of a seven-input inference module. The uppermost trace in each photograph belongs to the output. Four of the inputs in each case are tied to 5 V. The remaining three, which are visible as the lower traces in each photograph, are switched to 5 V from (a) 0, 0.4 V, 0.8 V; (b) 2.1 V, 2.5 V, 2.9 V; and (c) 3.8 V, 4.2 V, 4.6 V.
which the positive error is most pronounced. In three distinct intervals— V V, V V, V V— attains a minimum of 0.781 and V. , as estimated from the number of ramp amplifiers biased at a ground-rail vertex, is approximately 20 mV for
where is the number of outputs, is the number of input classes, and is the number of all antecedent terms in the rule base. The fuzzy controller we built with these units for , , and measures approximately 2 mm . The two programmable fuzzy controller chips mentioned in Section I are characterized with ( , , ) [13], and ( , , ) [14]. If these chips were implemented with the modules presented in this work, the corresponding chip size would be 4.5 and 8 mm , respectively. The fact that each of these two chips actually measures about 70 mm clearly shows the magnitude of compaction achievable with the ASIC approach. As verified by testing on individual processor blocks and on a fully integrated fuzzy controller, all cells exhibit very
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(c) Fig. 14. Partial control surface of the integrated controller. (a) Measured control surface. (b) Targeted control surface. (c) Error surface defined as the difference between the measured and targeted control surfaces.
good linearity over the entire rail-to-rail range. This leads to an accurate representation of the expert system. Furthermore, the chip operates with a single 5-V supply, accepts fully analog voltage inputs, and generates quantized analog voltage outputs. These interfaces operate over the same rail-to-rail range as internal nodes. The measured maximum processing speed is limited to 85 k samples per second. This limitation is imposed by the unbuffered outputs of the present design. REFERENCES [1] A. Costa, A. De Gloria, P. Faraboschi, A. Pagni, and G. Rizzotto, “Hardware solutions for fuzzy control,” Proc. IEEE, vol. 83, no. 3, pp. 422–434, Mar. 1995. [2] T. Yamakawa and T. Miki, “The current mode fuzzy logic integrated circuits fabricated by the standard CMOS process,” IEEE Trans. Comput., vol. C-35, pp. 161–167, Feb. 1986. [3] M. Sasaki, T. Inoue, Y. Shirai, and F. Ueno, “Fuzzy multiple-input maximum and minimum circuits in current mode and their analysis using bounded-difference equations,” IEEE Trans. Comput., vol. 39, pp. 768–774, June 1990. [4] J.-J. Chen, C.-C. Chen, and H.-W. Tsao, “Tunable membership function circuit for fuzzy control systems using CMOS technology,” Electron. Lett., vol. 28, no. 22, pp. 2101–2103, 1992.
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[15] L. Lemaitre, M. J. Patyra, and D. Mlynek, “Analysis and design of CMOS fuzzy logic controller in current mode,” IEEE J. Solid-State Circuits, vol. 29, pp. 317–322, Mar. 1994. [16] F. Krummenacher, “Micropower switched capacitor biquadratic cell,” IEEE J. Solid-State Circuits, vol. SSC-17, pp. 507–512, June 1982. [17] B. Pamir, F. D¨ulger, and Z. S. G¨unay, “Low-voltage rail-to-rail amplification with CMOS operational inverter,” in Proc. 12th Eur. Conf. Circuit Theory Design, Istanbul, Turkey, Aug. 1995, pp. 9–12. [18] U. Cilingiro˘ ¸ glu, “A charge-based neural hamming classifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 59–67, Jan. 1993. [19] B. M. Onat, J. A. McNeill, and U. Cilingiro˘ ¸ glu, “A neural euclidean classifier utilizing a purely capacitive synaptic matrix,” in Proc. 12th Eur. Conf. Circuit Theory .Design, Istanbul, Turkey, Aug. 1995, pp. 199–202. ¨ [20] H. Ozdemir, A. Kepkep, B. Pamir, Y. Leblebicix, and U. Cilingiro˘ ¸ glu, “A capacitive threshold-logic gate,” IEEE J. Solid-State Circuits, vol. 31, pp. 1141–1150, Aug. 1996.
U˘gur Cilingiro˘ ¸ glu (M’86) received the M.S. degree in electrical engineering from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1973, and the Ph.D. degree in microelectronics from Southampton University, Southampton, U.K., in 1978. From 1973 to 1984 and from 1986 to 1988, he was an Assistant Professor and Associate Professor, respectively, at ˙Istanbul Technical University, Turkey, where he has been working as a Professor since 1991. He was on the faculty of the Electrical Engineering Department of Texas A&M University, College Station, TX, from 1984 to 1986 and again from 1988 to 1991. He is presently an Adjunct Professorship in the same department. Prior to 1984, he worked as a Consultant with the Turkish Scientific and Technological Research Council, contributing to the establishment of a semiconductor technology research and development facility at Kocaeli, Turkey. Between 1986 and 1988, he was a Consultant to Teleta¸s A.S., ¸ organizing industrial training courses on CMOS technology and ASIC design. He spent the summer of 1990 at HewlettPackard Manufacturing Test Division, Loveland, CO, where he conceived and developed the capacitive pin-open board-testing technique known today as HP TestJet Technology. Currently, he is the Academic Coordinator at ETA ASIC Design Center, ˙Istanbul, Turkey. He holds three U.S. patents and is the author of Systematic Analysis of Bipolar and MOS Transistors (Norwood, MA: Artech House, 1993). His research activity in the past has involved all aspects of microelectronic circuits, devices, and technology. Most recently, he has been active in the area of engineered intelligence on silicon. Dr. Cilingiro˘ ¸ glu received a CENTO Scholarship in 1973, a Fulbright Research Fellowship in 1984, and an Eta Kappa Nu Outstanding Professor award in 1991.
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Banu Pamir (S’92) received the B.S. and M.S. degrees in electronics from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1988 and 1991, respectively. She is currently working toward the Ph.D. degree at the same university. Since 1988, she has been working as a Research Assistant at the Electronics and Communication Engineering Department of ˙Istanbul Technical University. From 1992 to 1994 Ms. Pamir was also with ETA ASIC Design Center, ˙Istanbul, developing fullcustom mixed-mode industrial ASIC’s. Her research interest is in the area of microelectronic implementation of emerging logic techniques.
Z. Sezgin Gunay ¨ received the B.S. degree in electronics from ˙IP stanbul Technical University, ˙Istanbul, Turkey, in 1993. In 1994, Mr. G¨unay worked for ETA ASIC Design Center, ˙Istanbul as a Design Engineer, developing full-custom mixed-mode industrial ASIC’s. He was with Texas Instruments, Dallas, TX, in the summer of 1996 as a Design Engineer developing data converters for low-voltage applications. Since 1994 he has been a Graduate Student and Research Assistant at the Electrical Engineering Department of Texas A&M University, College Station, TX. His research activities are in the area of analog and mixed-mode circuit design and data converters.
Fikret Dulger received the B.S. (in electronics) and ¨ M.S. degrees from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1993 and 1996, respectively. He worked as a Research Assistant at the Electronics and Communication Engineering Department of ˙Istanbul Technical University from 1993 to 1996. In 1994 he worked for ETA ASIC Design Center, ˙Istanbul, as a Design Engineer developing full-custom mixed-mode industrial ASIC’s. Currently, he is a Graduate Student and Research Assistant in the Electrical Engineering Department of Texas A&M University, College Station, TX. His research interests are in the area of analog electronics.
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Sampled-Analog Implementation of Application-Specific Fuzzy Controllers U˘gur Cilingiro˘ ¸ glu, Member, IEEE, Banu Pamir, Student Member, IEEE, Z. Sezgin G¨unay, and Fikret D¨ulger
Abstract— Sampled-analog circuit techniques are exploited in an application-specific integrated fuzzy controller design. A circuit library comprising a sample-and-hold amplifier, positive and negative ramp amplifiers, an inference cell, adder, and weighted adder amplifiers, and a divider unit was developed for this purpose. Any expert system of piecewise linear input membership functions, conjunctive rules and singleton output classes can be implemented with this library. The library was implemented in a 1.2 m double-metal double-poly CMOS technology. Test results indicate excellent linearity and accuracy in full 5-V railto-rail operation in all units. A controller of four inputs, 16 rules, and two outputs fabricated with these library units occupies 1.76 mm2 silicon. Test results indicate full functionality. The measured speed, 85 k samples per second, is limited by the unbuffered outputs. Sampling rate can be increased by 50% in those applications where pipelining is permissible. Index Terms—Controller, sampled analog.
I. INTRODUCTION
F
UZZY logic has been developed over the past three decades into a widely applied technique in classification and control engineering. This logic can be implemented in one of the following forms: 1) software simulation, which is highly cost effective if volume production is not demanded, and neither portability nor processing speed is critical; 2) microprocessor or microcontroller implementation, which is most suitable for low-volume production of slow but portable systems; 3) using a field-programmable or reconfigurable fuzzy processor chip, which offers high speed to portable systems in low-volume production; 4) using an application-specific (ASIC) fuzzy processor chip, which offers high speed in a cost-effective way for portable systems in high-volume production [1]. Quite obviously, the last two of these implementation styles require fuzzy-specific chip design. Indeed, numerous simulated or partially integrated architectures have been proposed in the past decade to fulfill this need [2]–[12]. Publications on fully integrated fuzzy-system chips, however, are relatively rare. One of these involves a digital fuzzy-controller [13].
Manuscript received December 5, 1995; revised December 12, 1996. This work was supported in part by the Technology Development Foundation of Turkey and by Ar¸celik A. S.. ¸ The authors are with the ETA Design Center and Department of Electronics ¨ Ayaza˘ga Kamp¨us¨u, and Communication, ˙Istanbul Technical University, ˙ITU Maslak-80626, ˙Istanbul, Turkey. Publisher Item Identifier S 1063-6706(97)04841-8.
This chip can be configured for the modes 4-in/2-out/51-rules and 2-in/1-out/102-rules; it features full programmability of membership functions and rules and offers a 6-b input/output (I/O) resolution and a 4-b internal resolution. Device count is above 680 k and chip size in 1.1- m CMOS is 70.14 mm . Another fully integrated programmable fuzzy controller chip, exploiting sampled analog-circuit techniques for internal processing, is described in [14]. It can be configured for up to eight inputs and four outputs, each transformable into seven classes at most. Rule capacity is 32, precision is 6 b, and chip size in 0.8- m CMOS is 70 mm . The current-based analog ASIC described in [15] is another example of fully integrated fuzzy controller. This chip is mask programmed to a configuration of 2-in/1-out/9-rules with three classes per input or output. Although the exemplar configuration is less sophisticated than those described above, the architecture still reflects the silicon area saved by omitting field programmability: The controller contains only 500 devices and fits into 0.4-mm silicon in 1.2- m CMOS. The chip we describe in this paper is another example of the ASIC approach to fully integrating a fuzzy controller on silicon. However, our approach relies on sampled analogcircuit techniques, which not only naturally provide for analogvoltage representation of I/O variables and, thus, reduce interface complexity, but also lead to a more accurate representation of the algorithm. The accuracy stems from the fact that internal parameters are determined solely by capacitance ratios instead of MOSFET current ratios. The dedicated configuration of this chip is 4-in/2-out/16-rules. It contains a total of 11 input and seven output classes and measures 1.76 mm in 1.2- m CMOS. In Section II, we present architectural features of the controller. The fuzzifier, inference engine, and defuzzifier modules are discussed in Sections III–V, respectively. Implementation and test results are the subject of Section VI. Finally, conclusions are presented in Section VII. II. ARCHITECTURAL FEATURES In a typical fuzzy-controller algorithm, data are processed in three successive computational steps. Namely, fuzzification, inference, and defuzzification. In each step, however, multiple channels of data are treated in parallel. An architectural schematic of a fuzzy controller hardware is shown in Fig. 1. It comprises blocks of three main processor modules marked fuzzifier module, inference module, and defuzzifier module, and two routing matrices interconnecting these three successive
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Fig. 1. Architecture of a fuzzy controller.
blocks. In a sampled analog implementation, inclusion of a data-path controller block is also necessary for properly processing and shifting data from input to output. Each fuzzifier module transforms a sampled and held input variable into a degree of membership in one fuzzy input-class. Therefore, one such module is required for each fuzzy input class. In the present implementation, membership functions are assumed to be piecewise linear such as trapezoid, triangle, or ramp. Each inference module calculates the truth value of one fuzzy rule. A fuzzy rule is assumed to be a conjunctive proposition of antecedent terms. Each such term is represented by a degree of membership generated by some fuzzifier module. The truth value is calculated from . Each defuzzifier module generates one crisp output (control) variable from truth values transmitted from the inference block. We adopt the method of weighted-average of singletons for defuzzification, which prescribes
(1)
where, is the singleton value of the output class associated with rule and is the truth value of the same rule. All of the fuzzy variables , , , , and parameter can be represented, without loss of generality, with real numbers in between zero and one. The corresponding electrical variables in the present implementation are voltages defined generally as where is a fuzzy variable and is the supply voltage. III. THE FUZZIFIER MODULE As pointed out in Section II, a fuzzifier module is expected to implement a piecewise linear membership function. Generally, the following three different functions are required: 1) positive ramp; 2) negative ramp; and 3) trapezoid or triangle. As shown in Fig. 2, however, a trapezoidal or triangular membership function can be generated with a pair of
Fig. 2. Generating a trapezoidal or triangular membership function with a pair of positive and negative ramp function.
positive and negative ramp functions follows:
and
as
Since fuzzifier outputs are fed into inference modules, which are supposed to perform a min operation anyway, an can be implemented by feeding a pair of and into the same inference module. Therefore, all membership functions can be realized solely with ramp functions, which are implemented in the present design with the switched-capacitor (SC) voltage amplifier configuration, shown in Fig. 3(a). This amplifier is a derivative of the stray insensitive SC integrator proposed in [16] and is built around a nondifferential resettable core amplifier that has a large negative open-loop gain around a self-reference level between the two rail levels, as depicted in Fig. 3(b). The core amplifier is a PSRR-enhanced version of the operational inverter (OPI), reported in [17]. It mainly consists of three CMOS inverter stages, the first of which is power supplied via source followers to enhance power supply rejection ratio (PSRR) and the third is equipped with a very simple compensation network. In a 1.2- m mainstream technology it merely occupies 46 m 56 m silicon. The amplifier configuration of Fig. 3(a) operates in a twophase nonoverlapping clock scheme. Input and output nodes of OPI are reset to by a feedback switch during the reset phase. In the positive-ramp amplifier configuration, the lower plate of receives input during this phase, while those of and are tied to ground. In the following evaluation phase, the resetting feedback of OPI is removed and, thus, the input node of OPI enters a high-impedance state. However, a closed-loop operation is established via the capacitor while the bottom plate of is tied to ground and that of is
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(a)
(b)
(c)
Fig. 4. The sample-and-hold unit.
(d)
Fig. 3. (a) The amplifier configuration implementing ramp functions V(PR) and V(NR) for fuzzification. (b) The transfer characteristic of the core amplifier OPI. (c) Positive-ramp output versus input voltage. (d) Negative-ramp output versus input voltage.
connected to by
. Output in the evaluation phase is described
for
(2)
where (3) and (4) and , OPI remains Within the input range limited by nonsaturated. Any input voltage outside this range forces . The characteristic OPI output to saturate at 0 V or described by (2) and depicted in Fig. 3(c) is typical of a positive-ramp function. Note that the grade and offset of the and ramp are determined solely by the capacitive ratios , whereas the two saturation levels are determined by rail voltages. The amplifier configuration of Fig. 3(a) is transformed into negative-ramp amplifier by interfacing, as indicated in parentheses. In this case, the output in the evaluation phase is described by for
Fig. 5. An
m-input
inference module.
where and are still defined by (3) and (4), respectively. The resulting versus characteristic is depicted in Fig. 3(c). Again, the gain and offset are determined by the and . capacitive ratios The negative-ramp amplifier is not a sampling amplifier because it generates a valid output in the same evaluation
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(a)
(b) Fig. 6. HSPICE transient waveforms of a seven-input inference module. Output waveform is shown in solid line. Input voltages differ by 20 mV in the range. (a) 0–0.12 V. (b) 4.88–5.00 V.
phase as the input is received. For this reason, the controller prior to input variables ( ) are sampled and held as fuzzification. The sample-and-hold units used for this purpose are constructed as a unity-gain zero-offset version of the
positive-ramp amplifier, as shown in Fig. 4. These units also have a rail-to-rail functionality. In summary, a fuzzifier module contains a single noninverting or inverting amplifier for a positive or negative ramp
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Fig. 8. Adder and weighted adder circuit schematic. Fig. 7. Block diagram of the defuzzifier module.
function, but a pair of noninverting and inverting amplifiers for a trapezoidal or triangular function. IV. THE INFERENCE MODULE Fig. 5 shows the circuit diagram of an -input inference module. It is a derivative of the maxnet configuration described in [18]. The circuit comprises identical cells, each assigned to one input. A cell is built around a competition node, e.g., in Cell-1. This node has a pull-down path via NMOS and a pull-up path via a parallel network of PMOS devices placed in series with a PMOS . The gate of each device in the parallel network is controlled by the competition node of another cell. A total of such control paths establish mutually inhibitory connections among all cells so that when all and are on, the module converges to a stable state in which one and only one competition node remains at 0 V and the others are pulled up to a voltage above , where is the absolute value of the PMOS device-threshold voltage. This is guaranteed by ratioing and in such a way that even if a single PMOS device in a parallel pull-up net receives 0 V at its gate, the competitionnode voltage of that cell exceeds . In a stable state, therefore, the parallel pull-up network of the cell of 0-V node voltage is completely cut off, whereas all other cells’ nodes are pulled up by one device in each parallel pull-up net. Having described the stable state of the interconnected competition nodes, we now explain the sequence of operations in the entire inference module and illustrate it with the SPICE transient analysis results, shown in Fig. 6. All inputs , are transferred onto the competition nodes of separate cells via switches during and devices an input phase. Note that since switches and are cut off, competition nodes are not interactive in this phase; they all appear as a purely capacitive load to the fuzzifier modules that generate the inputs. In the following selection phase, all and are turned on to initiate interaction among the competition nodes. A stable state is eventually reached in which the cell that has initially received the lowest input survives with a grounded competition node. All other cells raise their node voltages above . As can be seen from Fig. 5, switches are controlled by competition nodes. Once competition-node voltages have
reached a stable state with only one node having 0 V, only the controlled by that node remains connecting. Obviously, it connects the lowest input voltage among the set of inputs. This voltage is transferred to the output as switches turn on in the final output phase. The output voltage is, therefore, described by
As evidenced by the SPICE transient waveforms shown in Fig. 6(a) and (b) for two extreme input-voltage vectors, the inference module is functional for the entire rail-to-rail input range, hence, fully compatible with the fuzzifier output range. V. THE DEFUZZIFIER MODULE According to (1), defuzzification involves simple addition, weighted addition, and division operations. Each of these is performed by a dedicated unit, as depicted by the block diagram in Fig. 7. The circuit schematic of both types of adders is given in Fig. 8. It is a multiple-input derivative of the sample-andhold architecture shown in Fig. 4. Note that the inputs , arriving from inference modules are received in a reset phase. Output in the following evaluation phase is described by output
(5)
If the capacitors on all input columns are identical, i.e., , , the circuit implements simple addition, i.e., . In order to prevent the adder from saturation, however, this sum should never exceed . An obvious way to comply with this requirement is to select . This would ensure nonsaturation even when all inputs to the adder are at . In a properly designed rule base, however, such an extreme input vector is unlikely to occur because it would imply a controller input condition that fits all rules with 100% truth value. Usually, the maximum possible value of the sum is a fraction of , i.e., , where factor is considerably less than unity. Assuming that has been determined by analyzing the control surface of the controller, it is more reasonable to implement the capacitance ratio in accordance with because this not only results in a
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smaller size for , but also yields an amplified adder output as described by (6) Provided that the weighted addition is also amplified by the same factor , the quotient of the final division operation will not change. Only the precision of division will improve as a result of this amplification. A weighted adder is implemented by sizing input capacitors in accordance with . Output voltage is obtained from (5) as (7) are not greater than unity, this output Since singleton values voltage cannot exceed the adder output voltage given by (6). This also ensures that the weighting adder cannot saturate. A schematic of the divider unit is given in Fig. 9. It comprises a stack of comparators, whose outputs are fed into an output adder, which generates the crisp system output . The adder configuration is exactly like the one shown in Fig. 8. Its input capacitors are sized in accordance with , , which yields from (5) (8) and Each comparator is built with two capacitors and a cascade of two ordinary CMOS inverters, the first of which is resettable. In a reset phase, all these first inverter stages in the entire stack are reset to the logic threshold . In the mean time, bottom plates of all receive the adder signal , which is described by (6). In this phase, the bottom plates of are tied to ground. Note that reset is removed slightly before the switches controlling capacitor bottom plates are turned off. This helps avoid an offset that might otherwise result from charge injection onto the capacitor bottom-plate columns. In the following phase, the weighted adder signal of (7) is imposed on all while all are grounded. The resulting voltage perturbation at the input of an inverter cascade is positive if ; otherwise, a negative perturbation occurs. Assuming that the inverter cascade has a sufficiently high gain, then output from the cascade is described by if
(9)
if
(10)
where, the comparator threshold
is defined by (11)
By selecting capacitance ratios in accordance with (12)
Fig. 9. The divider configuration.
we create equally spaced thresholds in the range zero to one. If exceeds a total of thresholds, then precisely out of comparators transfer a to output adder and, according to (8), the adder responds by generating a system output of (13) where is a quantized representation of . It is obvious that the defuzzifier module computes (1) and presents the outcome as a quantized system-output voltage in full rail-to-rail range with a maximum quantization error . VI. IMPLEMENTATION
AND
TEST RESULTS
The fuzzy controller architecture described in previous sections has been implemented with Austria Mikro Systeme 1.2- m double-poly, double-metal CMOS technology. The test chip, whose photomicrograph is shown in Fig. 10, contains a fully integrated fuzzy controller and also various stand-alone processors for module characterization. Fig. 11 shows the measured transfer characteristics of four stand-alone fuzzifier modules which generate all three fuzzy membership functions of one particular input variable. These traces were obtained by ramping input voltage between 0 and 5 V and sampling it at a rate of 80 k samples per second (corresponding to a master clock frequency of 480 kHz). Targeted corner voltages and are 0.625 and 1.875 V for Fig. 11(a), 1.250 and 1.875 V for Fig. 11(b),
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Photomicrograph of the test chip.
3.125 and 3.750 V for Fig. 11(c), and 2.500 and 4.375 V for Fig. 11(d). Experimental results closely agree with these values and also indicate a very good linearity in almost full rail-to-rail output range.
The minimum-selection ability of a seven-input stand-alone inference module is shown in Fig. 12. The uppermost trace in all three photographs depicts the output voltage. Other traces belong to the three competing input voltages. Four of the
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(b)
(c)
(d)
Measured transfer characteristics of four different fuzzifier modules.
seven inputs were tied to 5 V, while the remaining three were set initially to 0, 0.4, and 0.8 V for the case of Fig. 12(a). These three inputs were then sequentially switched to 5 V beginning with the smallest, so that each became a minimum in succession. Initial input voltages were set to 2.1, 2.5, and 2.9 V for the case of Fig. 12(b) and to 3.8, 4.2, and 4.6 V for that of Fig. 12(c). Output traces clearly verify the minimum selection ability of the inference module in the entire rail-to-rail range. A stand-alone divider response is depicted in Fig. 13. The dividend is kept constant at 0.45 V while the divisor is ramped from 0 to 5 V. The output indeed follows the expected hyperbolic dependence on the divisor. As observed on the output trace for small values of the quotient, the divider partially smooths out quantization steps. This is due to the fact that the transfer characteristic of the comparators is somewhat graded due to limited gain, which makes it possible for one or two of the comparators to be only partially saturated. These nonsaturated outputs add analog terms to the final summing operation, which leads to a system-output voltage in between two neighboring quanta. This ability to interpolate is useful because it reduces quantization error. Due to a miscalculation of capacitance ratios, however, all threshold voltages in the entire comparator stack were realized with a 125-mV offset error as a result of which, not only the maximum quantization
error became 250 mV instead of 125 mV, but also the maximum output voltage was limited to 4.75 V because the comparator of the highest index could not be activated at all. The integrated controller implements a proprietary vacuum cleaner expert system developed for Ar¸celik A. S. ¸ It has four input variables which are transformed into a total of three trapezoid and eight ramp-membership functions. The rule base comprises 16 rules with a total of 64 antecedent terms. A total of seven singleton classes are contained in two . The output variables. Both outputs are quantized to adder and weighted adder blocks of the defuzzifier module . No were designed according to a scaling factor adder saturation effect was observable over the entire control surface. Timing is arranged by a data-path controller to have six distinct epochs of equal duration in one inference cycle, as tabulated in Table I. In a control application where pipelining th is permissible, processing can be pipelined by sampling input in fifth epoch instead of seventh, as shown in Table II. This would increase the rate of inference per second by a factor of 3/2. The integrated controller, complete with the data-path controller block, contains 2004 MOSFET’s and 263 poly-to-poly capacitors, and occupies 1.76-mm silicon. An exhaustive functional testing was performed at room temperature by
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TABLE I DATA-PATH CONTROL WITHOUT PIPELINING
TABLE II DATA-PATH CONTROL WITH PIPELINING
scanning the entire four-dimensional input space in 250-mV increments at a rate of 85 k samples per second. Difference between the measured and targeted values of the output voltage remained between 150–400 mV for the entire input space. An experimentally obtained control-surface graph is shown in and represent two of the four inputs variables Fig. 14(a). is an output variable, also measured in volts. in volts. Targeted control surface is depicted in Fig. 14(b). Difference , which we call error surface, between the two surfaces is shown in Fig. 14(c). Considering the number of subcircuits contained and the complexity of interconnectivity involved, it is very difficult to develop an accurate error model for the entirety of the integrated controller data path although possible error sources and their effect on circuit performance are well-documented individually for: 1) OPI-based closed-loop amplifiers such as the sample-and-hold, ramp amplifiers, adders, and weighted adders [17]; 2) extremum selectors such as the inference engine [18]; and 3) SC comparators, such as those used in the divider [19], [20]. The error surface depicted in Fig. 14(c) is indicative of two dominant systematic error sources. One is the quantization error, which, as mentioned previously, is negative due to an error made in capacitance ratio calculation. Theoretically the maximum magnitude of this error is 250 mV. In practice, the magnitude is suppressed by the graded transfer characteristic of divider comparators (as also described previously). This error is present in the background of the entire error surface and becomes dominant over the plateau and , where the second observed for large values of systematic error, which is to be explained next, is negligible.
The second systematic error is responsible for the positive peaks observed on the error surface. This error originates from fuzzifier ramp-amplifiers. Although these amplifiers exhibit very good linearity in a very large segment of the rail-torail output range, the near vicinity of the vertices of their transfer characteristic where the gain segment meets rail levels is inevitably graded. If such an amplifier is biased at or very near the ground-rail vertex, its output voltage exhibits a positive error due to this grading. The error is maximized when the amplifier is biased precisely at the vertex where theoretically the output voltage is expected to be 0 V. For a moderate 4 : 1 grade-ramp amplifier this maximum is about 50 mV. The obvious implication is that an inference module receiving the output of such an amplifier forward to the defuzzifier this error instead of 0 V provided that no smaller voltage is available at any of its other inputs. Any such error reaching the defuzzifier module is treated by the adder and weighted-adder units as a valid truth value as a result of which the output voltages of both of these units exceed the and by some and , expected values respectively. Considering the fact that the weighted adder , output is quantized by the divider into steps of size causes more than a weighted adder output error comparators to be activated if . As a result, the controller output exhibits a positive error of voltage between and where is the integer value of . This error, being inversely proportional to , , which is expected to be effective for small values of is indeed verified by the experimental error surface given in V along Fig. 14(c). Consider, for example, the line
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(a)
Fig. 13. Measured response of the divider. Dividend is constant at 0.45 V. Divisor is ramped from 0 to 5 V.
the first of these intervals, 60 mV for the second, and 90 mV for the third. These figures imply an expected positive output error in the ranges 0–250, 250–500, and 500–750 mV, respectively, which is in close agreement with the error observed. In between these three intervals, increases to 1.563 V and reduces the positive error by 50% on the average. High-temperature performance of the controller was tested by reextracting the control surface at 70 C. The maximum absolute deviation in the output voltage with respect to room temperature operation was found to be less than 12.5 mV over the entire control surface. VII. CONCLUSIONS
(b)
This work has explored sampled analog-circuit techniques in application-specific integration of fuzzy controllers. A set of seven subcircuits comprising a sample-and-hold amplifier, positive and negative ramp amplifiers, an inference cell, adder and weighted adder amplifiers, and a divider unit forms a complete library for implementing any fuzzy controller expert system with piecewise linear input membership functions, conjunctive rules, and singleton output classes. The chip size of a fully integrated controller including a data-path controller (but excluding the pads) can be estimated in mm for a typical 1.2- m CMOS technology from Size
(c) Fig. 12. The measured performance of a seven-input inference module. The uppermost trace in each photograph belongs to the output. Four of the inputs in each case are tied to 5 V. The remaining three, which are visible as the lower traces in each photograph, are switched to 5 V from (a) 0, 0.4 V, 0.8 V; (b) 2.1 V, 2.5 V, 2.9 V; and (c) 3.8 V, 4.2 V, 4.6 V.
which the positive error is most pronounced. In three distinct intervals— V V, V V, V V— attains a minimum of 0.781 and V. , as estimated from the number of ramp amplifiers biased at a ground-rail vertex, is approximately 20 mV for
where is the number of outputs, is the number of input classes, and is the number of all antecedent terms in the rule base. The fuzzy controller we built with these units for , , and measures approximately 2 mm . The two programmable fuzzy controller chips mentioned in Section I are characterized with ( , , ) [13], and ( , , ) [14]. If these chips were implemented with the modules presented in this work, the corresponding chip size would be 4.5 and 8 mm , respectively. The fact that each of these two chips actually measures about 70 mm clearly shows the magnitude of compaction achievable with the ASIC approach. As verified by testing on individual processor blocks and on a fully integrated fuzzy controller, all cells exhibit very
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(b)
(c) Fig. 14. Partial control surface of the integrated controller. (a) Measured control surface. (b) Targeted control surface. (c) Error surface defined as the difference between the measured and targeted control surfaces.
good linearity over the entire rail-to-rail range. This leads to an accurate representation of the expert system. Furthermore, the chip operates with a single 5-V supply, accepts fully analog voltage inputs, and generates quantized analog voltage outputs. These interfaces operate over the same rail-to-rail range as internal nodes. The measured maximum processing speed is limited to 85 k samples per second. This limitation is imposed by the unbuffered outputs of the present design. REFERENCES [1] A. Costa, A. De Gloria, P. Faraboschi, A. Pagni, and G. Rizzotto, “Hardware solutions for fuzzy control,” Proc. IEEE, vol. 83, no. 3, pp. 422–434, Mar. 1995. [2] T. Yamakawa and T. Miki, “The current mode fuzzy logic integrated circuits fabricated by the standard CMOS process,” IEEE Trans. Comput., vol. C-35, pp. 161–167, Feb. 1986. [3] M. Sasaki, T. Inoue, Y. Shirai, and F. Ueno, “Fuzzy multiple-input maximum and minimum circuits in current mode and their analysis using bounded-difference equations,” IEEE Trans. Comput., vol. 39, pp. 768–774, June 1990. [4] J.-J. Chen, C.-C. Chen, and H.-W. Tsao, “Tunable membership function circuit for fuzzy control systems using CMOS technology,” Electron. Lett., vol. 28, no. 22, pp. 2101–2103, 1992.
[5] F. J. Pelayo, J. Ortega, and A. Prieto, “Current-mode analogue defuzzifier,” Electron. Lett., vol. 29, no. 9, pp. 743–744, 1993. [6] T. Yamakawa, “A fuzzy inference engine in nonlinear analog mode and its application to a fuzzy logic control,” IEEE Trans. Neural Networks, vol. 4, pp. 496–522, May 1993. [7] T. Kettner, C. Heite, and K. Schumacher, “Analog CMOS realization of fuzzy logic membership functions,” IEEE J. Solid-State Circuits, vol. 28, pp. 857–861, July 1993. [8] S. S. Chen, C. S. Chiang, K. W. Su, and J. B. Kuo, “BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers,” Electron. Lett., vol. 29, no. 6, 1993. [9] I. E. Opris and F. Balteanu, “BiCMOS tunable membership function circuits,” Int. J. Electron., vol. 75, no. 4, 1993. [10] K. Tsukano and T. Inoue, “Synthesis of operational transconductance amplifier-based analog fuzzy functional blocks and its application,” IEEE Trans. Fuzzy Syst., vol. 3, pp. 61–68, Feb. 1995. [11] C.-Y. Huang, C.-J. Wang, and B.-D. Liu, “Modular current-mode multiple input minimum circuit for fuzzy logic controllers,” Electron. Lett., vol. 32, no. 12, pp. 1067–1069, 1996. ´ Barriga, “Inte[12] J. L. Huertas, S. S´anchez-Soleno, I. Baturone, and A. grated circuit implementation of fuzzy controllers,” IEEE J. Solid-State Circuits, vol. 31, pp. 1051–1058, July 1996. [13] H. Watanabe, W. Dettloff, and K. Yount, “A VLSI fuzzy logic controller with reconfigurable, cascadable architecture,” IEEE J. Solid-State Circuits, vol. 25, pp. 376–382, Apr. 1990. [14] J. W. Fattaruso, S. S. Mahant-Shetti, and J. B. Barton, “A fuzzy logic inference processor,” IEEE J. Solid-State Circuits, vol. 29, pp. 397–402, Apr. 1994.
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[15] L. Lemaitre, M. J. Patyra, and D. Mlynek, “Analysis and design of CMOS fuzzy logic controller in current mode,” IEEE J. Solid-State Circuits, vol. 29, pp. 317–322, Mar. 1994. [16] F. Krummenacher, “Micropower switched capacitor biquadratic cell,” IEEE J. Solid-State Circuits, vol. SSC-17, pp. 507–512, June 1982. [17] B. Pamir, F. D¨ulger, and Z. S. G¨unay, “Low-voltage rail-to-rail amplification with CMOS operational inverter,” in Proc. 12th Eur. Conf. Circuit Theory Design, Istanbul, Turkey, Aug. 1995, pp. 9–12. [18] U. Cilingiro˘ ¸ glu, “A charge-based neural hamming classifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 59–67, Jan. 1993. [19] B. M. Onat, J. A. McNeill, and U. Cilingiro˘ ¸ glu, “A neural euclidean classifier utilizing a purely capacitive synaptic matrix,” in Proc. 12th Eur. Conf. Circuit Theory .Design, Istanbul, Turkey, Aug. 1995, pp. 199–202. ¨ [20] H. Ozdemir, A. Kepkep, B. Pamir, Y. Leblebicix, and U. Cilingiro˘ ¸ glu, “A capacitive threshold-logic gate,” IEEE J. Solid-State Circuits, vol. 31, pp. 1141–1150, Aug. 1996.
U˘gur Cilingiro˘ ¸ glu (M’86) received the M.S. degree in electrical engineering from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1973, and the Ph.D. degree in microelectronics from Southampton University, Southampton, U.K., in 1978. From 1973 to 1984 and from 1986 to 1988, he was an Assistant Professor and Associate Professor, respectively, at ˙Istanbul Technical University, Turkey, where he has been working as a Professor since 1991. He was on the faculty of the Electrical Engineering Department of Texas A&M University, College Station, TX, from 1984 to 1986 and again from 1988 to 1991. He is presently an Adjunct Professorship in the same department. Prior to 1984, he worked as a Consultant with the Turkish Scientific and Technological Research Council, contributing to the establishment of a semiconductor technology research and development facility at Kocaeli, Turkey. Between 1986 and 1988, he was a Consultant to Teleta¸s A.S., ¸ organizing industrial training courses on CMOS technology and ASIC design. He spent the summer of 1990 at HewlettPackard Manufacturing Test Division, Loveland, CO, where he conceived and developed the capacitive pin-open board-testing technique known today as HP TestJet Technology. Currently, he is the Academic Coordinator at ETA ASIC Design Center, ˙Istanbul, Turkey. He holds three U.S. patents and is the author of Systematic Analysis of Bipolar and MOS Transistors (Norwood, MA: Artech House, 1993). His research activity in the past has involved all aspects of microelectronic circuits, devices, and technology. Most recently, he has been active in the area of engineered intelligence on silicon. Dr. Cilingiro˘ ¸ glu received a CENTO Scholarship in 1973, a Fulbright Research Fellowship in 1984, and an Eta Kappa Nu Outstanding Professor award in 1991.
IEEE TRANSACTIONS ON FUZZY SYSTEMS, VOL. 5, NO. 3, AUGUST 1997
Banu Pamir (S’92) received the B.S. and M.S. degrees in electronics from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1988 and 1991, respectively. She is currently working toward the Ph.D. degree at the same university. Since 1988, she has been working as a Research Assistant at the Electronics and Communication Engineering Department of ˙Istanbul Technical University. From 1992 to 1994 Ms. Pamir was also with ETA ASIC Design Center, ˙Istanbul, developing fullcustom mixed-mode industrial ASIC’s. Her research interest is in the area of microelectronic implementation of emerging logic techniques.
Z. Sezgin Gunay ¨ received the B.S. degree in electronics from ˙IP stanbul Technical University, ˙Istanbul, Turkey, in 1993. In 1994, Mr. G¨unay worked for ETA ASIC Design Center, ˙Istanbul as a Design Engineer, developing full-custom mixed-mode industrial ASIC’s. He was with Texas Instruments, Dallas, TX, in the summer of 1996 as a Design Engineer developing data converters for low-voltage applications. Since 1994 he has been a Graduate Student and Research Assistant at the Electrical Engineering Department of Texas A&M University, College Station, TX. His research activities are in the area of analog and mixed-mode circuit design and data converters.
Fikret Dulger received the B.S. (in electronics) and ¨ M.S. degrees from ˙Istanbul Technical University, ˙Istanbul, Turkey, in 1993 and 1996, respectively. He worked as a Research Assistant at the Electronics and Communication Engineering Department of ˙Istanbul Technical University from 1993 to 1996. In 1994 he worked for ETA ASIC Design Center, ˙Istanbul, as a Design Engineer developing full-custom mixed-mode industrial ASIC’s. Currently, he is a Graduate Student and Research Assistant in the Electrical Engineering Department of Texas A&M University, College Station, TX. His research interests are in the area of analog electronics.
