Single Event Coupling Soft Errors in Nanoscale CMOS Circuits
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Single Event Coupling Soft Errors in Nanoscale CMOS Circuits Selahattin Sayil, Member, IEEE, Sumanth R. Yeddula, Student Member, IEEE, Juyu Wang, Student Member Abstract— Due to scaling effects, circuits become increasingly sensitive to transients caused by single event (SE) particles. Researchers mostly considered SE transients (SETs) as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications additional sources such as SE soft delays, clock jitter, race and SE coupling effects need to be included in analysis. This work focuses on coupling-induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SET effects, and crosstalk contribution to soft error rate has been examined. In addition, SE coupling delay effects have been compared to radiation induced soft delay effect for various technologies. In comparisons, the distributed nature of interconnect has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies. Index Terms— Single Event Crosstalk, Soft Error Reliability, Coupling Noise.
I. INTRODUCTION
T
HE International Technology Roadmap for Semiconductors (2011 Edition) has pointed to signal integrity in chips as a major challenge [1]. Recently, radiationinduced soft errors in commercial nanometer CMOS technologies have become a growing concern. Soft errors in memory have been a very well known problem at terrestrial level. However, due to increasing clock frequencies and shrinking device sizes, it has been predicted that the majority of the observed radiation induced soft failures will be due to transients that will occur in combinational logic (CL) circuits below 65 nm [2]. When an incident charged particle strikes the sensitive area within a circuit such as the depletion region of transistor drains, many electron-hole pairs are created due to ionization mechanism. These free carriers can later drift under the electric field creating a transient voltage pulse. This transient is also known as “Single Event Transient” or SET. An SET may pass through a series of CL gates and reach to storage elements under certain conditions. If it arrives at the storage element during its latching window, incorrect data may be stored resulting in soft error or single event upset (SEU). For advanced technologies, circuit scaling causes reduced supply voltages, transistor drive currents and shrinking node capacitances. All these factors can contribute to increased circuit sensitivity to SETs in CL due to reduced critical charge. The chip soft-error rate (SER) is usually defined by the Failure-In-Time (FIT) or by Mean-Time-To-Failure (MTTF). One FIT is equivalent to 1 failure in 1 billion device hours of operation. MTTF, on the other hand, is inversely related to
FIT. For example, a FIT rate of 1000 is equivalent to 114 years (109/(1000x24x365)). It has been reported that advanced processors with large multimegabit-embedded SRAM can easily have soft failure rates in excess of 50,000 FIT at terrestrial level. The same error rate can also be achieved for standard high-density ASIC designs at 90 nm and below in [2]. For single-chip consumer applications, this error rate may not still be important for most designers, but for highreliability systems composed of multi-chip assemblies such a rate becomes intolerable [2]. Hence, for mission-critical or high-reliability applications such as military, avionics, medical systems, other sources for such errors need to be included in reliability analysis in addition to SETs. These additional error sources include SE soft delays [3], radiation induced clock jitters and clock pulses [4], SE crosstalk noise (SECN) pulses [5], and finally the SE crosstalk delay (SECD) effects [6] that have been reported relatively recently. All these errors occur under specific conditions: The soft delay effect occurs when high-energy particle hits the drain node of a CMOS gate’s transistor while signal at the output is transitioning. As a result, the signal is delayed and incorrect data storage may occur if the delayed signal violates the timing requirements. The SE clock jitter occurs when particles inject charge onto clock circuit nodes during clock edge present. An energetic particle strike can also create a “false clock pulse” on clock circuit nodes during when no clock pulse is present [4]. Finally, the SE crosstalk noise and delay effects occur via interconnect coupling effects. It is no longer just the normal signal switching events on aggressor (affecting) lines that are responsible for such crosstalk effects. As technology scaling continues, the charge deposited due to a SE hit particle on aggressor line may also create increasing cross-coupling noise effects, and in some cases, the noise effects even may exceed that of a normal switching crosstalk [5, 7]. Balasubramanian et al. [5] have shown that SETs can induce crosstalk effects on neighboring lines that can create logic level state changes for interconnects as small as 100 µm on technologies 90 nm and lower. The crosstalk effects induced by an SET have been studied for various interconnect lengths and deposited charges up to 1 pC using a simple lumped RC model for interconnect. They have also experimentally measured the SE induced crosstalk in a 90 nm process which proved the existence of the problem. Recent work in [7] proposed a fast SE crosstalk noise estimation method for use in design automation tools and briefly discussed the effect of SE crosstalk noise on circuit reliability using a test circuit. However, the SE crosstalk and SET effects have never been compared comprehensively.
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2 Hence, this work first compares SET and SE crosstalk noise effects in detail and then studies SE crosstalk SER contribution using test circuits. An SET generated on an affecting wire may also cause signal delays on neighboring wires via cross-coupling effects if these lines are in switching. This effect can be named as SE crosstalk delay [5]. There has not been any work to compare SE crosstalk delay to soft delay to our knowledge. Hence, this work also compares SECD to soft delay effect using 130, 90 and 65 nm technologies. In comparison, high-energy atmospheric neutrons at ground level have been assumed. Results are shown using HSPICE simulations with interconnect and device parameters derived from ITRS [1] and Predictive Technology Model (PTM) in [8]. This paper has been organized as follows: Section II explains various CL soft error sources. In Section III, we describe the simulation setup. In Section IV, we discuss on experimental results. After studying the effect of technology scaling on SECN and we make a comparison between SECN and SET effects. Then, we examine the SE crosstalk contribution on circuit reliability using MTTF calculations. In this section, an attempt has also been made to compare SE crosstalk delay to soft delay effect using 130, 90 and 65 nm technologies. It will be shown that SECD effects can be quite comparable to soft delay effect, and in some cases, may even exceed the soft delay. Finally, we conclude in Section V. II. SOFT ERROR SOURCES At ground level, soft errors are mainly induced by three different radiation mechanisms: alpha particles emitted from trace radioactive impurities in materials, interaction of lowenergy thermal neutrons with certain boron isotopes in device, and the reaction of high-energy cosmic neutrons (>1 MeV) with silicon and other device materials. In addition to SETs, radiation induced soft delay effects are also on the increase in CMOS logic designs. Soft delay can be described as the amount of delay induced on a CMOS gate due to high-energy particle strike on its sensitive region, which happens only during signal switching [3]. Incorrect data storage may occur if delayed signal violates the timing requirements of the storage elements. In other words, a soft delay error (SDE) is created. As an example, consider the circuit given in Fig. 1. An input pulse has been connected to the input of the first inverter. When Vo1 is undergoing a falling phase of transition, the PMOS transistor turns OFF and become susceptible to a particle strike. If a high energetic particle strikes node Vo 1 during this phase of transition, the generated current on PMOS transistor drain due to SE hit (shown with the current source) can pull the signal in positive direction causing longer transition times. The delay effect is observable at the output of the succeeding gate(s), if the path is logically enabled. It has been reported that the soft delay effect will become more pronounced in newer technologies due to reduced circuit node capacitances [3]. Hence, for high-reliability designs, SDEs must also be considered in the analysis in addition to SETs as the two error mechanisms are different in the way that they are masked.
Fig.1. Soft delay effect causing delay effects on succeeding gates.
For a CL circuit, there are three masking effects that can prevent an SET from propagating and being latched by a memory element: logical, electrical, and latch-window masking. On the other hand, SDEs can only be masked by logical and latch-window masking. Since soft delay is not a voltage glitch, electrical masking does not apply. If a signal is once delayed then it can propagate to circuit output(s) through functionally sensitized path(s) without any attenuation of the delay. Gill et al. [3] have compared SET and soft delay sensitivities of various benchmark circuits for a maximum Linear Energy Transfer (LET) of 20 MeV. The results for some benchmark circuits indicated that a higher number of nodes were sensitive to soft delay effects than SETs due to absence of electrical masking in soft delay propagation. Another soft error mechanism in CL, SE induced clock jitter, occurs when particles inject charge onto clock circuit nodes during clock edge present. As a result, clock edge moves back and forth and incorrect data may be stored. An energetic particle strike can also create a “false clock pulse” on clock circuit nodes during when there is no clock pulse present. This effect is also known as “radiation induced race” [4]. The SE crosstalk noise and delay effects occur via interconnect coupling mechanism. With advances in circuit scaling, increased cross-coupling effects occur among wires due to reduced distances and increased thickness to width ratio of interconnects. The interaction caused by parasitic coupling between wires, which is widely known as crosstalk, may cause undesired effects such as positive and negative glitches, overshoot, undershoot, signal delays or even signal speed-up. If crosstalk effects on the victim net (affected line) are large, they can propagate into storage elements that connected to victim line and can cause errors. With increasing coupling effects, an SET generated on a circuit node is no longer limited to the logic path existing between the hit node and a latch. Fig. 2a shows an aggressorvictim pair along with its drivers and receivers. Since inputs of both drivers are held at logic 1, the outputs are normally at logic 0. An SE hit at the drain of OFF PMOS transistor of the inverter driver causes output to go to logic 1 for some pulse duration. The SET voltage created then can affect the victim line through coupling capacitor Cc inducing SECN on the victim. The cross-coupling effects produced by SE hits can violate noise margins of gates connected to affected line and may result in logic errors. Serious effects may occur if the affected line is somewhat important such as a clock line.
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3
(a)
Nevertheless, researchers often use the 10- model, to represent the distributed RC line in simulations [9]. In this work, a 10- model is used for every 100µm of wire to represent the RC distributed behavior (Fig. 3). In our analysis, we ignore inductance effects and assume capacitive coupling as the dominant mechanism for crosstalk [7]. In simulations, two parallel 1000-m long interconnects on intermediate layer have been considered. It is assumed that the aggressor and victim driver sizes are at 2X (2 times the minimum size) and the loads at the end of wires are minimum sized identical inverters.
Fig.3. Simulation setup for SE crosstalk noise (b) Fig.2. a) SE crosstalk noise, b) SE crosstalk delay (Lumped model is for demonstration only).
Layout design engineers may have taken preventive measures such as line spacing to minimize crosstalk effects caused by normal switching. Although a given net passes the noise check, it may still pose a threat if SE crosstalk effects are not properly considered. This is due to the fact that an SET waveform rises much rapidly compared to normal aggressor waveform, and in turn may induce more noise on the victim net [5]. In addition, an SET generated on an affecting wire (due to particle hits on driver transistors) may cause signal delays on neighboring interconnects via cross-coupling effects if these lines are in switching. This effect can be named as SE crosstalk delay [6]. In the example shown in Fig. 2b, an SE particle hits the output node of aggressor driver and causes a voltage transient in positive direction. The transient then spreads into the victim line via coupling capacitance and causes a signal slowdown as shown on the victim line shown. The increase in interconnect delay due to SET coupling can affect circuit performance as delay changes may violate setup or hold time requirements of logic storage circuits connected to these receivers. III. SIMULATION SETUP When studying interconnect behavior, ideally a distributed model should be used to represent interconnect. However, due to the complexity issues, the behavior is mostly approximated by sections of lumped circuit elements. An accurate representation of a distributed RC circuit can be obtained by using multiple-π segments. Accuracy of the model increases as the number of segments increase, and the transient behavior approaches that of a distributed RC line. Kawaguchi and Sakurai have reported that the error in simulating delay of the distributed RC line by using 5-π segment is less than 1% for almost all cases [9].
The current source in Fig. 3 represents an SE hit at the output of aggressor driver. In simulations, we assume high-energy atmospheric neutrons at ground level. The max LET of such particles is approximately at 15 MeV-cm2/mg [10]. A particle with an LET of 1 MeV cm2/mg deposits around 10 fC/μm along its track, hence an upper bound of 150 fC/μm charge density can be calculated. The collected charge, on the other hand, can be found by multiplying the charge density with the charge collection depth. In [10], Zhou and Mohanram have calculated the upper bounds of 0.21 pC, 0.15 pC and 0.11 pC for 130nm, 100nm and 70nm technologies, respectively, considering actual doping densities. In this work, we assume a maximum deposited charge of 150 fC in all three technologies as we study various soft error mechanisms. Researchers reported that, for higher LETs (>10 MeV), the current pulses have a plateau region in addition to the double exponential wave shape [11]. Hence, the use of ideal double exponential current source alone is not sufficiently accurate, although it provides a reasonable first-order estimate as a base function model. TCAD based methods, however, require large computation times while achieving a great level of accuracy. It is desirable to model particle strikes as current sources that can be easily injected on circuit nodes for performing quick SPICE simulations. Our modeling here is based on a combined approach where device simulations are first used to characterize current pulses for ion strikes and then these pulses are later used as inputs to HSPICE to emulate ion strikes [11]. For this purpose, the data obtained from device simulations are fitted to a double exponential model (given in (1)) with appropriate characteristic parameters. This model assumes that the SE current pulse exhibits an exponential behavior during its rise and decay. The double exponential model given in (1) is composed of an exponential function accounting for the rise in magnitude
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4 of the resulting single-event current and another exponential function modeling the decay in magnitude of this current. t / I max (1 e 1 ) I (t ) ( t t d ) / 2 I maxe
if t t d if t t d
(1)
where, 1 and 2 are the rise and the fall time constants of current pulse, respectively. Imax is its magnitude, and td is the delay time for the falling exponential that controls the duration of the plateau effect. IV. EXPERIMENTAL RESULTS A. Analysis of Single Event Crosstalk and Comparison to Single Event Transients In order to analyze SECN, both the aggressor and victim driver inputs are connected to “logic high”. In this case, normally aggressor driver output would be at “logic low” but it would be taken to “logic high” if there is a sufficient SE hit charge on output node of the driver. Fig. 4 shows the effect of various deposited charges on SECN magnitude. The results here are shown for the three technologies. Figure indicates that SE induced crosstalk amplitude increases in proportion to the deposited charge in all three technologies. The data also shows the vulnerability of circuits to SET crosstalk noise as feature sizes scale down. A 125 fC hit charge causes crosstalk noise amplitude of 380 mV in 130 nm technology, while the same charge causes a noise amplitude of 675 mV in 65 nm.
Fig. 4. SE induced crosstalk amplitude vs. technology.
In order to compare SET to SE crosstalk, we have used the circuit shown in Fig. 1 for SET simulation and the set-up shown in Fig. 3 for SECN simulation. Referring to Fig. 1, the input to the first inverter has been tied to VDD instead of a switching waveform for simulating the SET. As in SE crosstalk simulation, the hit driver has been sized at 2X while the following inverters have been taken as minimum size (1X) inverters, similar to victim line end inverters in Fig. 3. An SE hit has been simulated at the output of the first inverter using a double exponential source given in (1) and the hit charges needed to cause switching on the following inverters have been determined. Then similarly in Fig. 3, the victim receiver waveforms VOV1 and VOV2 have been observed
for switching activity and required minimum deposited charges needed on the aggressor driver output have been determined. Table I shows the results obtained for all three technologies. In all three technologies considered, the SE crosstalk effect requires approximately six times more deposited charge in order to cause switching on the receiver gate, but when this happens, multiple SEU effects occur. For example, a 120 fC deposited charge in 65 nm technology results in switching of both aggressor and victim receivers. TABLE I THE MINIMUM HIT CHARGES NEEDED FOR SET AND SE CROSSTALK PROPAGATION SE Effect
130 nm
90 nm
65 nm
SET
26.8fC
21.4fC
17.5fC
SECN
165.4fC
137.4fC
113.1fC
In order to study the effect of SE crosstalk on circuit reliability, the error rate or probability contribution should be identified. For this, the ALU and ACCU (Adder/Accumulator) modules from AM2901 4-bit microprocessor bit-slice have been selected for SER simulations. Although the AM2901 bitslice is dated, these modules include large number of nodes and many gates. For example, the ALU module itself contains 83 gates, 12 input and 10 outputs and 276 SE vulnerable nodes [12]. Due to large number of the simulations that need to be completed, only 90 and 65 nm technologies are considered. The circuit has been laid out in 90 and 65 nm technologies using Microwind CMOS layout design and simulation tool. The minimum allowable spacing between wires has been taken during the routing process. All circuit parasitic information has been extracted and the resulting Spice file has been simulated with and without considering the SECN effects. In calculating the SER without any crosstalk effects, the cross-coupling capacitances among wires have been ignored during simulations. The simulation methodology assumes that, with a particle strike, positive or negative charges up to 150 fC are equally likely to be generated. Different charge injection levels from 10 to 150 fC have been evaluated. It is also assumed that no timing window masking occurs, i.e., once an SET reaches at one of the circuit’s outputs, it has been assumed that soft error condition is generated. With the large number of input patterns and nodes to be simulated, the simulation time can be very time consuming; hence in order to reduce runtime, simulations are performed for only randomly selected input combinations from which a reasonably accurate SER estimate can be obtained. The probability of failure for a circuit, POFC is given by: n
__
POFC wi Ei , i 1
with wi
Ai
i1 Ai
(2)
n
__
Here, Ai is the area of the node i; and Ei is given as:
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5 __
Ei
1 k
k
E
i
(3)
i 1
where, if the injection into node i results in a fault 1, Ei 0, no fault k = (the number of input combinations)x (particle charge injection levels). Assuming, the particle density at sea level (New York) is approximately 100,000/cm2/yr, MTTF can be calculated probability from POFC: MTTF
1 POFC Area of circuit 100,000
(4)
Fig. 5 shows the calculated SER values of the ALU and ACCU modules for 90 and 65 nm technologies considered. For both technologies, the probability of failure increases when the SECN effects are included. As a result, the MTTF values decreases with coupling. Referring the Fig. 5, we also notice that the MTTF values increase for the same circuit in 65 nm compared to 90 nm technology. The reduction in circuit size offsets the effect of increased circuit sensitivity in 65 nm. The circuit area was about 50% smaller compared to 90 nm technologies, as a result, the probability of failure decreased in 65 nm.
the protection may not be sufficient, as delay caused by SE coupling can be larger. In order to analyze the SECD, we consider the same interconnect system discussed earlier and assume similar driver sizes. Referring to Fig. 3, a rising pulse waveform with a 100 ps rise time has been applied to victim driver (instead of VDD) while aggressor driver was kept at VDD. An SE hit charge of up to 150 fC has been simulated at the end of the aggressor driver to examine the effect of SET on victim line delay. Two inverters have been used to filter out the distortion on victim line and the delay is measured at VOV2. For soft delay simulation, the set-up shown in Fig. 1 has been utilized and the results are compared to that of SECD simulation. For soft delay simulation, an input pulse with a rise time of 100 ps has been connected to the input of the first inverter. An SE hit has been injected at the output of the first inverter around halfway the falling signal transition in order to maximize the induced delay amount. Similar to SECD simulation, the hit driver has been sized at 2X with the second and third inverters taken as minimum size inverters. These inverters filter out the distortion caused by the SE pulse and the delay is measure finally at VO3. Fig. 6 shows the resulting SE crosstalk and soft delays for 130, 90 and 65 nm technologies considered.
Fig. 5. SE crosstalk contribution to soft error rate. Fig. 6. SECD vs. soft delay comparison for 130, 90 and 65 nm technologies
From Fig. 5, we observe that the MTTF value for the test circuits decreases on the average by 11.6%, and 13.7%, respectively, for 90 and 65 nm technologies when coupling effects are included. This indicates that SECN effects increase circuit sensitivity to radiation and hence may need to be incorporated in reliability analysis especially for missioncritical applications. B. Analysis of SE Crosstalk Delay and Comparison to Soft Delay Previously, it was shown that SETs can induce larger crosstalk delays than normal switching waveforms above a certain deposited hit charge [6]. During layout optimization, the wires might be spaced out enough to prevent timing violations caused by normal aggressor switching. However,
These plots indicate that the SECD can be quite comparable to the soft delay effect, especially for smaller technologies. As deposited charge value increases, soft delay increase seems to slow down. This delay saturation effect was also observed in inverter and nand gates considered in [3]. We have also observed that, after a particular deposited charge, the SECD exceeds the soft delay amount in all three technologies considered. These charges were at 145, 105 and 80 fC for 130, 90 and 65 nm technologies, respectively. With coupling effects, the hit charge effectively couples to victim network before it causes hit node voltage to saturate. This might be the reason why the delay saturation effect was not observed in SECD.
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6 V. CONCLUSION With continuous scaling of current VLSI technology, the majority of the observed radiation induced soft failures will be due to transients that occur in CL. For mission-critical applications, various sources for such radiation induced soft errors need to be included in reliability analysis in addition to SETs. This paper studied SE crosstalk noise and delay effects in detail using a distributed model for interconnect. Results are shown using HSPICE Simulations with interconnect and device parameters derived from ITRS and PTM for 130, 90 and 65 nm technologies. The data indicates that the vulnerability of circuits to SE crosstalk noise as feature sizes scale down. We have also compared SE crosstalk noise effects to SETs and found that multiple SEUs might occur when coupling effects are included. The interconnect coupling effects can cause SETs to contaminate electronically unrelated circuit paths which can in turn increase the “SE Susceptibility” of CMOS circuits to SETs. The SE crosstalk contribution to circuit soft error rate has been examined (in terms of MTTF) using the ALU and ACCU modules from AM2901 4-bit slice. Simulation results show that the SE coupling effects increase circuit sensitivity to radiation; as a result MTTF values reduce. For 65 nm technology, the MTTF values decrease by 14% on average when coupling effects are included. This work also compared SECD to soft delay effect using 130, 90 and 65 nm technologies. Results showed that, for newer technologies, SECD can be quite comparable to soft delay effect, and in some cases may even exceed the soft delay. In contrast to soft delay case, the delay saturation effects was not observed for SECD since the presence of interconnect coupling effectively transfers deposited charge to neighboring lines for charge levels considered. In order to complement the SE hardening process, coupling effects among interconnects need to be considered in the SE hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. ACKNOWLEDGMENT This work was supported in part by the Research Enhancement grant from Lamar University and TSGC New Investigations Program (NIP) grant from NASA.
technologies,” IEEE Transactions on Nuclear Science, vol. 53, no. 6, Dec. 2006. [6] S. Sayil, A. B. Akkur, “Mitigation for single event coupling delay,” International Journal of Electronics, Volume 97, Issue 1, pages 17 – 29, January 2010. [7] Sayil, S., Boorla, V.K.,Yeddula, S.R., “Modeling Single Event Crosstalk in Nanometer Technologies”, IEEE Trans. on Nucl. Sci., vol. 57 , no. 5 , pt. 2, pp. 2493 – 2502, October 2011. [8] Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm, 2012. [9] H. Kawaguchi, T. Sakurai, “Delay and noise formulas for capacitively coupled distributed RC lines”, Proc. Of Asian South Pacific DAC, pp. 35–38, 1998. [10] Q. Zhou and K. Mohanram, ““Cost-effective radiation hardening technique for combinational logic,” in Proc. ICCAD, Nov. 2004, pp. 100–106. [11] S. Uznanski, G. Gasiot, P. Roche, J. L. Autran, and C. Tavernier, “Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops,” IEEE Trans. Nucl. Sci., vol. 57, no. 4, pp. 1876–1883, Aug. 2010. [12] L.W. Massengill, A.E. Baranski, D.O. Van Nort, J. Meng, and B.L. Bhuva, “Analysis of single-event effects in combinational logicsimulation of the AM2901 bitslice processor,” IEEE Trans. on Nuclear Science, vol. 47, no.6, pp. 2609-2615, 2000.
Selahattin Sayil received his Ph.D. degree in Electrical Engineering from Vanderbilt University, TN, in 2000. He is currently an Associate Professor in Electrical Engineering at Lamar University. His current research interests include Interconnect Analysis, Soft Error Modeling and Mitigation. He is an Associate Editor of International Journal of Electronics. Sumanth R. Yeddula received his Master of Science Degree in Electrical Engineering from Lamar University in August 2012. His research areas include EEG analysis, Bio-medical Signal Processing, VLSI Design and modeling. He currently works for HTC Global Services as a consultant. Juyu Wang received her Master of Science Degree in Electrical Engineering from Lamar University in May 2010. Her research areas include Single Event Hardening, Leakage Power Optimization, and Carbon nanotube Interconnects. Direct questions and comments about this article to Selahattin Sayil, Department of Electrical Engineering, Lamar University, PO Box 10029, Beaumont, TX 77710; [email protected].
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International International Technology Roadmap for Semiconductors, 2011 Edition, Semiconductor Industry Association (SIA), San Jose, CA. B. Jacob, S. W. Ng, and D. T. Wang, Memory Systems: Cache, DRAM, Disk., Morgan Kaufmann Publishers, September 2007. B. S. Gill, C. Papachristou, F. G. Wolff, “Soft delay error effects in CMOS combinational circuits,” Proc. of 22 nd VLSI Test Symposium, pp. 325-330, 2004. N. Seifert, P. Shipley, M.D. Pant, V. Ambrose, B. Gill, “Radiationinduced clock jitter and race,” Proc. Int. Phys. Reliab. Symp., pp. 215222, 2005. A. Balasubramanian, Sternberg, B. L. Bhuva, L. W. Massengill, “Crosstalk effects caused by single event hits in deep sub-micron CMOS
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1
Single Event Coupling Soft Errors in Nanoscale CMOS Circuits Selahattin Sayil, Member, IEEE, Sumanth R. Yeddula, Student Member, IEEE, Juyu Wang, Student Member Abstract— Due to scaling effects, circuits become increasingly sensitive to transients caused by single event (SE) particles. Researchers mostly considered SE transients (SETs) as the main cause for combinational logic (CL) related radiation-induced soft errors. However, for high-reliability applications additional sources such as SE soft delays, clock jitter, race and SE coupling effects need to be included in analysis. This work focuses on coupling-induced soft error mechanisms in CL, namely the SE crosstalk noise and delay effects. An attempt has been made to compare SE crosstalk noise and SET effects, and crosstalk contribution to soft error rate has been examined. In addition, SE coupling delay effects have been compared to radiation induced soft delay effect for various technologies. In comparisons, the distributed nature of interconnect has been taken into account and results are demonstrated using HSPICE simulations with interconnect and device parameters derived in 130, 90 and 65 nm technologies. Index Terms— Single Event Crosstalk, Soft Error Reliability, Coupling Noise.
I. INTRODUCTION
T
HE International Technology Roadmap for Semiconductors (2011 Edition) has pointed to signal integrity in chips as a major challenge [1]. Recently, radiationinduced soft errors in commercial nanometer CMOS technologies have become a growing concern. Soft errors in memory have been a very well known problem at terrestrial level. However, due to increasing clock frequencies and shrinking device sizes, it has been predicted that the majority of the observed radiation induced soft failures will be due to transients that will occur in combinational logic (CL) circuits below 65 nm [2]. When an incident charged particle strikes the sensitive area within a circuit such as the depletion region of transistor drains, many electron-hole pairs are created due to ionization mechanism. These free carriers can later drift under the electric field creating a transient voltage pulse. This transient is also known as “Single Event Transient” or SET. An SET may pass through a series of CL gates and reach to storage elements under certain conditions. If it arrives at the storage element during its latching window, incorrect data may be stored resulting in soft error or single event upset (SEU). For advanced technologies, circuit scaling causes reduced supply voltages, transistor drive currents and shrinking node capacitances. All these factors can contribute to increased circuit sensitivity to SETs in CL due to reduced critical charge. The chip soft-error rate (SER) is usually defined by the Failure-In-Time (FIT) or by Mean-Time-To-Failure (MTTF). One FIT is equivalent to 1 failure in 1 billion device hours of operation. MTTF, on the other hand, is inversely related to
FIT. For example, a FIT rate of 1000 is equivalent to 114 years (109/(1000x24x365)). It has been reported that advanced processors with large multimegabit-embedded SRAM can easily have soft failure rates in excess of 50,000 FIT at terrestrial level. The same error rate can also be achieved for standard high-density ASIC designs at 90 nm and below in [2]. For single-chip consumer applications, this error rate may not still be important for most designers, but for highreliability systems composed of multi-chip assemblies such a rate becomes intolerable [2]. Hence, for mission-critical or high-reliability applications such as military, avionics, medical systems, other sources for such errors need to be included in reliability analysis in addition to SETs. These additional error sources include SE soft delays [3], radiation induced clock jitters and clock pulses [4], SE crosstalk noise (SECN) pulses [5], and finally the SE crosstalk delay (SECD) effects [6] that have been reported relatively recently. All these errors occur under specific conditions: The soft delay effect occurs when high-energy particle hits the drain node of a CMOS gate’s transistor while signal at the output is transitioning. As a result, the signal is delayed and incorrect data storage may occur if the delayed signal violates the timing requirements. The SE clock jitter occurs when particles inject charge onto clock circuit nodes during clock edge present. An energetic particle strike can also create a “false clock pulse” on clock circuit nodes during when no clock pulse is present [4]. Finally, the SE crosstalk noise and delay effects occur via interconnect coupling effects. It is no longer just the normal signal switching events on aggressor (affecting) lines that are responsible for such crosstalk effects. As technology scaling continues, the charge deposited due to a SE hit particle on aggressor line may also create increasing cross-coupling noise effects, and in some cases, the noise effects even may exceed that of a normal switching crosstalk [5, 7]. Balasubramanian et al. [5] have shown that SETs can induce crosstalk effects on neighboring lines that can create logic level state changes for interconnects as small as 100 µm on technologies 90 nm and lower. The crosstalk effects induced by an SET have been studied for various interconnect lengths and deposited charges up to 1 pC using a simple lumped RC model for interconnect. They have also experimentally measured the SE induced crosstalk in a 90 nm process which proved the existence of the problem. Recent work in [7] proposed a fast SE crosstalk noise estimation method for use in design automation tools and briefly discussed the effect of SE crosstalk noise on circuit reliability using a test circuit. However, the SE crosstalk and SET effects have never been compared comprehensively.
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2 Hence, this work first compares SET and SE crosstalk noise effects in detail and then studies SE crosstalk SER contribution using test circuits. An SET generated on an affecting wire may also cause signal delays on neighboring wires via cross-coupling effects if these lines are in switching. This effect can be named as SE crosstalk delay [5]. There has not been any work to compare SE crosstalk delay to soft delay to our knowledge. Hence, this work also compares SECD to soft delay effect using 130, 90 and 65 nm technologies. In comparison, high-energy atmospheric neutrons at ground level have been assumed. Results are shown using HSPICE simulations with interconnect and device parameters derived from ITRS [1] and Predictive Technology Model (PTM) in [8]. This paper has been organized as follows: Section II explains various CL soft error sources. In Section III, we describe the simulation setup. In Section IV, we discuss on experimental results. After studying the effect of technology scaling on SECN and we make a comparison between SECN and SET effects. Then, we examine the SE crosstalk contribution on circuit reliability using MTTF calculations. In this section, an attempt has also been made to compare SE crosstalk delay to soft delay effect using 130, 90 and 65 nm technologies. It will be shown that SECD effects can be quite comparable to soft delay effect, and in some cases, may even exceed the soft delay. Finally, we conclude in Section V. II. SOFT ERROR SOURCES At ground level, soft errors are mainly induced by three different radiation mechanisms: alpha particles emitted from trace radioactive impurities in materials, interaction of lowenergy thermal neutrons with certain boron isotopes in device, and the reaction of high-energy cosmic neutrons (>1 MeV) with silicon and other device materials. In addition to SETs, radiation induced soft delay effects are also on the increase in CMOS logic designs. Soft delay can be described as the amount of delay induced on a CMOS gate due to high-energy particle strike on its sensitive region, which happens only during signal switching [3]. Incorrect data storage may occur if delayed signal violates the timing requirements of the storage elements. In other words, a soft delay error (SDE) is created. As an example, consider the circuit given in Fig. 1. An input pulse has been connected to the input of the first inverter. When Vo1 is undergoing a falling phase of transition, the PMOS transistor turns OFF and become susceptible to a particle strike. If a high energetic particle strikes node Vo 1 during this phase of transition, the generated current on PMOS transistor drain due to SE hit (shown with the current source) can pull the signal in positive direction causing longer transition times. The delay effect is observable at the output of the succeeding gate(s), if the path is logically enabled. It has been reported that the soft delay effect will become more pronounced in newer technologies due to reduced circuit node capacitances [3]. Hence, for high-reliability designs, SDEs must also be considered in the analysis in addition to SETs as the two error mechanisms are different in the way that they are masked.
Fig.1. Soft delay effect causing delay effects on succeeding gates.
For a CL circuit, there are three masking effects that can prevent an SET from propagating and being latched by a memory element: logical, electrical, and latch-window masking. On the other hand, SDEs can only be masked by logical and latch-window masking. Since soft delay is not a voltage glitch, electrical masking does not apply. If a signal is once delayed then it can propagate to circuit output(s) through functionally sensitized path(s) without any attenuation of the delay. Gill et al. [3] have compared SET and soft delay sensitivities of various benchmark circuits for a maximum Linear Energy Transfer (LET) of 20 MeV. The results for some benchmark circuits indicated that a higher number of nodes were sensitive to soft delay effects than SETs due to absence of electrical masking in soft delay propagation. Another soft error mechanism in CL, SE induced clock jitter, occurs when particles inject charge onto clock circuit nodes during clock edge present. As a result, clock edge moves back and forth and incorrect data may be stored. An energetic particle strike can also create a “false clock pulse” on clock circuit nodes during when there is no clock pulse present. This effect is also known as “radiation induced race” [4]. The SE crosstalk noise and delay effects occur via interconnect coupling mechanism. With advances in circuit scaling, increased cross-coupling effects occur among wires due to reduced distances and increased thickness to width ratio of interconnects. The interaction caused by parasitic coupling between wires, which is widely known as crosstalk, may cause undesired effects such as positive and negative glitches, overshoot, undershoot, signal delays or even signal speed-up. If crosstalk effects on the victim net (affected line) are large, they can propagate into storage elements that connected to victim line and can cause errors. With increasing coupling effects, an SET generated on a circuit node is no longer limited to the logic path existing between the hit node and a latch. Fig. 2a shows an aggressorvictim pair along with its drivers and receivers. Since inputs of both drivers are held at logic 1, the outputs are normally at logic 0. An SE hit at the drain of OFF PMOS transistor of the inverter driver causes output to go to logic 1 for some pulse duration. The SET voltage created then can affect the victim line through coupling capacitor Cc inducing SECN on the victim. The cross-coupling effects produced by SE hits can violate noise margins of gates connected to affected line and may result in logic errors. Serious effects may occur if the affected line is somewhat important such as a clock line.
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3
(a)
Nevertheless, researchers often use the 10- model, to represent the distributed RC line in simulations [9]. In this work, a 10- model is used for every 100µm of wire to represent the RC distributed behavior (Fig. 3). In our analysis, we ignore inductance effects and assume capacitive coupling as the dominant mechanism for crosstalk [7]. In simulations, two parallel 1000-m long interconnects on intermediate layer have been considered. It is assumed that the aggressor and victim driver sizes are at 2X (2 times the minimum size) and the loads at the end of wires are minimum sized identical inverters.
Fig.3. Simulation setup for SE crosstalk noise (b) Fig.2. a) SE crosstalk noise, b) SE crosstalk delay (Lumped model is for demonstration only).
Layout design engineers may have taken preventive measures such as line spacing to minimize crosstalk effects caused by normal switching. Although a given net passes the noise check, it may still pose a threat if SE crosstalk effects are not properly considered. This is due to the fact that an SET waveform rises much rapidly compared to normal aggressor waveform, and in turn may induce more noise on the victim net [5]. In addition, an SET generated on an affecting wire (due to particle hits on driver transistors) may cause signal delays on neighboring interconnects via cross-coupling effects if these lines are in switching. This effect can be named as SE crosstalk delay [6]. In the example shown in Fig. 2b, an SE particle hits the output node of aggressor driver and causes a voltage transient in positive direction. The transient then spreads into the victim line via coupling capacitance and causes a signal slowdown as shown on the victim line shown. The increase in interconnect delay due to SET coupling can affect circuit performance as delay changes may violate setup or hold time requirements of logic storage circuits connected to these receivers. III. SIMULATION SETUP When studying interconnect behavior, ideally a distributed model should be used to represent interconnect. However, due to the complexity issues, the behavior is mostly approximated by sections of lumped circuit elements. An accurate representation of a distributed RC circuit can be obtained by using multiple-π segments. Accuracy of the model increases as the number of segments increase, and the transient behavior approaches that of a distributed RC line. Kawaguchi and Sakurai have reported that the error in simulating delay of the distributed RC line by using 5-π segment is less than 1% for almost all cases [9].
The current source in Fig. 3 represents an SE hit at the output of aggressor driver. In simulations, we assume high-energy atmospheric neutrons at ground level. The max LET of such particles is approximately at 15 MeV-cm2/mg [10]. A particle with an LET of 1 MeV cm2/mg deposits around 10 fC/μm along its track, hence an upper bound of 150 fC/μm charge density can be calculated. The collected charge, on the other hand, can be found by multiplying the charge density with the charge collection depth. In [10], Zhou and Mohanram have calculated the upper bounds of 0.21 pC, 0.15 pC and 0.11 pC for 130nm, 100nm and 70nm technologies, respectively, considering actual doping densities. In this work, we assume a maximum deposited charge of 150 fC in all three technologies as we study various soft error mechanisms. Researchers reported that, for higher LETs (>10 MeV), the current pulses have a plateau region in addition to the double exponential wave shape [11]. Hence, the use of ideal double exponential current source alone is not sufficiently accurate, although it provides a reasonable first-order estimate as a base function model. TCAD based methods, however, require large computation times while achieving a great level of accuracy. It is desirable to model particle strikes as current sources that can be easily injected on circuit nodes for performing quick SPICE simulations. Our modeling here is based on a combined approach where device simulations are first used to characterize current pulses for ion strikes and then these pulses are later used as inputs to HSPICE to emulate ion strikes [11]. For this purpose, the data obtained from device simulations are fitted to a double exponential model (given in (1)) with appropriate characteristic parameters. This model assumes that the SE current pulse exhibits an exponential behavior during its rise and decay. The double exponential model given in (1) is composed of an exponential function accounting for the rise in magnitude
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4 of the resulting single-event current and another exponential function modeling the decay in magnitude of this current. t / I max (1 e 1 ) I (t ) ( t t d ) / 2 I maxe
if t t d if t t d
(1)
where, 1 and 2 are the rise and the fall time constants of current pulse, respectively. Imax is its magnitude, and td is the delay time for the falling exponential that controls the duration of the plateau effect. IV. EXPERIMENTAL RESULTS A. Analysis of Single Event Crosstalk and Comparison to Single Event Transients In order to analyze SECN, both the aggressor and victim driver inputs are connected to “logic high”. In this case, normally aggressor driver output would be at “logic low” but it would be taken to “logic high” if there is a sufficient SE hit charge on output node of the driver. Fig. 4 shows the effect of various deposited charges on SECN magnitude. The results here are shown for the three technologies. Figure indicates that SE induced crosstalk amplitude increases in proportion to the deposited charge in all three technologies. The data also shows the vulnerability of circuits to SET crosstalk noise as feature sizes scale down. A 125 fC hit charge causes crosstalk noise amplitude of 380 mV in 130 nm technology, while the same charge causes a noise amplitude of 675 mV in 65 nm.
Fig. 4. SE induced crosstalk amplitude vs. technology.
In order to compare SET to SE crosstalk, we have used the circuit shown in Fig. 1 for SET simulation and the set-up shown in Fig. 3 for SECN simulation. Referring to Fig. 1, the input to the first inverter has been tied to VDD instead of a switching waveform for simulating the SET. As in SE crosstalk simulation, the hit driver has been sized at 2X while the following inverters have been taken as minimum size (1X) inverters, similar to victim line end inverters in Fig. 3. An SE hit has been simulated at the output of the first inverter using a double exponential source given in (1) and the hit charges needed to cause switching on the following inverters have been determined. Then similarly in Fig. 3, the victim receiver waveforms VOV1 and VOV2 have been observed
for switching activity and required minimum deposited charges needed on the aggressor driver output have been determined. Table I shows the results obtained for all three technologies. In all three technologies considered, the SE crosstalk effect requires approximately six times more deposited charge in order to cause switching on the receiver gate, but when this happens, multiple SEU effects occur. For example, a 120 fC deposited charge in 65 nm technology results in switching of both aggressor and victim receivers. TABLE I THE MINIMUM HIT CHARGES NEEDED FOR SET AND SE CROSSTALK PROPAGATION SE Effect
130 nm
90 nm
65 nm
SET
26.8fC
21.4fC
17.5fC
SECN
165.4fC
137.4fC
113.1fC
In order to study the effect of SE crosstalk on circuit reliability, the error rate or probability contribution should be identified. For this, the ALU and ACCU (Adder/Accumulator) modules from AM2901 4-bit microprocessor bit-slice have been selected for SER simulations. Although the AM2901 bitslice is dated, these modules include large number of nodes and many gates. For example, the ALU module itself contains 83 gates, 12 input and 10 outputs and 276 SE vulnerable nodes [12]. Due to large number of the simulations that need to be completed, only 90 and 65 nm technologies are considered. The circuit has been laid out in 90 and 65 nm technologies using Microwind CMOS layout design and simulation tool. The minimum allowable spacing between wires has been taken during the routing process. All circuit parasitic information has been extracted and the resulting Spice file has been simulated with and without considering the SECN effects. In calculating the SER without any crosstalk effects, the cross-coupling capacitances among wires have been ignored during simulations. The simulation methodology assumes that, with a particle strike, positive or negative charges up to 150 fC are equally likely to be generated. Different charge injection levels from 10 to 150 fC have been evaluated. It is also assumed that no timing window masking occurs, i.e., once an SET reaches at one of the circuit’s outputs, it has been assumed that soft error condition is generated. With the large number of input patterns and nodes to be simulated, the simulation time can be very time consuming; hence in order to reduce runtime, simulations are performed for only randomly selected input combinations from which a reasonably accurate SER estimate can be obtained. The probability of failure for a circuit, POFC is given by: n
__
POFC wi Ei , i 1
with wi
Ai
i1 Ai
(2)
n
__
Here, Ai is the area of the node i; and Ei is given as:
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5 __
Ei
1 k
k
E
i
(3)
i 1
where, if the injection into node i results in a fault 1, Ei 0, no fault k = (the number of input combinations)x (particle charge injection levels). Assuming, the particle density at sea level (New York) is approximately 100,000/cm2/yr, MTTF can be calculated probability from POFC: MTTF
1 POFC Area of circuit 100,000
(4)
Fig. 5 shows the calculated SER values of the ALU and ACCU modules for 90 and 65 nm technologies considered. For both technologies, the probability of failure increases when the SECN effects are included. As a result, the MTTF values decreases with coupling. Referring the Fig. 5, we also notice that the MTTF values increase for the same circuit in 65 nm compared to 90 nm technology. The reduction in circuit size offsets the effect of increased circuit sensitivity in 65 nm. The circuit area was about 50% smaller compared to 90 nm technologies, as a result, the probability of failure decreased in 65 nm.
the protection may not be sufficient, as delay caused by SE coupling can be larger. In order to analyze the SECD, we consider the same interconnect system discussed earlier and assume similar driver sizes. Referring to Fig. 3, a rising pulse waveform with a 100 ps rise time has been applied to victim driver (instead of VDD) while aggressor driver was kept at VDD. An SE hit charge of up to 150 fC has been simulated at the end of the aggressor driver to examine the effect of SET on victim line delay. Two inverters have been used to filter out the distortion on victim line and the delay is measured at VOV2. For soft delay simulation, the set-up shown in Fig. 1 has been utilized and the results are compared to that of SECD simulation. For soft delay simulation, an input pulse with a rise time of 100 ps has been connected to the input of the first inverter. An SE hit has been injected at the output of the first inverter around halfway the falling signal transition in order to maximize the induced delay amount. Similar to SECD simulation, the hit driver has been sized at 2X with the second and third inverters taken as minimum size inverters. These inverters filter out the distortion caused by the SE pulse and the delay is measure finally at VO3. Fig. 6 shows the resulting SE crosstalk and soft delays for 130, 90 and 65 nm technologies considered.
Fig. 5. SE crosstalk contribution to soft error rate. Fig. 6. SECD vs. soft delay comparison for 130, 90 and 65 nm technologies
From Fig. 5, we observe that the MTTF value for the test circuits decreases on the average by 11.6%, and 13.7%, respectively, for 90 and 65 nm technologies when coupling effects are included. This indicates that SECN effects increase circuit sensitivity to radiation and hence may need to be incorporated in reliability analysis especially for missioncritical applications. B. Analysis of SE Crosstalk Delay and Comparison to Soft Delay Previously, it was shown that SETs can induce larger crosstalk delays than normal switching waveforms above a certain deposited hit charge [6]. During layout optimization, the wires might be spaced out enough to prevent timing violations caused by normal aggressor switching. However,
These plots indicate that the SECD can be quite comparable to the soft delay effect, especially for smaller technologies. As deposited charge value increases, soft delay increase seems to slow down. This delay saturation effect was also observed in inverter and nand gates considered in [3]. We have also observed that, after a particular deposited charge, the SECD exceeds the soft delay amount in all three technologies considered. These charges were at 145, 105 and 80 fC for 130, 90 and 65 nm technologies, respectively. With coupling effects, the hit charge effectively couples to victim network before it causes hit node voltage to saturate. This might be the reason why the delay saturation effect was not observed in SECD.
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6 V. CONCLUSION With continuous scaling of current VLSI technology, the majority of the observed radiation induced soft failures will be due to transients that occur in CL. For mission-critical applications, various sources for such radiation induced soft errors need to be included in reliability analysis in addition to SETs. This paper studied SE crosstalk noise and delay effects in detail using a distributed model for interconnect. Results are shown using HSPICE Simulations with interconnect and device parameters derived from ITRS and PTM for 130, 90 and 65 nm technologies. The data indicates that the vulnerability of circuits to SE crosstalk noise as feature sizes scale down. We have also compared SE crosstalk noise effects to SETs and found that multiple SEUs might occur when coupling effects are included. The interconnect coupling effects can cause SETs to contaminate electronically unrelated circuit paths which can in turn increase the “SE Susceptibility” of CMOS circuits to SETs. The SE crosstalk contribution to circuit soft error rate has been examined (in terms of MTTF) using the ALU and ACCU modules from AM2901 4-bit slice. Simulation results show that the SE coupling effects increase circuit sensitivity to radiation; as a result MTTF values reduce. For 65 nm technology, the MTTF values decrease by 14% on average when coupling effects are included. This work also compared SECD to soft delay effect using 130, 90 and 65 nm technologies. Results showed that, for newer technologies, SECD can be quite comparable to soft delay effect, and in some cases may even exceed the soft delay. In contrast to soft delay case, the delay saturation effects was not observed for SECD since the presence of interconnect coupling effectively transfers deposited charge to neighboring lines for charge levels considered. In order to complement the SE hardening process, coupling effects among interconnects need to be considered in the SE hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. ACKNOWLEDGMENT This work was supported in part by the Research Enhancement grant from Lamar University and TSGC New Investigations Program (NIP) grant from NASA.
technologies,” IEEE Transactions on Nuclear Science, vol. 53, no. 6, Dec. 2006. [6] S. Sayil, A. B. Akkur, “Mitigation for single event coupling delay,” International Journal of Electronics, Volume 97, Issue 1, pages 17 – 29, January 2010. [7] Sayil, S., Boorla, V.K.,Yeddula, S.R., “Modeling Single Event Crosstalk in Nanometer Technologies”, IEEE Trans. on Nucl. Sci., vol. 57 , no. 5 , pt. 2, pp. 2493 – 2502, October 2011. [8] Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm, 2012. [9] H. Kawaguchi, T. Sakurai, “Delay and noise formulas for capacitively coupled distributed RC lines”, Proc. Of Asian South Pacific DAC, pp. 35–38, 1998. [10] Q. Zhou and K. Mohanram, ““Cost-effective radiation hardening technique for combinational logic,” in Proc. ICCAD, Nov. 2004, pp. 100–106. [11] S. Uznanski, G. Gasiot, P. Roche, J. L. Autran, and C. Tavernier, “Single event upset and multiple cell upset modeling in commercial bulk 65 nm CMOS SRAMs and flip-flops,” IEEE Trans. Nucl. Sci., vol. 57, no. 4, pp. 1876–1883, Aug. 2010. [12] L.W. Massengill, A.E. Baranski, D.O. Van Nort, J. Meng, and B.L. Bhuva, “Analysis of single-event effects in combinational logicsimulation of the AM2901 bitslice processor,” IEEE Trans. on Nuclear Science, vol. 47, no.6, pp. 2609-2615, 2000.
Selahattin Sayil received his Ph.D. degree in Electrical Engineering from Vanderbilt University, TN, in 2000. He is currently an Associate Professor in Electrical Engineering at Lamar University. His current research interests include Interconnect Analysis, Soft Error Modeling and Mitigation. He is an Associate Editor of International Journal of Electronics. Sumanth R. Yeddula received his Master of Science Degree in Electrical Engineering from Lamar University in August 2012. His research areas include EEG analysis, Bio-medical Signal Processing, VLSI Design and modeling. He currently works for HTC Global Services as a consultant. Juyu Wang received her Master of Science Degree in Electrical Engineering from Lamar University in May 2010. Her research areas include Single Event Hardening, Leakage Power Optimization, and Carbon nanotube Interconnects. Direct questions and comments about this article to Selahattin Sayil, Department of Electrical Engineering, Lamar University, PO Box 10029, Beaumont, TX 77710; [email protected].
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