slides - EECS @ UMich
A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS David D. Wentzloff and Anantha P. Chandrakasan Massachusetts Institute of Technology Cambridge, MA ISSCC 2007
Motivation Energy/bit [J]
• Low-data rate, energy-constrained apps. 1μ 0.1μ
[ISSCC]
10n 1n
Trend: Data rate Energy/bit
0.1n 1k 10k 0.1M 1M 10M 0.1G 1G Data rate [b/s]
• Pulsed-UWB signaling inherently duty-cycled TX and RX on only when a pulse is present
Fast (2ns) turn-on time
System Specifications • PPM signaling with non-coherent receiver Data encoded in pulse position
Variable frame time 1
1
0
0
30ns
• Three channel frequency plan PSD
Each channel 550MHz wide Center frequency: 6000ppm 3.1GHz
Self-mixing receiver
5GHz
Relaxed RF tolerance
All-Digital Transmitter
Pulse Generation Principle • Use a tapped variable delay line and edge combiner to synthesize a pulse Positive Edge Combiner
…
Equivalent to… Pulse LO
Center frequency depends on delay
Single modulated pulse
Width depends on number of edges combined
Frequency selectivity without LO
Spectrum cSarbmlgin PSD [dBm/MHz]
10
Randomly modulated PPM signals have spectral lines
0 -10 -20
PPM+BPSK scrambling eliminates tones
-30 -40 0.8
0.9 1 1.1 Normalized Frequency
1.2
Conventional PPM+BPSK Data n pulse
Data n+1 pulse
Inverted pulse
Spectrum cSarbmlgin PSD [dBm/MHz]
10
Randomly modulated PPM signals have spectral lines
0 -10 -20
PPM+Delay-Based BPSK scrambling eliminates tones in the main lobe
-30 -40 0.8
0.9 1 1.1 Normalized Frequency
1.2
Proposed PPM+DB-BPSK Data n pulse
Data n+1 pulse
0.5TRF Delay
DB-BPSK: Minimal Overhead
Transmitter Block Diagram 32 stages, digital delay PRF
PRBS
Edge Selection
Mask edges to combiner
Feedback stage disabled when pulsing
30-Edge Combiner
Positive edge in
one RF pulse out
Digital Delay Stage 25f
50f
Full-swing signals
____ in[n] in[n]
6-bit current starving
in[n+1] 25f
50f
______ in[n+1]
R1[n] 2-bit cap bank
R2[n] PRBS
Overall ±30% variation in delay
8-bit delay control
Only selected edges are combined
Delay Line Calibration Configure delay line as a ring oscillator
fRING = fRF / 32 Measure frequency by counting ring cycles
8-bit control
C1 C0
I5
I4
I3
I2
I1
I0
Begin
Choose cap bank
4 banks
No
Yes
Choose next current bit
6 bits
Measure frequency
No
Last current bit?
Yes
Frequency in range?
Done
Delay Range and Accuracy Simulated RF Output Frequency [GHz]
6 5 4 3 2 1 0
FF 0
31 63
TT
SS
95 127 159 191 223 255 Digital Code
Delay Range and Accuracy Measured RF Output Calibration Accuracy
5
50
4
25
3
MHz
Frequency [GHz]
6
2 Measured RF and cal. output
1 0
0
31 63
95 127 159 191 223 255 Digital Code
0
-25 -50 0
31
63 95 127 159 191 Digital Code
Ring output is an accurate measure of pulse center frequency
30-Edge Combiner XOR combiner outputs
15-Edge Combiner 1
Interleaved 15-edge combiners
15-Edge Combiner 2 M2 A
x15
Edge to pulse
Masked edges
To pad driver
Q B M1
[Kim, JSSC ‘02]
M4 _ Q M3
Q _ Q Edge[1] Edge[2] A B
RF Pad Driver Linear-in-dB scaling
Weak pull-up
Off-chip
From edge combiner
_______ Standby
_______ Standby Stacked NMOS to g[1] g[2] g[7] reduce leakage 5
S11
S11 in Idle State
S11 [dB]
0 -5 -10 -15 -20
27% efficiency
1
2
3 4 Frequency [GHz]
5
6
DB-BPSK Implementation Per-stage delay is ½ RF period PRBS bit selects register
Mask values offset by 1 bit
R1 R2
2.5ns 650mV
PSD [dBm/MHz]
DB-BPSK Pulses
-25 -35
PPM + DB-BPSK Spectrum PPM
FCC Mask
-45 -55
PPM + DB-BPSK
-65 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 Frequency [GHz]
Measured Spectrum 3-Channel Spectrum
CH2 Gain Settings -40 PSD [dBm/MHz]
PSD [dBm/MHz]
-40 -50 -60 -70 -80
0
1
2 3 4 Frequency [GHz]
5
6
-45 -50 -55 -60 3.65 3.85 4.05 4.25 4.45 Frequency [GHz]
Technology
90nm CMOS
Active Area
0.2x0.4mm2
Modulation
PPM
Scrambling
DB-BPSK
Supply
1V
Leakage Power
96μW
Active E/pulse
37pJ/pulse
PRF Range
10kHz to 16.7MHz
Total E/bit
9.6nJ/bit to 43pJ/bit
0.8mm
Summary
0.8mm
• Energy consumed in sub-Vt leakage and CV 2 • Digital architecture practical for non-coherent RX Acknowledgements – MARCO/DARPA Focus Center for Circuit & System Solutions (C2S2), National Science Foundation (NSF), and STMicroelectronics for chip fabrication
Motivation Energy/bit [J]
• Low-data rate, energy-constrained apps. 1μ 0.1μ
[ISSCC]
10n 1n
Trend: Data rate Energy/bit
0.1n 1k 10k 0.1M 1M 10M 0.1G 1G Data rate [b/s]
• Pulsed-UWB signaling inherently duty-cycled TX and RX on only when a pulse is present
Fast (2ns) turn-on time
System Specifications • PPM signaling with non-coherent receiver Data encoded in pulse position
Variable frame time 1
1
0
0
30ns
• Three channel frequency plan PSD
Each channel 550MHz wide Center frequency: 6000ppm 3.1GHz
Self-mixing receiver
5GHz
Relaxed RF tolerance
All-Digital Transmitter
Pulse Generation Principle • Use a tapped variable delay line and edge combiner to synthesize a pulse Positive Edge Combiner
…
Equivalent to… Pulse LO
Center frequency depends on delay
Single modulated pulse
Width depends on number of edges combined
Frequency selectivity without LO
Spectrum cSarbmlgin PSD [dBm/MHz]
10
Randomly modulated PPM signals have spectral lines
0 -10 -20
PPM+BPSK scrambling eliminates tones
-30 -40 0.8
0.9 1 1.1 Normalized Frequency
1.2
Conventional PPM+BPSK Data n pulse
Data n+1 pulse
Inverted pulse
Spectrum cSarbmlgin PSD [dBm/MHz]
10
Randomly modulated PPM signals have spectral lines
0 -10 -20
PPM+Delay-Based BPSK scrambling eliminates tones in the main lobe
-30 -40 0.8
0.9 1 1.1 Normalized Frequency
1.2
Proposed PPM+DB-BPSK Data n pulse
Data n+1 pulse
0.5TRF Delay
DB-BPSK: Minimal Overhead
Transmitter Block Diagram 32 stages, digital delay PRF
PRBS
Edge Selection
Mask edges to combiner
Feedback stage disabled when pulsing
30-Edge Combiner
Positive edge in
one RF pulse out
Digital Delay Stage 25f
50f
Full-swing signals
____ in[n] in[n]
6-bit current starving
in[n+1] 25f
50f
______ in[n+1]
R1[n] 2-bit cap bank
R2[n] PRBS
Overall ±30% variation in delay
8-bit delay control
Only selected edges are combined
Delay Line Calibration Configure delay line as a ring oscillator
fRING = fRF / 32 Measure frequency by counting ring cycles
8-bit control
C1 C0
I5
I4
I3
I2
I1
I0
Begin
Choose cap bank
4 banks
No
Yes
Choose next current bit
6 bits
Measure frequency
No
Last current bit?
Yes
Frequency in range?
Done
Delay Range and Accuracy Simulated RF Output Frequency [GHz]
6 5 4 3 2 1 0
FF 0
31 63
TT
SS
95 127 159 191 223 255 Digital Code
Delay Range and Accuracy Measured RF Output Calibration Accuracy
5
50
4
25
3
MHz
Frequency [GHz]
6
2 Measured RF and cal. output
1 0
0
31 63
95 127 159 191 223 255 Digital Code
0
-25 -50 0
31
63 95 127 159 191 Digital Code
Ring output is an accurate measure of pulse center frequency
30-Edge Combiner XOR combiner outputs
15-Edge Combiner 1
Interleaved 15-edge combiners
15-Edge Combiner 2 M2 A
x15
Edge to pulse
Masked edges
To pad driver
Q B M1
[Kim, JSSC ‘02]
M4 _ Q M3
Q _ Q Edge[1] Edge[2] A B
RF Pad Driver Linear-in-dB scaling
Weak pull-up
Off-chip
From edge combiner
_______ Standby
_______ Standby Stacked NMOS to g[1] g[2] g[7] reduce leakage 5
S11
S11 in Idle State
S11 [dB]
0 -5 -10 -15 -20
27% efficiency
1
2
3 4 Frequency [GHz]
5
6
DB-BPSK Implementation Per-stage delay is ½ RF period PRBS bit selects register
Mask values offset by 1 bit
R1 R2
2.5ns 650mV
PSD [dBm/MHz]
DB-BPSK Pulses
-25 -35
PPM + DB-BPSK Spectrum PPM
FCC Mask
-45 -55
PPM + DB-BPSK
-65 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 Frequency [GHz]
Measured Spectrum 3-Channel Spectrum
CH2 Gain Settings -40 PSD [dBm/MHz]
PSD [dBm/MHz]
-40 -50 -60 -70 -80
0
1
2 3 4 Frequency [GHz]
5
6
-45 -50 -55 -60 3.65 3.85 4.05 4.25 4.45 Frequency [GHz]
Technology
90nm CMOS
Active Area
0.2x0.4mm2
Modulation
PPM
Scrambling
DB-BPSK
Supply
1V
Leakage Power
96μW
Active E/pulse
37pJ/pulse
PRF Range
10kHz to 16.7MHz
Total E/bit
9.6nJ/bit to 43pJ/bit
0.8mm
Summary
0.8mm
• Energy consumed in sub-Vt leakage and CV 2 • Digital architecture practical for non-coherent RX Acknowledgements – MARCO/DARPA Focus Center for Circuit & System Solutions (C2S2), National Science Foundation (NSF), and STMicroelectronics for chip fabrication
