slides - Microsystems Technology Laboratories - MIT
A CMOS-Compatible Fabrication Process for Scaled Self-Aligned InGaAs MOSFETs Jianqiang Lin Dimitri Antoniadis and Jesús del Alamo Microsystems Technology Laboratories, MIT CS MANTECH, May 18-21, 2015 Acknowledgements: DTRA NSF E3S STC MIT SMART program 1
Motivation for III-V CMOS • Superior electron transport properties for III-Vs Vinj: source injection velocity
• III-V’s: promising to extend Moore’s Law • Focus of this talk: InGaAs MOSFET fabrication technology 4
Self-aligned recessed-gate QW-MOSFET HEMTs
Considerations for III-V MOSFETs • Gate insulator – thin with low leakage, low Dit
• High-level self-alignment 2 m [Kim IEDM 2011]
– ohmic metal, access region, gate
• CMOS compatibility – free of wet-etch, lift-off and Au
Proposed MOSFET structure:
3
Process overview Mo/W ohmic contact
CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE
Resist SiO2 W/Mo n+ cap InP InGaAs/InAs -Si InAlAs
[Lin, APEX 2012] III-V recess
Gate stack
[Lin, IEDM 2013] [Waldron, IEDM 2007] Via and pad Via
Mo HfO2
[Lin, IEDM 2012-2014]
4
Details of contact and III-V recess processes Mo/W ohmic contact
CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE
Resist SiO2 W/Mo n+ cap InP InGaAs/InAs -Si InAlAs
[Lin, APEX 2012] III-V recess
Gate stack
[Lin, IEDM 2013] [Waldron, IEDM 2007] Via and pad Via
Mo HfO2
[Lin, IEDM 2012-2014]
5
W barrier for undercut immunity Goal: to reduce device footprint and gate pitch size Oxidized Mo SiO2 Mo
[Lin, IEDM 2012]
(a)
20 nm [Lin, IEDM 2012]
[Lin, IEDM 2013]
6
Problems with wet etch gate recess
• Isotropic wet etch → large lateral extent – Large footprint – Ungated and uncapped access regions → access resistance ↑ 7
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE
• Anisotropic
SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
-Si
8
III-V dry etch: surface roughness Selected chemistry Cl2:N2 Key parameters:
As-grown
Selected recipe
Bias Pressure Gas ratio (Cl2:N2) Gas chemistry
Not selected recipes
9 [Zhao EDL 2014]
III-V dry etch: trenching BCl3-chemistry
[Zhao IEDM 2014]
Cl2:N2-chemistry
Low bias
High bias
10
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE
• Anisotropic • Accurate depth control
SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
-Si
1 nm/cyc
Digital Etch (DE)
[Lin, EDL 2014]
O2 Plasma H2SO4
11
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
• Anisotropic • Accurate depth control • Accurate and fast calibration
-Si
1 nm/cyc
Digital Etch (DE)
[Lin, EDL 2014]
O2 Plasma H2SO4
12
Precise channel thickness (tc) control 1 nm depth control
tc=
tc=
ON-state: ION, gm, RSD OFF-state: S, DIBL, Vt roll-off [Lin, TED submitted]
800
DIBL (mV/V)
Device scaling study
tc=12 nm
600 400 200
3 nm
0 0.01
0.1
1 Lg(m)
10
13
Typical long-channel characteristics -3
10
-4
10 Id (A/m)
-5
10
-6
10
83 mV/dec
-7
10
-8
Lg=120 nm
10
Vds=0.05 and 0.5 V
-9
10
-0.2
0.0 0.2 Vgs (V)
0.4
• Steep S at low Vds → Low Dit • Jg< 10-2 A/cm2 at EOT~0.5 nm → gate leakage suppression (typical HEMT: Jg>100 A/cm2)
14
Scalability and performance Scalability
Performance
[Lin, IEDM 2014]
Id (mA/m)
3.1 mS/m 1.0 Lg=20 nm Vgs-Vt= 0.5 V 0.8 Ron=224 m 0.4 V 0.6 0.4 0.2 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Vds (V)
MIT MOSFETs Ref: del Alamo ESSDERC 2013 (updated)
15
Conclusions • Scalable self-aligned InGaAs MOSFETs – CMOS manufacturability, performance, scalability
• Bilayer ohmic contact for footprint scaling • III-V recess – III-V dry etch: smooth surface and no trenching – Digital etch: accurate depth control
• InGaAs MOSFET performance analysis – – – –
Steep subthreshold swing: low Dit Gate leakage suppression Record transconductance achieved Working Lg=20 nm InGaAs MOSFETs
16
Motivation for III-V CMOS • Superior electron transport properties for III-Vs Vinj: source injection velocity
• III-V’s: promising to extend Moore’s Law • Focus of this talk: InGaAs MOSFET fabrication technology 4
Self-aligned recessed-gate QW-MOSFET HEMTs
Considerations for III-V MOSFETs • Gate insulator – thin with low leakage, low Dit
• High-level self-alignment 2 m [Kim IEDM 2011]
– ohmic metal, access region, gate
• CMOS compatibility – free of wet-etch, lift-off and Au
Proposed MOSFET structure:
3
Process overview Mo/W ohmic contact
CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE
Resist SiO2 W/Mo n+ cap InP InGaAs/InAs -Si InAlAs
[Lin, APEX 2012] III-V recess
Gate stack
[Lin, IEDM 2013] [Waldron, IEDM 2007] Via and pad Via
Mo HfO2
[Lin, IEDM 2012-2014]
4
Details of contact and III-V recess processes Mo/W ohmic contact
CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE
Resist SiO2 W/Mo n+ cap InP InGaAs/InAs -Si InAlAs
[Lin, APEX 2012] III-V recess
Gate stack
[Lin, IEDM 2013] [Waldron, IEDM 2007] Via and pad Via
Mo HfO2
[Lin, IEDM 2012-2014]
5
W barrier for undercut immunity Goal: to reduce device footprint and gate pitch size Oxidized Mo SiO2 Mo
[Lin, IEDM 2012]
(a)
20 nm [Lin, IEDM 2012]
[Lin, IEDM 2013]
6
Problems with wet etch gate recess
• Isotropic wet etch → large lateral extent – Large footprint – Ungated and uncapped access regions → access resistance ↑ 7
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE
• Anisotropic
SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
-Si
8
III-V dry etch: surface roughness Selected chemistry Cl2:N2 Key parameters:
As-grown
Selected recipe
Bias Pressure Gas ratio (Cl2:N2) Gas chemistry
Not selected recipes
9 [Zhao EDL 2014]
III-V dry etch: trenching BCl3-chemistry
[Zhao IEDM 2014]
Cl2:N2-chemistry
Low bias
High bias
10
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE
• Anisotropic • Accurate depth control
SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
-Si
1 nm/cyc
Digital Etch (DE)
[Lin, EDL 2014]
O2 Plasma H2SO4
11
New III-V recess technology: Precise channel thickness (tc) control Cl2 anisotropic RIE SiO2 W/Mo n+ InGaAs/InP
InP
InGaAs/InAs InAlAs
• Anisotropic • Accurate depth control • Accurate and fast calibration
-Si
1 nm/cyc
Digital Etch (DE)
[Lin, EDL 2014]
O2 Plasma H2SO4
12
Precise channel thickness (tc) control 1 nm depth control
tc=
tc=
ON-state: ION, gm, RSD OFF-state: S, DIBL, Vt roll-off [Lin, TED submitted]
800
DIBL (mV/V)
Device scaling study
tc=12 nm
600 400 200
3 nm
0 0.01
0.1
1 Lg(m)
10
13
Typical long-channel characteristics -3
10
-4
10 Id (A/m)
-5
10
-6
10
83 mV/dec
-7
10
-8
Lg=120 nm
10
Vds=0.05 and 0.5 V
-9
10
-0.2
0.0 0.2 Vgs (V)
0.4
• Steep S at low Vds → Low Dit • Jg< 10-2 A/cm2 at EOT~0.5 nm → gate leakage suppression (typical HEMT: Jg>100 A/cm2)
14
Scalability and performance Scalability
Performance
[Lin, IEDM 2014]
Id (mA/m)
3.1 mS/m 1.0 Lg=20 nm Vgs-Vt= 0.5 V 0.8 Ron=224 m 0.4 V 0.6 0.4 0.2 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Vds (V)
MIT MOSFETs Ref: del Alamo ESSDERC 2013 (updated)
15
Conclusions • Scalable self-aligned InGaAs MOSFETs – CMOS manufacturability, performance, scalability
• Bilayer ohmic contact for footprint scaling • III-V recess – III-V dry etch: smooth surface and no trenching – Digital etch: accurate depth control
• InGaAs MOSFET performance analysis – – – –
Steep subthreshold swing: low Dit Gate leakage suppression Record transconductance achieved Working Lg=20 nm InGaAs MOSFETs
16
