Spur-Free Multirate All-Digital PLL for Mobile ... - Semantic Scholar

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 12, DECEMBER 2011

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS Robert Bogdan Staszewski, Fellow, IEEE, Khurram Waheed, Senior Member, IEEE, Fikret Dülger, Member, IEEE, and Oren E. Eliezer, Member, IEEE

Abstract—We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a 2 and consingle-chip GSM/EDGE RF-SoC. It occupies 0.35 sumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

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Index Terms—All-digital PLL (ADPLL), digitally-controlled oscillator (DCO), dithering, multirate signal processing, phase-locked loop (PLL), time-to-digital converter (TDC).

I. INTRODUCTION

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F phase/frequency modulation is an important part of today’s wireless systems. Virtually all high-volume commercial radios use modulation standards that involve phase modulation (PM) or its derivative, frequency modulation (FM). Some standards, such as Bluetooth Basic Data Rate (BDR) and Global System for Mobile Communications (GSM), communicate their digital information symbols entirely through FM.1 More advanced standards, such as Bluetooth Enhanced Data Rate (EDR), WCDMA and Long-Term Evolution (LTE) of the 3GPP cellular, employ complex-envelope or vector modulation, Manuscript received April 15, 2011; revised June 03, 2011; accepted July 15, 2011. Date of publication August 30, 2011; date of current version November 23, 2011. This paper was approved by Guest Editor Hooman Darabi. R. B. Staszewski is with Microelectronics Department/DIMES, Technische Universiteit Delft, The Netherlands (e-mail: [email protected]). K. Waheed is with Freescale Semiconductor, Austin, TX 78739 USA (e-mail: [email protected]). F. Dülger is with Texas Instruments, Dallas, TX 75243 USA (e-mail: fikret. [email protected]). O. E. Eliezer is with Xtendwave, Dallas TX 75254 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2011.2162769 1Bluetooth uses Gaussian frequency shift keying (GFSK) whereas GSM uses Gaussian minimum shift keying (GMSK) with the modulation index h of 0.32 and 0.5, respectively. The modulation index defines the maximum frequency deviation f from the carrier center frequency f : f h= =T , where T is the symbol period.

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= ( 2)(1 )

in which the PM/FM may be regarded as an orthogonal component to the amplitude modulation (AM). As such, any complex signal transmitter could be realized with the orthogonal PM/FM and AM paths. By manipulating the complex signal trajectory, the WCDMA modulation range could be substantially compressed to the point that it might be handled by an EDGE polar transmitter [1]. The : frequency as a effort of compressing the FM ( derivative of phase) and AM ( : amplitude) signal components sigis of great interest due to the fact that converting the nals from the native Cartesian complex number representation into the equivalent and representation results in a significant bandwidth expansion as a result of the following non-linear and . transformations: The delay mismatch analysis between FM and AM paths was presented in [2]. Theoretical performance analysis of a discretetime RF polar transmitter and the general effect of mismatches between the FM and AM paths was carried out in [3]. Until a few years ago, virtually all high-performance phaselocked loops (PLLs) were based on a charge-pump architecture [4]. This architecture, shown in Fig. 1(a), owes its popularity to the relative simplicity and ease of meeting even the most demanding performance requirements. The timing difference between the frequency reference (FREF) and closest down-divided VCO output edges is estimated by the phase/frequency detector that outputs rail-to-rail UP and DOWN pulses . Index with a duty cycle (i.e., duration) proportional to variable represents significant (rising or falling) edges of the FREF clock and denotes the discrete-time domain of the PLL operation. The UP and DOWN pulses produce either positive or negative, respectively, current pulses by the charge pump current sources, which get integrated and filtered by the loop filter. The output of the loop filter controls the VCO frequency through a tuning voltage. The loop operates in a negative feedis forced to zero.2 Since freback manner such that quency is a time differentiation of phase, the variable output will precisely follow the reference frequency frequency according to , where FCW is a frequency command word. Despite the apparent simplicity, the traditional charge-pump PLL of Fig. 1(a) shows signs of breaking down when attempted in a nanoscale CMOS technology, especially as part of a system-on-chip (SoC). Due to the low supply voltage constraint of MOS transistors, the and poor drain dynamic resistance 2It is ensured by so-called type-II configuration, which introduces a pole at dc by virtue of the ideal current source and capacitor. Type-I configuration is also possible, in which case t k will go to some non-zero value proportional to the VCO frequency deviation from its center.

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STASZEWSKI et al.: SPUR-FREE MULTIRATE ALL-DIGITAL PLL FOR MOBILE PHONES IN 65 NM CMOS

Fig. 1. PLL types: (a) conventional charge-pump PLL; (b) all-digital PLL. For comparison sake, (a) is drawn in the fractional- configuration.

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current sources are now far from ideal. Due to the MOS gate leakage, it is difficult to use high-density MOS varactors but on-chip metal-to-metal capacitors consume large area. While external capacitors are typically acceptable in low-complexity ICs, more sophisticated SoCs would not tolerate the associated extra I/O interface, routing and signal integrity degradations. Furthermore, ensuring wide linear tuning range of a VCO is very difficult in low-voltage technologies [5]. Consequently, the traditional charge-pump PLL architecture has not only issues with the scaled CMOS technology but, in addition, is limited in its ability to effectively perform wideband frequency modulation. The most obvious attempt of FM would be to add the dynamic data modulation to the semi-static channel FCW. Unfortunately, this type of PLL has rather a very limited bandwidth, thus severely restricting the FM data rate. A method to increase the data rate by compensating for the PLL loop high frequency attenuation through boosting the high frequency components of the modulation signal was proposed in [6]. That architecture, however, requires precise matching between the digital precompensation filter and the analog PLL transfer function across process and temperature variations. The all-digital PLL (ADPLL) architecture, shown in Fig. 1(b), was conceived [5], [7] to not only address the above implementational issues but also to add flexibility, reconfigurability and transfer-function precision in order to meet the diverse and strict requirements of advanced communication systems. At the fundamental level, the ADPLL operates in the true phase domain by comparing the variable phase of the multi-GHz digitally-controlled oscillator (DCO) with the reference phase of the lower-frequency (e.g., 8–40 MHz) FREF clock of high long-term precision. The comparison result is a digital phase which, after filtering by the digital loop filter, adjusts error the DCO frequency in the negative feedback manner. From the implementational point of view, the architecture of Fig. 1(b) can be considered a digital equivalent of Fig. 1(a), where the dithering of the smallest VCO is replaced by the DCO with binary (i.e., 2-state) varactors, the phase/frequency detector and charge pump combination is replaced by the time-to-digital

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converter (TDC) with normalization of its quantization step, and the analog loop filter is replaced by the digital loop filter. From the very beginning, the ease at which the ADPLL could perform frequency modulation has been exploited to not only generate a continuous wave (CW) RF carrier of high purity but also to perform accurate and relative wideband data modulation that is not restricted by the loop bandwidth. This experience has been ported to commercial products of ever increasing complexity to realize all-digital implementations of RF transmitters that are amenable to SoC integration in nanoscale CMOS processes. They have been commercially realized for Bluetooth [8], GSM/EDGE [9]–[11] and WCDMA [12]. The ADPLL is nowadays a subject of intensive research in academia and industry, and many independent realizations have been published, including [13]–[25]. One potential weakness of the ADPLL, however, is that the TDC and DCO quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase noise increase. As such, finite TDC resolution can distort data modulation and spectral mask at near integer- channels, while the finite DCO step size can add far-out spurs and phase noise. Also, a major underreported issue is an injection pulling of the DCO due to a digital activity producing harmonic frequencies nearby the DCO resonant frequency, which can also create spurs. This work addresses all these problems and demonstrates RF performance, which matches and exceeds that of the best-in-class traditional approaches. In this paper, we present an evolution of the ADPLL architecture to meet the ever-increasing requirements of lower area and power consumption, improved phase noise and spurious tones, reduced modulation distortion and increased modulation bandwidth. In Section II, we propose a multirate ADPLL operation, in which the frequency modulation data samples operate at a high rate obtained by a low integer division of the RF oscillator clock, which is independent from the phase detection rate at the reference frequency. In Section III, we describe problems associated with the finite resolution of the TDC conversion function as well as coupling issues that result in spurs. Two solutions to these problems are then offered. Section IV proposes a noise-free dithering scheme for the reference frequency clock. An offset ADPLL architecture that performs frequency translation of the feedback clock is proposed in Section V. Implementation and measurement results are presented in Section VI. II. EVOLUTION TOWARDS MULTIRATE ADPLL ARCHITECTURE A. Digital-to-Frequency Converter 1) Ideal DFC: Ideal representation of a digital-to-frequency converter (DFC) is shown in Fig. 2. It accepts a frequency command word (FCW) of discrete-time index , and produces a digital clock with a continuous-time frequency deviation away from the center frequency . The output frequency change is assumed instantaneous. The conversion gain is the slope of the input-output transfer function. It is desired that the value be constant and known precisely. 2) Open-Loop Digital-to-Frequency Converter: A straightforward digital implementation of the DFC could be the one

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Fig. 2. Ideal digital-to-frequency converter (DFC). It should be noted that the subscript ’V ’ is a little misnomer here, since there is no “variable” clock in the sense of the feedback adjustment. It is kept here for the sake of continuity of the developmental progression.

Fig. 4. RF digital-to-frequency converter (DFC) realized using a digitally-controlled oscillator (DCO). The DCO has a normalized gain of f =LSB, which is [Hz/LSB] by f =K [unitachieved by multiplying the actual gain K less], where the hat operator denotes the estimate.

Fig. 3. Open-loop fractional edge divider.

shown in Fig. 3. It is almost identical to a phase accumulator in the well-known direct digital frequency synthesizer (DDFS). It outputs a digital clock, CLK2, but requires a higher-frequency clock, CLK1. It is an open-loop clock edge divider ) that accumulates FCW and outputs (i.e., its most significant bit (MSB)3 as CLK2. The time-averaged division ratio is an inverse of the FCW. The FCW format is a fixed-point number with the radix point being just above the MSB. For example, FCW binary code of “11000…” means , so the average division ratio is 4/3. Except for the simple negative power-of-two numbers, all other FCW values produce instantaneous division ratio that is somewhat different from the average division ratio, thus resulting in quantization jitter. A closely related DFC is so-called “flying-adder” [26], [27], which accepts an input clock with multiple phases and switches between the phases so as to minimize the amount of jitter. B. ADPLL-Based Frequency Modulator While the digital DFC of Fig. 3 finds numerous uses at lower baseband frequencies, it is quite impractical at higher RF frequencies due to the larger amount of quantization jitter and the requirement that the CLK1 input clock be of significantly higher frequency than twice the desired output frequency. Consequently, a new DFC architecture shown in Fig. 4 has been proposed [5], [7] for RF wireless applications that require low spurious tones and phase noise (RF equivalent of jitter) as well as low power consumption. The new architecture is based on a digitally-controlled oscillator (DCO). Unfortunately, the free-running DCO would invariably exhibit wander or random walk of its phase with the expected variance approaching infinity. Therefore, the DCO requires adjustment of its slowly varying wander (lower frequency components of its phase noise) with the stable frequency reference (FREF). The adjustments are obtained by forming a negative-feedback loop around the DCO. The higher frequency components of the phase noise, which are beyond the loop bandwidth, will not be cancelled. However, 3Alternatively, a carry-out could be used as an output clock with short pulse duration.

these components of a typical LC-tank oscillator are made sufficiently low. The negative feedback is built using an all-digital phase-locked loop (ADPLL) architecture [7]. It comprises a time-to-digital converter (TDC) to estimate the variable phase, an FCW accumulator to calculate the reference phase, an arithmetic subtractor to calculate the phase error based on the reference phase and variable phase, and a digital loop filter to control the ADPLL bandwidth and transfer function characteristics. The ADPLL has a natural wideband FM capability. It is realized as a two-point modulation scheme [28]–[30]. One feed directly modulates the DCO, while the other feed is compensating and prevents the modulating data from affecting the phase error. The former path has highpass, whereas the latter path has lowpass filtering characteristics. Both of them properly combined (exact delay alignment) create all-pass transfer function characteristics. It should be emphasized, that due to the digital nature, the modulating paths enjoy the clock-cycle precision, which is guaranteed by constraint over the process, voltage and tempera). The DCO response speed is limited by the of the ture ( varactors, which is on the order of 100 of GHz. Consequently, in contrast to the traditional analog-intensive implementations of polar transmitters, the various data paths do not need to be calibrated. For the two-point modulation scheme to work properly, the in units DCO needs to have a normalized gain is the frequency of the reference clock. of [Hz/LSB], where is relatively straightforward in the ADPLL Estimating [28], [29] and normalizing it to would merely require a digital multiplier operating on its tuning input. If the normalization is exact, the modulating transfer function is flat in -domain and has only a sinc-type response from dc to in s-domain caused by the DCO zero-order hold interface [3]. normalization error on the ADPLL The effect of the transfer functions has been analyzed in [28]–[30] — the latter reference offers the most details and insight. The absence of continuous-time filtering results in signal replicas at multiplies ), as shown in Fig. 5. of the sampling rate (here, The DCO is a highly-linear replacement of the traditional VCO. The fine frequency resolution is achieved by dithering of its finest unit-weighted variable capacitors (varactors) using the high-speed down-divided DCO clock, as shown in Fig. 6. The tuning word is a fixed-point number with the integer part directly controlling the number of active

STASZEWSKI et al.: SPUR-FREE MULTIRATE ALL-DIGITAL PLL FOR MOBILE PHONES IN 65 NM CMOS

Fig. 5. Spectral replicas of a discrete-time FM signal and their filtering by the ZOH.

Fig. 6. Actual realization of the DCO with resolution improvement through a 61 modulator clocked by the down-divided DCO output clock.

Fig. 7. Multirate DFC capable of accommodating modulation sampling rates higher than the FREF.

unit-weighted binary-controlled varactors. The fractional part is fed to the modulator, which produces an integer stream whose average value is equal to that of the fractional input. dithering clock rate for GSM/EDGE transThe preferred ) in order to mitters is typically over 200 MHz (e.g., spread the quantization noise, due to the limited resolution, over sufficient frequency range. Non-cellular transmitters typically have some additional constraints, such as coexistence with a or 8, does cellular host system. For example, using not work well for the Bluetooth 2.4 GHz carrier, since the replica energy could fall into the 1.8 GHz cellular modulator at the rate avoids this band. Running the problem. Since the modulating samples are clocked at , the ADPLL . The of Fig. 4 cannot handle the frequency content over FREF clock oscillator typically uses a resonating crystal slab, whose maximum frequency of around 80 MHz is physically limited by its minimum thickness. Other types of FREF resonators, such as RC- and MEMS-based are not yet mature enough to replace the decades-old proven crystal-based solutions. To make and further push the the data sampling rate independent from replicas’ energy beyond any protected frequency band, the new multirate architecture of Fig. 7 is proposed. The phase error detecting and filtering part of the ADPLL still rate. This is natural since the FREF clock is the only runs at

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source here that provides the long-term super-stable timing reference to correct the slowly drifting DCO phase. Performing the phase error operations at a higher rate would not make sense4. The phase error samples are filtered and upsampled to the rate, where is the variable frequency of the DCO and is a small integer (preferably a power-of-two number). They are then merged with the modulating data of the same rate.5 The bandwidth could be as high as 100s modulating data of MHz thus easily covering the most demanding modulation 20 MHz channel bandwidth. standards, such as LTE with signal conversion into and polar compoNote that the nents significantly expands the bandwidth [3], but techniques, such as [1], could be used to address that effect. The two functional parts of the ADPLL-based frequency modulator: the phase error calculator and data modulator, have their own separate clock domains: FREF and CKV, respectively. Since their frequency relationship is a time-variant fractional number, their mutual interfaces require sampling rate converters (SRC). The SRC for the phase error is either zero-order hold (ZOH) or first-order (i.e., linear) interpolator, clock rate ratio and the level of depending on the the targeted performance. The compensating path, on the other hand, can be as simple as the ZOH, which is mainly due to the low-pass transfer function of the reference phase accumulator. can be easily realized The DCO clock edge divider by with low power consumption using static CMOS dividers in scaled CMOS technology. The second DCO divider shown in Fig. 7 is fractional, and could be implemented according to the topology shown in Fig. 3. Its purpose is to produce a stable ) clock or its integer multiple for the purpose symbol-rate ( of symbol-rate processing and pulse-shape filtering. Note that the modulating data rate in Fig. 7 is channel dependent, and also has a second-order dependency on its instantaneous frequency deviation. However, maintaining a harmonic relationship between the modulating clock rate and the DCO resonant frequency is highly beneficial to avoid injection pulling spurs [31]. The symbol rate processing in the digital baseband and the pulse-shape filtering, on the other hand, are preferably implemented in the fixed-frequency clock domain (integer multiple of the symbol rate) that is channel-independent. It implies that the FCW fractional number to the divider shown in Fig. 3 must be channel dependent with possible dependency (in case it is significant) on the instantaneous frequency deviation. C. Frequency Modulator Within an All-Digital Polar Transmitter Fig. 8 demonstrates the use of the above principles of multirate ADPLL-based frequency modulator to realize an all-digital polar transmitter for wireless applications. It is based on the architecture shown in Fig. 7 with added details from Figs. 3 and 6, as well as a crystal oscillator (XO) with a dither control, a difference-mode phase detector [9], back-end digital transmit modulator and a digital power amplifier (DPA)-based amplitude mod4Unless the FREF signal is a continuous-time signal, which could be further oversampled to get more timing information. 5Alternatively, the phase error rate could be an integer times slower than the modulating data rate for easy recombining before feeding it to the DCO.

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Fig. 8. Implementational block diagram of an EDGE polar transmitter based on the multirate DFC with three clock domains: FREF (f ), CKV (f =N ) and CKS (1=T : symbol rate).

ulator (AM). The low-band (LB) carrier is obtained by edge-dividing by two the CKV clock of the high-band (HB) carrier. The DPAs for HB and LB are separate. In addition to the two clock domains in Fig. 7, a third CKS clock domain is introduced that is of fixed frequency related to the symbol rate and independent from FREF. The multirate ADPLL architecture features support of modulating samples of much higher rate than the reference clock. In fact, FREF does not play any role in the data modulation. Consequently, the XO could be free-running and the reference frequency adjustment is performed through FCW. The CKV/16 clock is used to obtain the channel-frequency-independent rate through a fractional clock edge division. It clocks the digital back-end transmit pulse-shape filtering at a clock path circuits that perform the symbol rate. The rate that is an integer multiple of the COordinate Rotation by DIgital Computer (CORDIC) conversion into the and polar representation is also performed at that rate. An additional SRC circuit converts the symbol-related sampling frequency into the channel-frequency-dependent rate in order to properly interface with the DCO and bandwidth is much wider DPA. For other standards, whose than that of EDGE, it might be beneficial to place the CORDIC after the SRC. The CORDIC is an iterative algorithm with internal operations running at 8–16 higher rate. Generating that internal CORDIC clock might be more beneficial if a simple division of the DCO clock were used. samples at FREF rate get converted to The phase error channel-dependent CKV/16 rate by the sample-rate converter (SRC) and merged with the modulating samples of the same modurate. The fractional bits get further dithered by the lator operating at CKV/8 rate. This way, the injection pulling spurs of the prior implementations [8], [9], with the input at modulator CKV/8 clock is furFREF rate, are avoided. The

) to obtain the CKV/16 clock ther divided by two (i.e., in Fig. 8), which is used by the (i.e., digital front-end of the FM and AM paths. Referring to Fig. 5, rate or 110–125 MHz is bethe first replica at yond the protected receive low band and only needs to meet the relatively-relaxed FCC requirements. The CKV/16 clock is also used as the interpolated sampling rate of the phase error corrections. The single DCO gain-normalization multiplier of the prior implementations [8], [9], whose purpose is to normalize the transfer function of the DCO to the reference and thus make it independent from the process, frequency ) variations, gets split into two voltage and temperature ( parts: a fine precision multiplier in the data modulation path . and a coarse multiplier (right bit shift) of the filtered While the fine DCO transfer function precision (e.g., 0.5–5%, depending on the modulation standard and loop bandwidth) is needed for the distortion-free modulation [28], [29], [3], only a rough approximation of it (e.g., 5–25%) would be required to establish an acceptable range for the closed-loop ADPLL bandwidth. The PLL loop bandwidth affects mainly the settling time and the noise rejection, so a 5–25% variation in it would have minimal effect on the system performance. It should be samemphasized that the error in the normalization of the ples is quite benign since it uniformly expands or contracts all the zero and pole locations of the ADPLL closed-loop transfer function. multiplier is beneficial for sevThe split of the eral reasons. First, the accurate, hence complex, multiplier is no longer present within the ADPLL loop. Only a trivial multiplier of short computational delay is needed there. Hence, it will not affect the ADPLL loop delay, which could worsen the phase margin in case of a wide bandwidth operation. The accu-

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rate multiplier now is only required in the feedforward transmit path, so adding pipelining delay stages should have no consequence on the system performance. Second, the multiplier adjustment can now be performed anytime during the data transmission. This would not be possible in the prior arsamchitectures without making hits or perturbations. The ples after the loop filter typically have a large dc component (this is independent of the loop type), so changing the multiplier value will produce an instant change to the DCO tuning word, thus creating sudden frequency deviation steps. The normalization adjustment of the DCO gain during data modulation could be beneficial for faster settling, but it is necessary in case of a full-duplex operation, such as in CDMA, which allows no time for off-line adjustments.

D. Phase Detector in the Multirate ADPLL The ADPLL of Fig. 8 operates in the phase domain as folis obtained by lows: The integer part of the variable phase sampling, on FREF clock, the current count of the DCO clock edges. The fractional part of the variable phase is obtained from the TDC-based interpolator, whose norsignifies the position of the FREF edge malized output with respect to the two neighboring DCO edges. The integer and fractional parts are added together to form the fixed-point vari. The phase error is obtained by able phase subtracting the differentiated variable phase from FCW and integrating the result. The direct calculation of the reference phase is not needed in this case. This difference form of the phase detection produces almost identical results as the original direct form [8], in which the phase error was directly calculated as . The only difference between these two forms is an arbitrary integration constant of the difference form. (Mathematically, integration following differentiation is a unity operation except for the integration constant .) This has a consequence of an arbitrary phase shift between FREF and CKV even for the type-II ADPLL configuration. However, since the ADPLL typically operates in a non-integer- configuration, and the absolute phase of the communication path is never relied upon anyway, this effect is immaterial. The practical benefits, however, are substantial. The differential form of the phase detector allows to “freeze” the time and to stop ramping the phase error, which is found useful during expected external perturbations, such as power amplifier (PA) ramp, a digital baseband (DBB) clock switchover or an external FLASH memory access. Since the phase error is an integral of the frequency error, a generally non-zero frequency error (e.g., during settling) will results in a local ramp of the phase error. Freezing the loop in order to avoid reaction to a transient, but known, perturbation is non-trivial in case of the direct-form phase detector. However, it only requires zeroing out the input of the final accumulator (i.e., frequency error) of the differential-form phase detector. This feature was frequently relied upon during the field operation of the presented architecture, and also in solving the self-interference problem presented in [35].

Fig. 9. Block diagram of the TDC and FREF retiming circuitry.

E. Reference Clock Retiming The ADPLL is fundamentally a digital system with two clocks, FREF and CKV, which are not entirely synchronous to each other, especially when the strict integer- frequency relationship is not maintained. Consequently, a great care must be used to avoid metastability, which can happen when clocking the signals originating from other clock domains. The solution is to retime FREF by CKV [8] to obtain the retimed FREF clock, CKR, in order to use it to process the signals operating at the FREF rate. This way, the digital signal handover between the CKR and CKV will be seamless. The retimed FREF clock, CKR, which is used for the generation and filtering (see Fig. 8), is obtained in a metastability-free manner by speculative resampling of FREF by the rising and falling DCO clock edges, and using the path (CKR_P or CKR_N), which is farther away from metastability, based on the arbitration signal SEL_EDGE from the TDC. This is illustrated in Fig. 9. The arbitration signal is simply an FREF-sampled tapped delay of a quarter of the DCO period. A similar speculative mechanism is used for 3 LSB bits of the variable that are counted asynchronously in a carry-ripple phase manner. Finally, the LSB bits of get merged with 5 MSB , which is based on a synchronous counter. This new bits of method of speculative sampling of the variable phase saves a significant amount of current in comparison with the straightforward approach [8], [9], whose critical timing path is very tight. A careful analysis has been performed on the Fig. 9 circuit metastability behavior. It involved finding a metastability window and resolution parameters through long SPICE simulations according to the method described in [32]. The result of this analysis revealed that the mean-time between failures corner to be on the (MTBF) of the system at the worst order of billions of years. Fig. 10 illustrates the conceptual details of the FREF retiming principle. The FREF clock is resampled by the rising and falling

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edges of the CKV clock to produce the QP and QN signals, respectively. These signals are then delayed by at least a quarter ) to produce two CKR of the DCO clock period (i.e., candidates: CKR_P and CKR_N. One of these candidates is guaranteed to be free from metastability. The selection is done by the arbiter signal SEL_EDGE, which is obtained by sampling delayed CKV clock by the FREF clock. In practice, the the arbiter signal would simply be a programmable TDC tap roughly corresponding to the delay. If the output rising edge of the delayed CKV clock appears after the rising edge of FREF, then the FREF reclocked by the falling edge of CKV is chosen, as shown at the top timing diagram of Fig. 10(b). The bottom timing diagram of Fig. 10(b) corresponds to the opposite situation. The delayed CKV clock has its rising edge before the FREF rising edge. In this case, FREF will be retimed by the rising CKV edge, since retiming it on the falling edge of CKV might result in metastability. A special case corresponds to the timing when the arbiter signal is aligned with FREF. In might exhibit the metastability itself. However, this case, as long as the flip-flop (FF) output has a valid logic level, the actual value (logic high or low) does not matter, since both ) of the QP and QN candidates are sufficiently away ( from the metastability condition. Certain FFs, such as the current-amplifier-biased FF described in [33], have the property of maintaining a valid output logic level even during the metastability resolution phase. The QP and QN delay described above is needed to maintain the approximate FREF rising edge timing while waiting for the arbiter signal. In the prior straightforward implementations, the delay was achieved by retiming the QP and QN signals through flip-flops. It is to be noted that other FREF retiming methods also exist, such as the sampler-based counter method in [25], although its hardware complexity is higher.

Fig. 10. Details of the FREF retiming principle.

III. SPURIOUS TONE ISSUES A. TDC Finite Resolution An undesirable consequence of finite-resolution converting functions is the introduction of quantization noise. As such, as shown in Fig. 11, the TDC produces a decoded digital integer proportional to the timing difference between the significant (rising or falling) edges of the reference clock (FREF) of freand variable clock (CKV) of frequency , but with quency a certain quantization: (1) where and are significant edge timestamps of the referis the TDC timing ence and variable clocks, respectively, resolution, and “round” is the quantizing operation of rounding to the next (or, alternatively, previous) integer. This sample-andquantize operation in time domain is identical in principle to the common analog-to-digital conversion (ADC), with the Fig. 11 structure closely resembling that of a flash ADC. Hence, a TDC could be considered a special case of an ADC, where “ ” stands for the analog quantity of time.

Fig. 11. TDC: simplified schematic view (top); signal timing (bottom). The raw output is converted into a binary word represented as t . The delay elements are realized as inverters but shown as non-inverting buffers for simplicity.

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The TDC quantization of the phase error estimation affects the phase noise at the ADPLL output. Under the large signal assumption (spanning multiple quantization levels), the variance . The or power of the timing uncertainty is:

STASZEWSKI et al.: SPUR-FREE MULTIRATE ALL-DIGITAL PLL FOR MOBILE PHONES IN 65 NM CMOS

Fig. 12. Typical phase noise (PN) spectrum of the ADPLL output. The close-in phase noise is dominated by the TDC quantization noise (except for the 1=f noise portion of the crystal oscillator at the lowest frequencies).

phase noise is obtained by normalizing the standard deviation ) of the timing error to the unit interval (CKV clock period and multiplying by radians: . The total phase noise power is uniformly spread over the span from dc to the Nyquist frequency. The single-sided spectral density is, there. Since the close-in transfer funcfore, expressed as tion from the TDC to the ADPLL RF output is unity within the loop bandwidth (and then decays with the attenuation of the loop filter, as shown in Fig. 12), the close-in phase noise spectrum at the output due to the TDC timing quantization is (2) Substituting (absolutely worst case, even for , , the 130 nm CMOS node [8]), , we obtain with a 0–100 kHz integrated phase noise of 0.49 , which is adequate even for GSM applications. Typical worst-case resolution ranges, as achieved in [8]–[10], and are obtained merely through the are fine lithography and excellent device matching of the advanced CMOS fabrication process with no particularly special design or layout techniques. In fact, due to project’s time constraints, the TDC in [5] was described in the structural-style VHDL hardware description language. Then, the synthesized logic gates were auto-placed and auto-routed. The fabricated IC RF performance met the Bluetooth specifications with margin. Fig. 11 illustrates an example of the structural regularity and hardware simplicity. The actual implementation is similar to [34] and uses two inverter chains generating delayed complementary signals feeding sense-amplifier flip-flops with complementary inputs is very close to the [33]. This way, the TDC resolution of an inverter, which is the fastest intrinsic (loaded) delay possible regenerative delay in a CMOS technology. Equation (2) reveals that the TDC phase noise contribution could be further minimized by improving the TDC timing resolution and increasing the sampling rate. Next generations of nanoscale CMOS processes can only bring reductions in at a scaling rate of 0.7 with each CMOS node, such that the worst case of 10 ps could now be attained at a typical nominal-leakage 40 nm CMOS node. For the same conditions as above, this produces a PN plateau of -103.9 dBc/Hz and a 0–100 kHz integrated phase noise of only 0.16 . B. TDC Resolution Quality Problems The typical TDC resolution values obtained in a scaled CMOS technology are fine enough to generally guarantee

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mobile phone quality of RF transmit and receive operations. However, (2), describing the effect of the TDC resolution on the ADPLL phase noise, is only valid under the “large signal” assumption in which the timing difference between the FREF and CKV clock edges continually exercises different quantization levels. This assumption generally holds and only a very small fraction of the RF channels would exhibit an ill-conditioned frequency relationship in which the quantization energy does not satisfy the white-noise assumption and can produce performance degradation worse than expected from the well-behaved distribution. For example, in near integerchannels ( ), at which the fractional part of the FCW is close to zero (but not exactly zero), the quantization energy of the TDC is mostly concentrated in tones close to dc. This condition of very close proximity to the integerfrequency multiplication can be either static (in case of CW or no modulation) or dynamic, in which the FCW, due to data modulation, can instantaneously come very close to an integer. The direct ADPLL frequency modulation causes, therefore, a continuous shift of these tones in correspondence to the modulation commands, and the damaging effect would depend on the statistics of the modulating FCW. These low-frequency tones, if they fall within the pass-band of the PLL, cannot be attenuated by the loop filter and, consequently, they modulate the DCO output, thus distorting the intended modulation. If the spurious tones fall between 300–700 kHz, then they affect the narrow-band spectrum mask, potentially exceeding the limits defined for GSM/EDGE transmitters. Similar parasitic DCO modulation for an ADPLL-based GMSK transmitter operating at integer- channels is explained in [35]. The detailed nature of the ill-behaved spurious tones is analyzed in [36]. An example phase error trajectory of the ill-behaved near-integer- condition is shown in Fig. 13. The output frequency is 1742.02 MHz ( ), which corresponds to with the reference frequency . The generated frequency lies 20 kHz away [i.e., at , where is the floor operation of ] from the integer- channel center frequency. The TDC resolution is 20 ps. It corresponds to the normalized phase , which is displayed as error value of the distance between the two dotted horizontal lines. If the TDC were missing (i.e., the ADPLL phase resolution falls back to due to existence of the variable phase counter and sampler ) then the repetition frequency of the sawtooth trajectory would be the same as the 20 kHz separation to the integerchannel. The fine TDC resolution increases the sawtooth trato 574 kHz jectory frequency by according to (3)

(3) Incidentally, the finer TDC resolution not only reduces the total power of the quantization noise, but also advantageously moves it away towards higher frequencies, where they could be easier filtered out. As such, improving the TDC resolution by a factor of two not only places the spurious tones at double their original frequency (possibly moving them

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Fig. 14. Subharmonic coupling of the generated RF signal into the crystal oscillator.

C. Parasitic Spurs

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Fig. 13. Phase error trajectory of an near-integer- condition (FCW = 67:000769). The raw phase error is in red; the filtered (3-dB loop bandwidth is about 60 kHz) phase error is in black. The two horizontal dotted line are separated by an equivalent inverter delay.

outside the loop filter cutoff frequency) but also reduces their pre-filtering power by 6 dB. The phase error trajectory of Fig. 13 also visibly contains other tonal frequencies. A more thorough analysis of the TDC spectral content was carried out in [36]. It is to be noted that although the phase error tones are beyond the 3-dB loop filter cutoff frequency, their energy is still significant enough to modulate the DCO, resulting in undesired spurs that are intolerable both in transmission and reception modes. The more obvious solution to the ill-conditioned TDC behavior would be to reduce the total quantization noise power by improving the basic TDC resolution beyond the fundamental technology limitation established by the most stable regenerative delay in CMOS, i.e., the inverter delay. Unfortunately, this approach typically involves significant design challenges and increased area and power consumption. The published approaches include: TDC with fractional resolution [13], noise-shaped TDC [16], TDC with precise calibration and mismatch correction as well as clock doubler [17], TDC with time amplification [18], and TDC with doubling the resolution through additional row of flip-flop registers operating on a delayed clock [37]. The approach we have chosen, however, is to stay with the intrinsic unit delay of a string of inverters, which according to (2), appears sufficient for a properly designed system. The ill-conditioned behavior that violates (2) assumptions is alleviated by either of the two proposed solutions: 1) noise-free dithering of the FREF clock [38] by forcing the TDC input to frequently cross multiple quantization levels; 2) frequency translation of the RF oscillator through cyclic rotation between its quadrature phases [39] in order to selectively move away from the integer- relationship. These two solutions are realized with much greater simplicity in comparison with those cited above, which improve the TDC resolution beyond the intrinsic inverter delay. They also avoid any modifications to the core TDC circuitry. This is all in accordance with the philosophy of keeping the critical “analog part” (here the continuous-time processing elements) to a minimum, while compensating the remaining analog imperfections in the ”digital domain” (i.e., digital assistance of RF), as advocated in [40].

A certain class of coupling spurs, which were found particularly troublesome, were described in detail in [35] for another ADPLL-based transmitter. The coupling mechanism is as follows (see Fig. 14): The FM/PM modulated RF clock on the feedback path to the TDC (i.e., the aggressor) gets parasitically coupled into the slicer input (i.e., the victim) of the FREF crystal oscillator (XO). By means of subharmonic modulation of the sinusoidal FREF oscillator waveform, jitter is created on the FREF digital clock. The coupling mechanism creates significant distortion of the modulated RF waveform at the integerchannels (i.e., when the instantaneous FCW is very close to integer). The jitter energy passes through the low-pass loop filter and modulates the DCO. Due to the relentless push towards integration and continued reduction of device feature size, this class of spurs is likely to become even more prevalent in the near future. Fortunately, the above mentioned mitigation techniques of the near-integer- condition of the feedback clock have been found reasonably effective in combating it. D. Injection Pulling Fig. 15 reveals a technique to lower spurs due to injection pulling. They are likely to happen when the higher harmonic of the digital baseband (DBB) clock falls in the vicinity of the DCO LC-tank resonant frequency. The coupling mechanism could be magnetic (DCO inductor, bondwires), capacitative (long parallel wires), through the substrate, through ground/supply common IR drop, etc. The injection-pulling force gets reduced when the DCO itself is used to clock the DBB, rather than the accompanying PLL. Consequently, by switching the source of the DBB clocks to that generated by instantaneously-integer clock edge division of the DCO output, as shown in Fig. 16, the massive digital circuitry and memory interfaces are clocked synchronously to the RF oscillator [31] thus mitigating their aggressor effects, despite the fractional frequency relationship between the aggressor’s harmonic and the RF carrier. At least several dB reduction in the fractional spur levels have been consistently measured. IV. NOISE-FREE DITHERING OF REFERENCE CLOCK As discussed in Section III-B, the finite TDC resolution of 10–30 ps produces low-enough flat quantization noise for satisfactory RF operation with ADPLL bandwidths of up to 150–300 kHz. However, at integer- channels, and especially when the TDC resolution is an integer multiple of the DCO period, the quantization noise is ill-shaped and can concentrate within the loop bandwidth. To solve the problem, FREF is used by delaying the FREF dithering of up to several clock by means of slowing down the edges [20], [41], [25]

STASZEWSKI et al.: SPUR-FREE MULTIRATE ALL-DIGITAL PLL FOR MOBILE PHONES IN 65 NM CMOS

Fig. 15. Interference to the DCO from the digital circuit activity. To mitigate it, the digital baseband (DBB) clock is made synchronous to the DCO clock. Dithering the DBB clock lowers the DBB induced spurs.

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Fig. 17. Crystal oscillator slicer with coarse (3-level) and fine (16-level) delay control.

Fig. 16. Generation of a DCO-synchronous clock of average frequency equal to that of DBB-PLL. For illustration purposes, the DBB-PLL clock period is 1 = of the DCO clock period.

+1 8

through adjustment of an inverter driving strength to its load capacitance ratio. Unfortunately, degrading FREF clock edges not only adds significant noise but also makes it more sensitive to various aggressors. Fig. 17 shows the proposed noise-free method, in which the crystal oscillator (XO) slicer combines by the programmable edge delay and performs time shift to dynamically adding intentional mismatch transistors . This way, the programmable the differential input pair voltage offset (see Fig. 18) gets converted through the to coarse dither time offset sinusoidal waveform slope at the origin, according to (4): (4) where is the frequency of the sinusoid, and is its amplitude. was used for this particular RF-SoC. XO of The coarse dither, when engaged at near integer- channels by synchronously toggling at 2.4 MHz rate, uses only two levels, and , so its transfer function is perfectly linear. value is not critical as long as it spans several The exact . The high toggling rate places the resulting mixing products outside of the higher-order ADPLL loop filter. A second supplementary method, fine dithering [42], is in added by connecting 16 unit-weighted transistors

Fig. 18. SPICE simulated transfer function of the coarse dither circuit for three distinct values of the delay control.

parallel with to change the mirroring ratio, thus affecting the bias current of the differential pair, and ultimately the delay . The delay means could be considered a digof ital-to-time converter (DTC) with the transfer function shown in Fig. 19. The DTC digital input is controlled by a 16-level MASH sequence. A similar dithering technique 4th-order was used in [41], in which the 32-level 5-th order MASH modulator controlled the DTC by slowing down the FREF clock edges through digital control of a load capacitance of a driving inverter. The multibit dithering, however, has significant disadvantages versus the 1-bit coarse dithering mainly from the standpoint of linearity of the DTC conversion transfer function. dithering is expected to push the quantization noise to The high frequencies but the DTC conversion element nonlinearities might cause spectral regrowth by which the quantization noise reappears at low frequencies. The 1-bit DTC does not suffer from it due to its perfectly linear transfer function.

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0 0

Fig. 22. Timing diagram of quadrature phase (i.e., I+, Q+, I , Q ) rotation vs. no rotation. FCW = 3:0 (ovals – selected CKV edges, rotation off), FCW = 2:75 (rectangles – selected CKV edges, rotation on).

Fig. 19. SPICE simulated transfer function of the fine dither circuit for 16 values of the delay control.

Fig. 20. All-digital offset PLL architecture that realizes frequency translation via periodic rotation of the selected DCO quadrature phase. The additional circuitry augmenting the original ADPLL is enclosed within the dotted box.

Fig. 21. Details of the DCO system comprising the DCO core operating at 2 the high-band frequency for generating the quadrature phase clocks. The quadrature clock rotation via the digital mux performs the frequency translation.

2

V. FREQUENCY TRANSLATION OF FEEDBACK VARIABLE CLOCK The second proposed solution to the ill-conditioned in) the teger- TDC behavior is to frequency translate ( feedback clock locally at the TDC while, of course, preserving frequency relationship. Since the four clock the global phases of an RF oscillator are always naturally available or required (2 or 4 frequency operation of the oscillator core is now almost universally adopted in order to alleviate the oscillator pulling by the transmitted output signal; receiver mixer requires quadrature phases, etc.) it would appear most straightforward to change the selected quadrature phase at regular intervals. If the next quadrature phase is selected with each FREF clock via a 2-bit modulo-4 up counter, then the . The implementation is frequency translation will be illustrated in Fig. 20 with the additional DCO details shown in Fig. 21. The counter runs on the negative edge of FREF. The 4:1 quad mux is realized using pass-gates and fully-static gates and requires no special RF considerations since it is not

in the RF signal path. The area overhead is almost nil. The potential timing violations during the mux selection change are of no consequence since the TDC is mostly inactive except at the vicinity of the rising FREF edges. Consequently, the system-level operation of the DCO phase change is hitless. Fig. 22 illustrates a timing diagram of the quadrature clock ro. tation that realizes the negative frequency translation by The phase error comparison of the DCO clock is performed on every rising edge of the FREF clock. The FREF and DCO edges being active in the comparison process are marked with vertical arrows.6 The selection of the DCO clock phase changes by 90 with each new FREF edge. The selected DCO phases are marked by the enclosing thin rectangles. A reference case of no rotation is included for comparison in which the arrows are enclosed in ovals. In this example, the frequency multiplicaand the feedback clock tion ratio or will keep on selecting the same phase, which in this case is . The TDC-based phase detector will see a constant input, with all the artifacts. During the quadrature rotation, however, the comparison edges will experience constant rotation of one-quarter of the DCO cycle with each FREF edge. This is equivalent to a frequency translation of 1/4 of the reference frequency, (seen by the phase detector) will and the corresponding . The 4-level counter mode (increbe ment/decrement) that controls the mux selection determines the frequency translation direction (down/up). For a great majority of the channels that do not experience the near-integer- condition, the counter is reset to . Since the phase detection process uses only one DCO edge at every comparison cycle, the quadrature phase switchover can be done hitlessly if the counter output changes around the falling FREF edge. Fig. 22 also reveals a potential issue with the integer count. The fourth FREF comparison lasts one CKV cycle shorter than the three previous comparisons. This is motivated by the fact that the edge comparison is best realized within the and angles beyond need principal angular range of to be mapped back to the principal range7. It always occurs whenever the quadrature phase selection crosses the full-cycle (270 ) to (0 ) or vice boundary, i.e., it changes from versa, in case of the opposite rotational direction. There are two solutions: 1) instantaneous adjustment of the expected integer 6Note that this specific implementation of the TDC-based phase detection process uses the closest preceding DCO clock edge, rather than the closest edge, however the two cases are equivalent with one clock-cycle delay. 7Using the conventional feedback divider would certainly relax that requirement but at a cost of the increased range that the TDC needs to cover. This would have severe consequences on the TDC area, power consumption and non-linearity.

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TABLE I ADPLL KEY PERFORMANCE WHEN TRANSMITTING IN GSM GMSK MODE AND IMPLEMENTATION TABLE.

Fig. 23. Chip micrograph of an ADPLL-based transceiver as part of a digital polar transmitter and receiver section of an GSM/EDGE RF-SoC.

part of FCW during the full-cycle boundary (i.e., between and ), which is already handled by the reference accumulator as part of its normal operation; 2) disregarding of the integer part of FCW. We have, anyway, chosen the latter option for the following reason. After the loop is settled, the expected CKV-FREF clock edge separation is very well defined. Its uncertainty is due to the composite jitter value of much better than 25 ps, which is well below 5% of the CKV period. Counting the CKV edges is thus unnecessary. The reason for the CKV incrementer is to help with the frequency acquisition, when the initial frequency offset can be on the order of 100s of MHz. Consequently, the CKV incrementer can be safely shut down after the frequency and phase are acquired. Insisting on keeping the integer count is possible, but the quadrature clock switching would need to be made hitless, which would require careful synchronization. VI. IMPLEMENTATION AND MEASURED RESULTS The proposed architecture and techniques have been implemented and successfully verified in a Texas Instruments 65-nm CMOS process technology. Fig. 23 shows a chip micrograph of a GSM/EDGE RF transceiver section that emphasizes the ADPLL circuits: DCO, TDC with the high-speed incrementer, together with the common area of digital logic. The DPA is a digitally-controlled amplifier that interfaces the DCO output with the external low impedance load of the antenna circuitry. The DPA also features a digital amplitude modulation capability, which, together with the ADPLL featuring the frequency modulation capability, can act as a digital polar transmitter. The and its current consumption is ADPLL area is only 0.35 only 32 mA (low band) and 38 mA (high band) at 1.2 V supply. A. Measurement Summary Since the RF frequency synthesizer is typically just an internal part of a transmitter or a receiver system of a wireless device, while there are numerous ways of allocating the overall RF performance to various subsystems, it would be rather difficult to objectively compare its performance as a sovereign circuit. Hence, its frequency modulation capability is utilized to form a GSM transmitter. This way, the ADPLL performance dominates and it allows it to be directly assessed against the official ETSI or 3GPP specification [43] line items. The measured RF performance of the ADPLL-based GSM transmitter is best-in-class and is summarized in Table I. The modulation distortion (i.e., rms and peak phase error), as well as modulation mask spectral emission (phase noise at 400 kHz offset from the

carrier frequency), show huge margin against the 3GPP spec. The 20 MHz far-out noise into the receive band shows at least 4 dB margin thus eliminating the need for external SAW filters. The same ADPLL can also be configured to perform an 8-PSK PM modulation as part of the polar EDGE transmitter. However, although the modulation bandwidth is higher, the ADPLL path no longer dominates the RF performance and, as expected from a well-designed system, the distortions due to the other orthogonal path, i.e., AM modulation, now become more significant. The overall EDGE performance is still best-in-class showing large margin to the 3GPP specifications: The modulation distortion expressed as the error vector magnitude (EVM) is measured 1.5/2.5% rms and 3/6% peak (LB/HB). The spectral mask at 400 kHz offset was measured -63/-63 dBc (LB/HB). The far-out noise emission of -158/-154 dBm/Hz (LB/HB) at 20 MHz offset is completely dominated by the DPA. Table II shows the comparison of the ADPLL-based polar EDGE transmitter (it uses an almost identical ADPLL as this design [11]) against six other designs that use the traditional analog-intensive approach. They all are results of commercial endeavors, so a reasonable effort to reduce area and power can be assumed. The presented design is best-in-class. It meets and exceeds the RF performance of conventional analog-intensive approaches at a fraction of silicon area (1/3 to 1/4) and consumed power (1/2 to 1/3). B. Verification of Coarse Dithering of the Reference Clock Fig. 24 demonstrates effectiveness of the coarse dithering in both continuous wave (CW) and GMSK modulated modes. The carrier is 200 kHz and 400 kHz away from the 46th harmonic of the 38.4 MHz FREF. Since the DCO LC tank resonates at 2 of the high-band frequency, the injection-pulling spurs will be 400 kHz and 800 kHz away from the carrier, respectively. The quantization noise, however, has a complex pattern, which is analyzed in [36]. Engagement of the coarse dithering eliminates the ill-shaped quantization noise (mainly causing modulation distortion) and the injection pulling (mainly causing spurs). C. Verification of Quadrature Phase Rotation of the RF Oscillator Clock in the Feedback Path The clock rotation mux and the counter-based mux selector are part of the digital logic section of the ADPLL. The tech-

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TABLE II COMPARISON OF SILICON AREA AND DISSIPATED POWER OF THE 65-NM ADPLL-BASED GSM/EDGE TRANSMITTER VERSUS OTHER PUBLISHED COMMERCIAL EDGE IMPLEMENTATIONS. IF NOT EXPLICITLY GIVEN, THE TX AREA WAS ASSUMED 1/3 OF THE TRANSCEIVER AREA. (THE THREE EARLIEST PUBLICATIONS DO NOT REVEAL ALL THE AREA/POWER DATA BUT INSPECTION OF THE CHIP MICROGRAPH INDICATES WORSE NUMBERS THAN THE MORE RECENT PUBLICATIONS.).

Fig. 25. Measured un-modulated spectrum at 883.6 MHz carrier (with an additional 67.7 kHz frequency offset due to all-one modulation) without (blue curve) and with (red curve) the frequency translation of the feedback clock. The 23rd harmonic of the 38.4 MHz reference frequency is 400 kHz below at 883.2 MHz. The spurious tones at the reference harmonic due to the parasitic coupling and other spectral distortions due to insufficient randomization of the TDC output are largely eliminated with the frequency translation.

Fig. 24. Measured effect of coarse dither at 2.4 MHz on CW- (top) and GMSKmodulated (bottom) spectra at 200 kHz (left) and 400 kHz (right) away from the 1766.4 MHz integer- channel.

N

nique has been successfully verified by comparing the RF performance before and after the engagement of the frequency translation of the feedback clock. Fig. 25 shows the spectrum of the un-modulated carrier at 467.7 kHz above the closest FREF harmonic. The center of the plot lies two GSM channels (i.e., 400 kHz) above the FREF harmonic, but the all-ones GSM data makes an additional 67.7 kHz shift. Due to the close separation of the DCO frequency and FREF harmonic, and thus resulting beating tones in the TDC, the spectrum (blue curve) normally experiences excessive distortions. The frequency separation was deliberately chosen to be not too small, as the distortions would otherwise be masked by the high power of the close-in phase noise, and not too large, as the generated tones would be well outside of the PLL filtering range. The engagement of the frequency translation of the feedback clock (red curve) largely eliminates the distortions. Even though the data frequency modulation tends to spread around the spurious tones and further mask them with the modulating energy, there are certain frequency offsets that are still vulnerable to these distortions. The modulating energy decreases away from the carrier until about 350 kHz away,

where it is so low that the phase noise and spurious contributors can start to dominate. At the same time, the 400 kHz frequency offset is one of the most vulnerable in the modulating spectrum specification. Larger frequency offsets present less of a problem due to the quickly decaying power of the parasitic coupling and the stronger filtering. Consequently, the above makes it imperative to test the system behavior at the 400-kHz offset. Thus, Fig. 26 shows the GSM modulated spectrum at 400 kHz above the reference frequency harmonic. The resulting energy at -400 kHz offset from the carrier exhibits a noticeable tone, which is reduced by 2–3 dB (to -67.5 dB with respect to the 0 kHz offset) when the proposed frequency translation is engaged. The modulation distortion was measured to reduce from 2.2 to 1.8 rms. The transmitter is thus fully compliant with the GSM/EDGE standard and no adverse degradation in other RF specifications was observed. It appears that, to the first order of approximation, the coarse/fine dithering and the phase rotation methods are independent and could be engaged at the same time, although the present system would require only one of them. D. Measurement of Far-Out Noise Emissions Fig. 27 shows typical measured far-out phase noise spectra in the receive bands of GSM-850 (top) and GSM-900 (bottom) during the 2-point GMSK modulation of the ADPLL. As part of a pre-production design-of-experiments (DoE), seven wafers were fabricated that would correspond to seven representative process technology corners. The RF performance was then measured at each of the corners in order to assess the performance spread and manufacturing yield. The measurements prove tight distribution and the virtually spurious-free ADPLL operation that guarantees GSM-compliant SAW-less transmit operation. The higher frequency bands (DCS-1800 and PCS-1900) also show similar behavior. Note that the GSM

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behavior of the TDC, as well as the injection pulling of the DCO through the harmonics of the digital clocks, are eliminated by the noise-free dithering of the FREF edges. The ADPLL modulates the DCO at an arbitrarily high data rate independent from the FREF clock. The RF performance is best-in-class and has large margin to the 3GPP GSM specifications. The spur-free operation has been verified through design-of-experiments (DoE) fabrication and performance measurements at seven in 65 nm process corners. The occupied area is only 0.35 CMOS. The consumed current is only 32 mA at 1.2 V supply. ACKNOWLEDGMENT Fig. 26. Measured GMSK modulated spectrum at 883.6 MHz carrier without (violet curve) and with (blue curve) the frequency translation of the feedback clock. The 23rd harmonic of the 38.4 MHz reference frequency is 400 kHz below at 883.2 MHz. The spectral mask degradation at the reference harmonic shows 2–3 dB of improvement.

Fig. 27. Measured TX WBN in the RX bands shown to be compliant with margin in 7 ICs covering all process corners: (top) GSM-850: 20-to-45 MHz offsets from 848.8 MHz; (bottom) GSM-950: 10-to-45 MHz offsets from 914.8 MHz.

spec of to

/100 kHz (

) corresponds

. VII. CONCLUSION

We have presented a new architecture of an all-digital phase-locked loop (ADPLL) for generating a modulated RF carrier in mobile phones. The ADPLL comprises a digitally-controlled oscillator (DCO) for generating a digital RF carrier and a time-to-digital converter (TDC) for phase detection. The typical spurious tones due to the ill-conditioned

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STASZEWSKI et al.: SPUR-FREE MULTIRATE ALL-DIGITAL PLL FOR MOBILE PHONES IN 65 NM CMOS

Robert Bogdan Staszewski (S’94–M’97–SM’05–F’09) received the B.S.E.E. (summa cum laude), M.S.E.E., and Ph.D. degrees from University of Texas at Dallas in 1991, 1992, and 2002, respectively. From 1991 to 1995 he was with Alcatel Network Systems in Richardson, TX, working on SONET cross-connect systems for fiber optics communications. He joined Texas Instruments, Dallas, TX, in 1995 where he was elected Distinguished Member of Technical Staff. Between 1995 and 1999, he was engaged in advanced CMOS read channel development for hard disk drives. In 1999, he co-started a Digital RF Processor (DRP™) group within Texas Instruments with a mission to invent new digitally-intensive approaches to traditional RF functions for integrated radios in deeply-scaled CMOS processes. He was appointed a CTO of the DRP group between 2007 and 2009. Since July 2009 he has been Associate Professor at Delft University of Technology in the Netherlands. He has authored and co-authored one book, three book chapters, 120 journal and conference publications, and holds 70 issued and 40 pending U.S. patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. Dr. Staszewski is an IEEE Fellow and has been a member of RF Subcommittee of ISSCC since 2007.

Khurram Waheed received the B.Sc.(hons.) degree in electrical engineering from the University of Engineering and Technology, Lahore, Pakistan, in 1994, and both the M.S. and Ph.D. degrees in electrical engineering from Michigan State University, East Lansing, in 2000 and 2003, respectively. He is currently a Senior System Architect with Freescale Semiconductors, Inc. Previously he has held positions with Advanced Engineering Research Organization (AERO, 1994–1999), Michigan State University (1999–2003), San Diego State University (2003–04) and Texas Instruments, Inc. (2004–2009). His research interests include novel digital and signal processing intensive architectural approaches to traditional RF functions, design of integrated radios in advanced CMOS processes, blind source recovery algorithms for static and dynamic environments, non-linear signal processing and communications algorithms and their implementations. He has published more than 50 technical papers, holds 9 granted and 25 pending patents. He Dr. Waheed is an active contributing member of IEEE Standards Association, Circuits and Systems and Communication Societies. He contributes to several Technical committees and serves as a reviewer for various international journals and conferences.

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Fikret Dülger received the B.S. and M.S. degrees in electronics from Istanbul Technical University (ITU), Istanbul, Turkey, in 1993 and 1996, respectively, and the Ph.D. degree in electronics from Texas A&M University, College Station, in 2002. He was a Research Assistant with the Electronics and Communication Engineering Department, ITU, from 1993 to 1996. In 1994, he was a Design Engineer with the ETA ASIC Design Center, Istanbul, Turkey. He was a Research and Teaching Assistant in the Department of Electrical Engineering, Texas A&M University, between 1996 and 2002. From 2002 to 2009, he worked as a Design Engineer in the RF IC Design Group, Texas Instruments Inc. Between February 2009 and April 2011 he was a Senior RF IC Design Engineer with Zoran, Plano, TX. In April 2011 he re-joined Texas Instruments. He has coauthored numerous scientific papers in international journals and conferences, a book titled Integrated RF Building Blocks for Wireless Communication Transceivers (Saarbrucken, VDM Verlag, 2008). His research and professional interests are in the area of analog circuit design for RF integrated circuits.

Oren Eliezer received the B.S.E.E and M.S.E.E. degrees in electrical engineering from Tel-Aviv University, Israel, in 1988 and 1996 respectively, and the Ph.D. degree from The University of Texas at Dallas (UTD), in 2008. He served in The Israel Defense Forces from 1988 to 1994, where he specialized in wireless communications, and after his military service he co-founded Butterfly Communications in Israel and served as the company’s chief engineer. Following Butterfly’s acquisition by Texas Instruments (TI) in 1999, he was relocated to Dallas in 2002, where he took part in the development of TI’s Digital RF Processor (DRP™) technology and was elected Senior Member of Technical Staff. At TI he specialized in digital transceiver architecture, built-in testing, calibration and compensation, and mitigation of self-interference in RF SoCs. He has authored and coauthored over 40 conference and journal papers on these topics and over 30 issued/pending patents. He is currently the Chief Technology Officer at Xtendwave in Dallas, and participates in the research at the Texas Analog Center of Excellence (TxACE) at UTD.