Strategic Test Cost Reduction with On-Chip ... - Semantic Scholar
Strategic Test Cost Reduction with On-Chip Measurement Circuitry for RF Transceiver Front-Ends – An Overview Marvin Onabajo, Felix Fernandez, Jose Silva-Martinez, and Edgar Sánchez-Sinencio Analog and Mixed-Signal Center Dept. of Electrical & Computer Eng., Texas A&M University College Station, TX 77843, USA {monabajo, felixf, jsilva, sanchez}@ece.tamu.edu Abstract—This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time.
I. INTRODUCTION AND MOTIVATION Trends towards increasing complexity of integrated mixed-signal systems are continuing to cause technical challenges and high cost associated with testing. In the past as well as in recent projections, it has been reported that testing can contribute up to 40-50% of the total integrated circuit manufacturing cost [1-3]. With the advent of more complex and costly system-in-a-package (SIP) and multichip module (MCM) technologies, there is an increased incentive for known-good-die testing at wafer sort to avoid the rising cost of subsequent packaging and final test. But, on-wafer verification at RF frequencies requires welldesigned and costly hardware for high-volume production test with automatic test equipment (ATE) [4]. Alternative approaches to provide product quality assurance have emerged involving design-for-test (DFT) and built-in self-test (BIST) of analog and mixed-signal circuits operating at RF frequencies. Similar to those DFT and BIST techniques popular in digital testing, the advantages of the approaches are improved test coverage at internal nodes, avoidance of long high-frequency signal paths to external measurement equipment, and potential for on-chip calibration. Based on the definition in [5], complete BIST requires the on-chip generation of test stimuli, response analysis of the signal at the output of the circuit under test (CUT), and generation of a pass/fail result or a series of bits that can be evaluated externally by bit-wise comparison with a reference vector using low-cost digital ATE. Due to the analog nature of the signals, full BIST of RF circuits currently requires long test times and significant chip area overhead for on-chip digital signal processing (DSP) [5]. It
1-4244-0173-9/06/$20.00 ©2006 IEEE.
also necessitates further improvements of testing methods, especially for on-line testing [6]. II.
TEST PHILOSOPHY AND ECONOMICS
Comprehensive, but time-consuming characterization testing is conducted during design debug and prior to highvolume production to ensure product compliance to specifications. On the contrary, the purpose of production testing is to screen out substandard parts due to processing defects and process variations. A more detailed discussion about the impact of test time on cost in the production phase is provided in [7]. Fig. 1 shows high-level charts of the traditional post-fabrication test flow and the test flow for known-good-die testing, which is in rising demand due to the emergence of multi-die assemblies and increasing packaging cost. The needs for continued development of DFT/BIST methods for analog cores and wafer-level burn-in tests have both been emphasized in the 2005 International Roadmap for Semiconductors [8]. With regards to the flow charts in Fig. 1, test cost reduction efforts typically fall into three categories [9]: • • •
“Test faster” – increased equipment throughput, operational efficiency (technicians, management, process engineers), ATE test program improvements “Test earlier” – early identification of faulty devices to prevent incurrence of packaging and additional test cost from further processing “Test less” – removal of redundant or non-critical tests based on statistical correlations with existing data (i.e. final test vs. wafer test), sampling plan reduction
a)
b) Figure 1. Production test flows: (a) traditional, (b) known-good-die test
Efficient ATE hardware development for RF test involves additional cost considerations [4, 10]. Table 1 provides a summary of key factors and their technical impact in the development of alternative test strategies.
TABLE I. Cost Factor Test time Number of inputs/outputs
Batch-mode testing
Test fixture design
ALTERNATIVE STRATEGIES FOR TEST COST REDUCTION
Technical Implications for Alternative On-Chip Test Approaches - Develop circuitry for on-chip measurements in the analog domain to avoid long signal paths to ATE and long computation time with DSP-based algorithms - Minimize test pins as they drive up the package cost and die size - Design on-chip circuitry to maximize coverage of internal nodes → multiplex test output signals - Avoid test stimuli that are difficult to generate with low-cost/low-frequency (preferably below 100MHz) digital ATE signals on multiple channels - Design for parallel testing of multiple parts (onwafer test offers more cost-saving opportunities in batch-mode via multi-site testing; mechanical handling time at final test is longer because individual packages are processed) - Use on-chip circuitry to generate high frequency test signals or to up-convert signals (impedance matching and RF ports require costly test fixture designs and more expensive RF testers) - Implement communication schemes between onchip circuitry and testers that are compatible with low-speed digital ATE
III. SURVEY OF RESEARCH RELATED TO BIST Reported RF BIST schemes have been aimed at providing specification-based functional verification and advancing structural tests to identify catastrophic failures. A widespread practice is to replace as many functional tests as permissible with faster structural tests during test time reduction efforts as the production yield improves. In the case of RF circuits, some form of functional verification is typically required even for mature products [10]. Thus, onchip RF test methodologies are directed towards verifying system specifications as well as acquiring pass/fail results. A. Functional and Specification-Driven Test Approaches A full BIST for wireless transceivers with on-chip test stimulus generation and extraction of signal-to-noise ratio (SNR), frequency response, and intermodulation distortion has been presented in [11]. This test scheme involves all transceiver blocks and the computation of the parameters in the digital baseband. More recently, it has been reported how optimized test stimuli can be utilized for spectral analysis and replace several block-level specification tests for integrated transceivers in loopback mode [12]. A single error vector magnitude (EVM) measurement can also be substituted for multiple tests because it contains information about the modulation quality and amplitude/phase responses across the entire bandwidth [7, 13]. Alternatively to the simultaneous verification of the entire transceiver front-end, mixed-signal test strategies have been proposed that involve the measurement of parameters such as gain, impedance match, noise figure, intermodulation, and 1-dB compression for individual blocks [14, 15]. The mixed-signal test approach allows obtaining data from each block that can be used in fault diagnosis and on-chip calibration at the cost of additional area and the generation of more test stimuli. These test stimuli are normally sinusoids for single- or two-tone tests.
It is critical that the measurement circuits for each RF block do not add extensive chip area overhead and do not load the RF signal path significantly. Additional requirements for the circuits are: minimal complexity, short processing time, and robustness to process variations. Since the sensor circuits are typically designed as non-intrusive as possible, the topology could be as minimal as a simple twotransistor differential peak detector in [16], which might require statistical regression models to predict specifications from the outputs. For applications that require continuous testing during normal operation, a statistical sampler consisting of a comparator and a flip-flop was proposed in [6] to estimate the power spectral density with the aid of predetermined information about the fault-free response. Specification-based strategies are the primary driving force behind the development of a variety of on-chip instrumentation circuits addressed in section IV. They add on-chip functional test capability and furnish necessary data for on-chip calibration. This can improves test coverage and enables correction of faulty RF systems-on-chips (SOCs) that are susceptible to functional parameter variations due to performance-dependency on on-chip passives with low quality factors as well as process variation. In batterypowered systems, the power consumption becomes a critical design factor. On-line measurement circuitry may be used for continuous or periodic testing rather than in production test mode, which adds a power consumption constraint. In general, on-chip characterization and specification-driven approaches have the tendency to take up considerable die area with signal generation, analog-to-digital conversion (for response capture), and DSP circuitry. B. Defect-Oriented and Structural Test Approaches With the goal to prevent non-functional parts from reaching the customer, it is an established test practice to identify catastrophic faults such as opens and shorts by measuring DC supply and leakage currents. Random catastrophic faults caused by metal or polysilicon cracks, missing contacts, and dust particles are detectable with these quick checks. For further fault diagnosis and calibration of the analog RF front-end blocks, special circuits have been constructed to measure supply current variations with minimal interference [17] and to calibrate bias currents [18]. It was also demonstrated in [2] that fault coverage can be improved by applying a ramp signal at the power supply nodes to measure the quiescent currents of the devices in different operating regions. Realistic fault modeling and simulations to assess the effects of particular defects on the overall performance is essential in structural and defect-oriented approaches. The methodologies to generate fault models and test cases for analog and RF circuits are similar to those for digital circuits. They typically involve the insertion of a fault into the circuit, simulation (Monte Carlo, process corner, or similar techniques), comparison with specifications to assess the fault, generation of a test list, and development of an effective test.
Analog and mixed-signal circuits require more accurate defect modeling than their digital counterparts. One reason for this is that the performance of analog circuits is more layout-dependent, which requires an analysis of the layout to identify realistic defects as in [19]. It has also been demonstrated that open or cracked metal lines at RF frequencies are not modeled appropriately with the traditional resistive model. In [20], for example, a model was proposed that takes tunneling current and noise generation between the two ends of cracked metal lines into account by including a capacitor and noise sources in the defect model. Another challenge in the fault modeling of analog circuits is to determine the correlation of the defects with the acceptable specification range. Extensive simulations are required because the goal of defect-oriented test is to replace specification-based measurements that require more expensive instrumentation and longer test time, which was done for s-parameters and noise figure measurements in [21]. Results from continued development of defect modeling and simulation models present an increasing incentive to save cost by optimizing test time and reducing test set-up complexity. IV.
ON-CHIP INSTRUMENTATION FOR RF BLOCKS
The attractiveness of on chip instrumentation is the possibility of measuring parameters of the CUT at the wafer level. A proposed detector-based BIST implementation that makes use of hardware-based test responses to produce a DC signature has been presented in [24]. This approach has been criticized for requiring post-production calibration for accuracy. On-chip instrumentation techniques have to be process variation and temperature (PVT) insensitive. The feature detectors suffer from process variation and thermal effects that may impact their performance. In RF circuits, it is possible for the detector size to approach the RF CUT size, which is an unacceptable area overhead [16]. Recently, a technique to circumvent these limitations was presented in [25]. It has been demonstrated that simple detector architectures can provide measurements with sufficient accuracy for feature extraction. This can be done by extracting the desired features based on relative measurements rather than absolute values. Measurement errors in the detector structure can be canceled when the outputs from two consecutive detectors are compared. The main trade-off for feature extraction BIST is between cost of chip area overhead and the test coverage improvement. Silicon real estate becomes a limiting factor as the complexity of the instrumentation increases. The tradeoff between area and test coverage has to be considered on a case-to-case basis. The RMS power detector presented in [25] provides sufficient dynamic range for a variety of RF applications, high input impedance, and consumes a small amount of area. Therefore, it is a practical option for feature extraction BIST. V.
RF TRANSCEIVER FRONT-END TESTING
In this section, a closer look will be taken at the testing requirements for the basic building blocks in the highfrequency front-end of RF transceivers. The transmitter
typically includes a low noise amplifier (LNA), a downconversion mixer, and a low-pass filter. In the transmitter section, the most critical building block is the power amplifier (PA). All of these blocks require different sets of measurements to properly characterize their behavior. The following test approaches can also be extended to circuit blocks in the intermediate frequency section of heterodyne architectures. All measurements can be realized by means of RMS power detection. A. LNA A typical LNA characterization includes the measurement of its power gain, third order intercept point (IIP3), input impedance matching (S11), and noise figure (NF). The power gain can be determined by comparing the power measurements at the input and output of the LNA. The LNA’s IIP3 cannot be extracted directly without the presence of a two-tone test, which necessitates the estimation with an alternative single-tone test as in [26]. The 1-dB compression can be determined by sweeping the power of the LNA input signal and comparing the input and output power measurements. In [15], it has been shown that the input matching and the system’s NF can be determined indirectly with on-chip instrumentation. The drawback of this approach is the need for an extra on-chip test amplifier. B. Mixer The mixer characterization includes the measurement of conversion gain, linearity, and NF. The gain and linearity, namely the 1-dB compression point measurements, are realized in the same manner as for the LNA. Due to the timevarying characteristics of the mixer, its noise figure is extremely difficult to measure. To the authors’ knowledge, no reference to this specific measurement has been published at the present time. C. Power Amplifier Typical PA metrics include output power, efficiency, power gain, linearity, and adjacent channel power ratio (ACPR). Generally, the power within the band of interest is taken into account during the characterization of PAs, but for the following BIST case, the output power assessment will be defined by a single-tone sinusoidal signal. The output power can be approximated by the DC output of the RMS power detector. The power added efficiency (PAE) can be extracted from the difference in the DC outputs of the RMS power detectors at the input and output of the PA assuming that constant DC power is drawn. The power gain can be extracted from the ratio of the DC power detectors at the PA input and output. Linearity can be assessed with the 1-dB compression point in the same manner as for the LNA and mixer. Finally, the ACPR measurement requires the power measurement within a certain bandwidth separate from the channel bandwidth. This information cannot be extracted with the RMS power detectors due to their broadband behavior.
VI.
CASE STUDY: COMBINING LOOPBACK WITH POWER DETECTORS FOR RF TRANSCEIVER SOCs
A simplified block diagram of a conventional RF transceiver front-end is displayed in Fig. 2. In this section, it will be illustrated how on-wafer specification-based test with low-cost ATE could be implemented for products in which such a front-end is integrated into a SOC together with the modulation/demodulation circuitry in the baseband. For simplicity, only the power amplifier (PA), low noise amplifier (LNA), down-conversion mixer, and low-pass filter are shown. The root-mean-square (RMS) power detectors generate a DC voltage proportional to the power at their inputs. An attenuator and offset mixer are added for the loopback. The offset mixer is required for communication standards employing separate uplink and downlink frequencies, such as W-CDMA and CDMA2000. The main test signals sent by the ATE are the test input bitstream to the baseband section and the offset signal to the mixer. The ATE acquires the low-frequency test results from the output of the baseband section and the DC-to-digital converter, which multiplexes the power detector outputs to reduce the pin count. Algorithms have been presented to demonstrate that an optimized periodic bitstream can be sent through the transmitter subsystem and looped back through the receiver subsystem for on-chip functional verification and specification prediction [12, 22]. In addition, RMS detectors were recently introduced [23] to characterize individual RF building blocks without significantly affecting circuit performance. As discussed in section IV, these detectors allow the measurement of output power levels, gains, and 1dB compression points for each block, while occupying an extremely small area. Their placement at the input and output of RF blocks allows the identification of fault locations. It also prevents fault masking that can occur due to error cancellations between sections. For example, a PA gain above the acceptable limit might not cause any increase in the bit error rate at the baseband output if the LNA gain is too high in the absence of RMS detectors. Thus, by combining loopback with power detector measurements, specification-based functional testing can be conducted at wafer sort with an increased coverage at internal nodes.
Figure 2. Transceiver front-end with loopback and RMS detectors
A. Loopback Block: Variable Attenuator & Offset Mixer At a minimum, characterization of the transceiver frontend circuitry will have to be performed at the low-power reference signal, the 1-dB compression levels, and the different power settings of the PA, LNA, or other amplification stages. From a block-level perspective (Fig. 3), the required attenuation of the signal in the loopback could be up to 120dB with multiple settings. An attenuator for loopback consisting of a passive resistor ladder network was reported in [27]. To allow testing at multiple power levels, the use of MOS devices in triode region to achieve variable attenuation in the loopback with low area overhead presents an opportunity for future work. Depending on the communication standard, the loopback block might have to provide 40-100MHz frequency shifting between the transmitter and receiver sections; which necessitates an offset mixer. A practical loopback block design must also meet the following specifications for the specific communication standard/transceiver: input/output impedance matching, noise requirement at the sensitive LNA input, switches with high isolation, suppression of spurious tones below specified blocking levels, avoidance of mixing byproducts that saturate the LNA, and other relevant requirements.
Figure 3. Loopback Block
B. RMS Power Detector The use of power detectors has been demonstrated as an efficient way to implement BIST in the RF section of transceivers [23, 24]. The basic concept behind the RMS power detection is a three stage design. The first stage senses the RF signal and amplifies it to a desired level. This signal is then rectified and low-pass filtered in the second and third stages to generate a pseudo-rms equivalent DC output. Previous implementations of this structure have been reported in [15, 28]. The main limitation of all of these structures is the rectification stage. Several publications use a BJT-based rectification as in [29]. Even though the BJT approach is an elegant solution, it requires a BiCMOS technology. Most of the current research efforts are focused on implementing power detectors in RF CMOS technologies in which true BJTs are not available. To this end, a CMOSbased rectification was presented in [23]. The most promising approach utilizes a class AB rectification, which was first introduced in [30]. These CMOS rectifiers are limited by their small linear dynamic range, which is about 20dB. Fig. 4 shows the main concept behind the relative power measurement involving the output comparison of two RMS detectors. The gain and 1-dB compression points are indicated in the figure. All the tests described in section V can be realized with the addition of power detectors and offset mixers. Thus, enabling high fault coverage and feature extraction of RF front-ends by means of BIST.
[8] [9] [10]
[11]
[12]
[13]
Figure 4. RMS Power detector gain and 1-dB compresion point
VII. CONCLUSION On-chip instrumentation can be utilized to reduce ATE hardware development cost and avoid technical complications associated with wafer probing at RF frequencies. BIST has emerged as a strong candidate to solve these issues. The benefits of a BIST have to be weighted against the cost of its required chip area on an applicationspecific basis. Challenges in RF/analog BIST continue to be addressed by current work in this field to improve fault modeling, on-chip instrumentation circuitry, and test strategies, while avoiding high frequency test inputs/ outputs. Recent developments in on-chip instrumentation research show a trend towards embedded non-intrusive circuitry with low-frequency or DC outputs for a robust interface between the CUT and ATE. In parallel, algorithm development for processing in the digital baseband is mainly directed towards exploiting RF system properties (e.g. spectral signatures, EVM) in order to enable faster processing with minimal need for additional digital circuitry. Synchronization of the aforementioned efforts will be critical to achieve cost-effective BIST and high test coverage. REFERENCES [1]
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I. INTRODUCTION AND MOTIVATION Trends towards increasing complexity of integrated mixed-signal systems are continuing to cause technical challenges and high cost associated with testing. In the past as well as in recent projections, it has been reported that testing can contribute up to 40-50% of the total integrated circuit manufacturing cost [1-3]. With the advent of more complex and costly system-in-a-package (SIP) and multichip module (MCM) technologies, there is an increased incentive for known-good-die testing at wafer sort to avoid the rising cost of subsequent packaging and final test. But, on-wafer verification at RF frequencies requires welldesigned and costly hardware for high-volume production test with automatic test equipment (ATE) [4]. Alternative approaches to provide product quality assurance have emerged involving design-for-test (DFT) and built-in self-test (BIST) of analog and mixed-signal circuits operating at RF frequencies. Similar to those DFT and BIST techniques popular in digital testing, the advantages of the approaches are improved test coverage at internal nodes, avoidance of long high-frequency signal paths to external measurement equipment, and potential for on-chip calibration. Based on the definition in [5], complete BIST requires the on-chip generation of test stimuli, response analysis of the signal at the output of the circuit under test (CUT), and generation of a pass/fail result or a series of bits that can be evaluated externally by bit-wise comparison with a reference vector using low-cost digital ATE. Due to the analog nature of the signals, full BIST of RF circuits currently requires long test times and significant chip area overhead for on-chip digital signal processing (DSP) [5]. It
1-4244-0173-9/06/$20.00 ©2006 IEEE.
also necessitates further improvements of testing methods, especially for on-line testing [6]. II.
TEST PHILOSOPHY AND ECONOMICS
Comprehensive, but time-consuming characterization testing is conducted during design debug and prior to highvolume production to ensure product compliance to specifications. On the contrary, the purpose of production testing is to screen out substandard parts due to processing defects and process variations. A more detailed discussion about the impact of test time on cost in the production phase is provided in [7]. Fig. 1 shows high-level charts of the traditional post-fabrication test flow and the test flow for known-good-die testing, which is in rising demand due to the emergence of multi-die assemblies and increasing packaging cost. The needs for continued development of DFT/BIST methods for analog cores and wafer-level burn-in tests have both been emphasized in the 2005 International Roadmap for Semiconductors [8]. With regards to the flow charts in Fig. 1, test cost reduction efforts typically fall into three categories [9]: • • •
“Test faster” – increased equipment throughput, operational efficiency (technicians, management, process engineers), ATE test program improvements “Test earlier” – early identification of faulty devices to prevent incurrence of packaging and additional test cost from further processing “Test less” – removal of redundant or non-critical tests based on statistical correlations with existing data (i.e. final test vs. wafer test), sampling plan reduction
a)
b) Figure 1. Production test flows: (a) traditional, (b) known-good-die test
Efficient ATE hardware development for RF test involves additional cost considerations [4, 10]. Table 1 provides a summary of key factors and their technical impact in the development of alternative test strategies.
TABLE I. Cost Factor Test time Number of inputs/outputs
Batch-mode testing
Test fixture design
ALTERNATIVE STRATEGIES FOR TEST COST REDUCTION
Technical Implications for Alternative On-Chip Test Approaches - Develop circuitry for on-chip measurements in the analog domain to avoid long signal paths to ATE and long computation time with DSP-based algorithms - Minimize test pins as they drive up the package cost and die size - Design on-chip circuitry to maximize coverage of internal nodes → multiplex test output signals - Avoid test stimuli that are difficult to generate with low-cost/low-frequency (preferably below 100MHz) digital ATE signals on multiple channels - Design for parallel testing of multiple parts (onwafer test offers more cost-saving opportunities in batch-mode via multi-site testing; mechanical handling time at final test is longer because individual packages are processed) - Use on-chip circuitry to generate high frequency test signals or to up-convert signals (impedance matching and RF ports require costly test fixture designs and more expensive RF testers) - Implement communication schemes between onchip circuitry and testers that are compatible with low-speed digital ATE
III. SURVEY OF RESEARCH RELATED TO BIST Reported RF BIST schemes have been aimed at providing specification-based functional verification and advancing structural tests to identify catastrophic failures. A widespread practice is to replace as many functional tests as permissible with faster structural tests during test time reduction efforts as the production yield improves. In the case of RF circuits, some form of functional verification is typically required even for mature products [10]. Thus, onchip RF test methodologies are directed towards verifying system specifications as well as acquiring pass/fail results. A. Functional and Specification-Driven Test Approaches A full BIST for wireless transceivers with on-chip test stimulus generation and extraction of signal-to-noise ratio (SNR), frequency response, and intermodulation distortion has been presented in [11]. This test scheme involves all transceiver blocks and the computation of the parameters in the digital baseband. More recently, it has been reported how optimized test stimuli can be utilized for spectral analysis and replace several block-level specification tests for integrated transceivers in loopback mode [12]. A single error vector magnitude (EVM) measurement can also be substituted for multiple tests because it contains information about the modulation quality and amplitude/phase responses across the entire bandwidth [7, 13]. Alternatively to the simultaneous verification of the entire transceiver front-end, mixed-signal test strategies have been proposed that involve the measurement of parameters such as gain, impedance match, noise figure, intermodulation, and 1-dB compression for individual blocks [14, 15]. The mixed-signal test approach allows obtaining data from each block that can be used in fault diagnosis and on-chip calibration at the cost of additional area and the generation of more test stimuli. These test stimuli are normally sinusoids for single- or two-tone tests.
It is critical that the measurement circuits for each RF block do not add extensive chip area overhead and do not load the RF signal path significantly. Additional requirements for the circuits are: minimal complexity, short processing time, and robustness to process variations. Since the sensor circuits are typically designed as non-intrusive as possible, the topology could be as minimal as a simple twotransistor differential peak detector in [16], which might require statistical regression models to predict specifications from the outputs. For applications that require continuous testing during normal operation, a statistical sampler consisting of a comparator and a flip-flop was proposed in [6] to estimate the power spectral density with the aid of predetermined information about the fault-free response. Specification-based strategies are the primary driving force behind the development of a variety of on-chip instrumentation circuits addressed in section IV. They add on-chip functional test capability and furnish necessary data for on-chip calibration. This can improves test coverage and enables correction of faulty RF systems-on-chips (SOCs) that are susceptible to functional parameter variations due to performance-dependency on on-chip passives with low quality factors as well as process variation. In batterypowered systems, the power consumption becomes a critical design factor. On-line measurement circuitry may be used for continuous or periodic testing rather than in production test mode, which adds a power consumption constraint. In general, on-chip characterization and specification-driven approaches have the tendency to take up considerable die area with signal generation, analog-to-digital conversion (for response capture), and DSP circuitry. B. Defect-Oriented and Structural Test Approaches With the goal to prevent non-functional parts from reaching the customer, it is an established test practice to identify catastrophic faults such as opens and shorts by measuring DC supply and leakage currents. Random catastrophic faults caused by metal or polysilicon cracks, missing contacts, and dust particles are detectable with these quick checks. For further fault diagnosis and calibration of the analog RF front-end blocks, special circuits have been constructed to measure supply current variations with minimal interference [17] and to calibrate bias currents [18]. It was also demonstrated in [2] that fault coverage can be improved by applying a ramp signal at the power supply nodes to measure the quiescent currents of the devices in different operating regions. Realistic fault modeling and simulations to assess the effects of particular defects on the overall performance is essential in structural and defect-oriented approaches. The methodologies to generate fault models and test cases for analog and RF circuits are similar to those for digital circuits. They typically involve the insertion of a fault into the circuit, simulation (Monte Carlo, process corner, or similar techniques), comparison with specifications to assess the fault, generation of a test list, and development of an effective test.
Analog and mixed-signal circuits require more accurate defect modeling than their digital counterparts. One reason for this is that the performance of analog circuits is more layout-dependent, which requires an analysis of the layout to identify realistic defects as in [19]. It has also been demonstrated that open or cracked metal lines at RF frequencies are not modeled appropriately with the traditional resistive model. In [20], for example, a model was proposed that takes tunneling current and noise generation between the two ends of cracked metal lines into account by including a capacitor and noise sources in the defect model. Another challenge in the fault modeling of analog circuits is to determine the correlation of the defects with the acceptable specification range. Extensive simulations are required because the goal of defect-oriented test is to replace specification-based measurements that require more expensive instrumentation and longer test time, which was done for s-parameters and noise figure measurements in [21]. Results from continued development of defect modeling and simulation models present an increasing incentive to save cost by optimizing test time and reducing test set-up complexity. IV.
ON-CHIP INSTRUMENTATION FOR RF BLOCKS
The attractiveness of on chip instrumentation is the possibility of measuring parameters of the CUT at the wafer level. A proposed detector-based BIST implementation that makes use of hardware-based test responses to produce a DC signature has been presented in [24]. This approach has been criticized for requiring post-production calibration for accuracy. On-chip instrumentation techniques have to be process variation and temperature (PVT) insensitive. The feature detectors suffer from process variation and thermal effects that may impact their performance. In RF circuits, it is possible for the detector size to approach the RF CUT size, which is an unacceptable area overhead [16]. Recently, a technique to circumvent these limitations was presented in [25]. It has been demonstrated that simple detector architectures can provide measurements with sufficient accuracy for feature extraction. This can be done by extracting the desired features based on relative measurements rather than absolute values. Measurement errors in the detector structure can be canceled when the outputs from two consecutive detectors are compared. The main trade-off for feature extraction BIST is between cost of chip area overhead and the test coverage improvement. Silicon real estate becomes a limiting factor as the complexity of the instrumentation increases. The tradeoff between area and test coverage has to be considered on a case-to-case basis. The RMS power detector presented in [25] provides sufficient dynamic range for a variety of RF applications, high input impedance, and consumes a small amount of area. Therefore, it is a practical option for feature extraction BIST. V.
RF TRANSCEIVER FRONT-END TESTING
In this section, a closer look will be taken at the testing requirements for the basic building blocks in the highfrequency front-end of RF transceivers. The transmitter
typically includes a low noise amplifier (LNA), a downconversion mixer, and a low-pass filter. In the transmitter section, the most critical building block is the power amplifier (PA). All of these blocks require different sets of measurements to properly characterize their behavior. The following test approaches can also be extended to circuit blocks in the intermediate frequency section of heterodyne architectures. All measurements can be realized by means of RMS power detection. A. LNA A typical LNA characterization includes the measurement of its power gain, third order intercept point (IIP3), input impedance matching (S11), and noise figure (NF). The power gain can be determined by comparing the power measurements at the input and output of the LNA. The LNA’s IIP3 cannot be extracted directly without the presence of a two-tone test, which necessitates the estimation with an alternative single-tone test as in [26]. The 1-dB compression can be determined by sweeping the power of the LNA input signal and comparing the input and output power measurements. In [15], it has been shown that the input matching and the system’s NF can be determined indirectly with on-chip instrumentation. The drawback of this approach is the need for an extra on-chip test amplifier. B. Mixer The mixer characterization includes the measurement of conversion gain, linearity, and NF. The gain and linearity, namely the 1-dB compression point measurements, are realized in the same manner as for the LNA. Due to the timevarying characteristics of the mixer, its noise figure is extremely difficult to measure. To the authors’ knowledge, no reference to this specific measurement has been published at the present time. C. Power Amplifier Typical PA metrics include output power, efficiency, power gain, linearity, and adjacent channel power ratio (ACPR). Generally, the power within the band of interest is taken into account during the characterization of PAs, but for the following BIST case, the output power assessment will be defined by a single-tone sinusoidal signal. The output power can be approximated by the DC output of the RMS power detector. The power added efficiency (PAE) can be extracted from the difference in the DC outputs of the RMS power detectors at the input and output of the PA assuming that constant DC power is drawn. The power gain can be extracted from the ratio of the DC power detectors at the PA input and output. Linearity can be assessed with the 1-dB compression point in the same manner as for the LNA and mixer. Finally, the ACPR measurement requires the power measurement within a certain bandwidth separate from the channel bandwidth. This information cannot be extracted with the RMS power detectors due to their broadband behavior.
VI.
CASE STUDY: COMBINING LOOPBACK WITH POWER DETECTORS FOR RF TRANSCEIVER SOCs
A simplified block diagram of a conventional RF transceiver front-end is displayed in Fig. 2. In this section, it will be illustrated how on-wafer specification-based test with low-cost ATE could be implemented for products in which such a front-end is integrated into a SOC together with the modulation/demodulation circuitry in the baseband. For simplicity, only the power amplifier (PA), low noise amplifier (LNA), down-conversion mixer, and low-pass filter are shown. The root-mean-square (RMS) power detectors generate a DC voltage proportional to the power at their inputs. An attenuator and offset mixer are added for the loopback. The offset mixer is required for communication standards employing separate uplink and downlink frequencies, such as W-CDMA and CDMA2000. The main test signals sent by the ATE are the test input bitstream to the baseband section and the offset signal to the mixer. The ATE acquires the low-frequency test results from the output of the baseband section and the DC-to-digital converter, which multiplexes the power detector outputs to reduce the pin count. Algorithms have been presented to demonstrate that an optimized periodic bitstream can be sent through the transmitter subsystem and looped back through the receiver subsystem for on-chip functional verification and specification prediction [12, 22]. In addition, RMS detectors were recently introduced [23] to characterize individual RF building blocks without significantly affecting circuit performance. As discussed in section IV, these detectors allow the measurement of output power levels, gains, and 1dB compression points for each block, while occupying an extremely small area. Their placement at the input and output of RF blocks allows the identification of fault locations. It also prevents fault masking that can occur due to error cancellations between sections. For example, a PA gain above the acceptable limit might not cause any increase in the bit error rate at the baseband output if the LNA gain is too high in the absence of RMS detectors. Thus, by combining loopback with power detector measurements, specification-based functional testing can be conducted at wafer sort with an increased coverage at internal nodes.
Figure 2. Transceiver front-end with loopback and RMS detectors
A. Loopback Block: Variable Attenuator & Offset Mixer At a minimum, characterization of the transceiver frontend circuitry will have to be performed at the low-power reference signal, the 1-dB compression levels, and the different power settings of the PA, LNA, or other amplification stages. From a block-level perspective (Fig. 3), the required attenuation of the signal in the loopback could be up to 120dB with multiple settings. An attenuator for loopback consisting of a passive resistor ladder network was reported in [27]. To allow testing at multiple power levels, the use of MOS devices in triode region to achieve variable attenuation in the loopback with low area overhead presents an opportunity for future work. Depending on the communication standard, the loopback block might have to provide 40-100MHz frequency shifting between the transmitter and receiver sections; which necessitates an offset mixer. A practical loopback block design must also meet the following specifications for the specific communication standard/transceiver: input/output impedance matching, noise requirement at the sensitive LNA input, switches with high isolation, suppression of spurious tones below specified blocking levels, avoidance of mixing byproducts that saturate the LNA, and other relevant requirements.
Figure 3. Loopback Block
B. RMS Power Detector The use of power detectors has been demonstrated as an efficient way to implement BIST in the RF section of transceivers [23, 24]. The basic concept behind the RMS power detection is a three stage design. The first stage senses the RF signal and amplifies it to a desired level. This signal is then rectified and low-pass filtered in the second and third stages to generate a pseudo-rms equivalent DC output. Previous implementations of this structure have been reported in [15, 28]. The main limitation of all of these structures is the rectification stage. Several publications use a BJT-based rectification as in [29]. Even though the BJT approach is an elegant solution, it requires a BiCMOS technology. Most of the current research efforts are focused on implementing power detectors in RF CMOS technologies in which true BJTs are not available. To this end, a CMOSbased rectification was presented in [23]. The most promising approach utilizes a class AB rectification, which was first introduced in [30]. These CMOS rectifiers are limited by their small linear dynamic range, which is about 20dB. Fig. 4 shows the main concept behind the relative power measurement involving the output comparison of two RMS detectors. The gain and 1-dB compression points are indicated in the figure. All the tests described in section V can be realized with the addition of power detectors and offset mixers. Thus, enabling high fault coverage and feature extraction of RF front-ends by means of BIST.
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Figure 4. RMS Power detector gain and 1-dB compresion point
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