Studying the impact of gate tunneling on dynamic ... - Semantic Scholar
Studying the Impact of Gate Tunneling on Dynamic Behaviors of PartiallyDepleted SOI CMOS Using BSIMPD Pin Su, Samuel K. H. Fung*, Weidong Liu and Chenming Hu Department of EECS, University of California at Berkeley, CA 94720, USA *IBM SRDC, Hopewell Junction, NY 12533, USA [email protected]
In this work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.
individual blocks [3, 4, 5, 6]. Due to the self-biasing of the floating body, PD SOI circuits present idiosyncratic dynamic behaviors (e.g., history and frequency dependence of switching speed) that may increase the risk of inadequate circuit designs. With oxide scaling, the tunneling current [7, 8, 9] between the gate and the body introduces an element of complication to the history effect. BSIMPD (Berkeley Short-Channel IGFET Model Partial Depletion) [10, 11] is one SPICE model that attempts to fill the gap. With its built-in floating-body, self-heating and body-contact modules [10, 12], BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI circuits. The accuracy and robustness of BSIMPD have been verified and tested extensively in industry [13, 14, 15]. Since BSIMPD is physically accurate, we may further utilize it as a tool to study the impact of gate tunneling on SOI CMOS so that circuit designers may gain insight to fully exploit the performance leverage offered by SOI. In this paper we investigate the dynamic behavior of a static CMOS inverter, the basic building block of higher order logic circuits, with the aid of BSIMPD. Through a comparison of the circuit behavior, with and without gate current, we examine the impact of oxide tunneling current on dynamic behaviors of PD SOI CMOS circuits.
1. Introduction
2. Tunneling Mechanism
Scaling for high performance has set the stage for partially depleted (PD) SOI to become an important CMOS technology [1, 2]. PD SOI provides a performance gain of 20 to 35 percent over bulk CMOS [1] due to the reduction of junction capacitance and the absence of the body-bias effect in series connected devices, e.g. in NAND and NOR gates. With the same performance (constant delay), SOI can operate at a lower voltage and therefore emerges as a strong contender for low power applications as well. The main barrier to the acceptance of PD SOI by circuit designers, however, is the requirement of careful analysis for the impact of floating body effects on
The origin of SOI dynamic behaviors is the history dependence [16, 17, 18] of the floating body potential. Since the time constant of body charging is different for capacitive coupling, thermal generation and recombination, gate-induced-drain-leakage (GIDL), impact ionization [19], and oxide tunneling, the circuit representation of the floating body in Figure 1 is used in BSIMPD to capture the dynamic behavior of SOI. Among all the body currents, the oxide tunneling, Igb, is playing an increasingly crucial role as the oxide thickness is scaled down (below 25Å) [20]. Figure 2 shows the dominant tunneling mechanism (direct valence-band electron tunneling) responsible for the
Abstract
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
charging of the SOI floating body. The current density is shown in Figure 3. In this work we employ calibrated model parameters which are representative of state-ofthe-art PD SOI technologies (L = 0.13 µm, TSi = 160 nm, Tbox = 150 nm) to examine the impact of Igb.
4), since time constant (tp) for the PMOSFET to reach steady state is longer than tn due to smaller recombination current, net charge injection (the integration of net body current in Figure 4(c)) for the PMOSFET and thus the induced forward bias δVbp is larger than δVbn for NMOSFET.
Gate dQ g dt
Igb
I ii
Body
Drain 2
I bd dQs dt
dQd dt I bjt
dQ bg dt
BackGate
Figure 1. Circuit representation of the floating body. Igb: oxide tunneling current. Iii: impact ionization current. Igidl: gate induced drain leakage. Ibjt: bipolar current. Ibs: recombination current. Ibd: junction leakage.
P substrate
Jgb
10
2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
m e as ure m en t B S IM P D
1 4.5A
1 6.7A
T o x= 2 0A
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
V g (V )
Figure 3. Oxide tunneling current model used in this study. Jgb depends on Vg (Vdd) and physical oxide thickness Tox and agrees well with data [9]. P+ poly
Jgb
IgMod=0 IgMod=1
0.4
5µs
Vdd
Vdd
0
0
0
0.2
Vdd
Vdd
δVbn
0.1
0.0
0.0 (b)
(a) 0
5
10
15
0
5
time (µsec)
3. Impact on Transient Responses of MOSFETS
10
15
time (µsec)
(c)
tn
1.5
body current (nA)
Figure 4 shows the step turn-on response of a MOSFET. Without oxide tunneling, body charge falls off due to carrier recombination after the gate-to-body capacitive coupling is shielded by the surface inversion layer. With oxide tunneling current, Igb, body charging continues until Igb is counterbalanced by forward junction current after a finite amount of time. This time constant depends on the forward IV characteristics of body-source/drain diodes (for a given Igb), and determines the degree of body potential, δVbn and δVbp, of the MOSFETs in steady state. In this study (Figure
δVbp
0.2
0.1
Figure 2. Band diagrams showing the dominant oxide tunneling mechanism responsible for charging the floating body – valence-band electron tunneling.
5µs
0.3
NMOS V bs (V)
N substrate
IgMod=0 IgMod=1
0.4
0
0.3
N+ poly
3
PMOS V sb (V)
I bs
J g b (A /c m)
Source
I gidl
10
1.0
NMOS
tp
PMOS
0.5 recombination current
0.0
oxide tunneling current
0
5
10
15
time (µsec)
Figure 4. Impact of gate tunneling (IgMod=1) on the transient behavior of (a) NMOSFET, (b) PMOSFET, and (c) body current. (Vdd = 1.5 V, Tox = 14.5 Å, W = 5 µm)
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
0.8
(a)
0.6
NMOS V bs (V)
Two 500 MHz input signals (with a 0.1 nanosecond slew and 0.9 nanosecond pulse width), one starting from DC GND and one from Vdd, are applied sequentially to a CMOS inverter (Figure 5). Figure 6 shows the body voltages of the MOSFETs in the inverter through the first cycle. Both Vb0n in Figure 6(a) and Vb0p in Figure 6(c) are determined by diode IV characteristics (a balance between the reverse leakage current from the diode across the body to drain junction and the forward bias current of the diode across the body to source junction). Contrary to the transistors starting at OFF state, the body voltages of the transistors starting at ON state are raised by the gate current as shown in Figure 6(b) and (d).
1.0
0.4
0.2
0.5
Vb0n 0.0
0.0 -0.2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
time (nsec) (b)
NMOS V bs (V)
1.5 Vin
Vbs@IgMod=0 Vbs@IgMod=1
0.6
1.0
0.4
0.2
VCn
δVbn
0.5
Vin (V)
0.8
Vdd
D
1.5
Vin
Vbs@IgMod=0 Vbs@IgMod=1
Vin (V)
4. Impact on Dynamic Behaviors of CMOS Circuits
0.0 0.0 -0.2
PFET
0.5
1.0
2.5
Vsb@IgMod=0 Vsb@IgMod=1
(c) 0.8
C (V)
NFET
PMOS V
sb
B
0 Case A: the first switch (low-to-high) when Vin starts at 0 Case B: the second switch (low-to-high) when Vin starts at Vdd Case C: the first switch (high-to-low) when Vin starts at Vdd Case D: the second switch (high-to-low) when Vin starts at 0
3.0
Vin 1.5
0.6
1.0
0.4 0.5
0.2
Vb0p
0.0
0.0
-0.2
Figure 5. The inverter delay depends on the history of the applied signal. The first switch starts at 0.9 nsec with a 0.1 nsec slew. The pulse width is 0.9 nsec.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
time (nsec) 1.0
(d)
Vsb@IgMod=0 Vsb@IgMod=1
sb
(V)
0.8
PMOS V
The impact on the inverter falltime-delay (TDfall) is shown in Figure 7(a). When the input signal Vin starts at Vdd, the initial forward bias δVbn lowers VT and enhances the current drive of the NMOSFET and therefore shortens TDfall. As the Vbs prior to rising-input transition (Figure 7(b)) drifts to the steady state value due to junction diode current, TDfall becomes insensitive to the presence of oxide tunneling. On the other hand, when Vin starts at 0 the initial forward bias δVbp raises the junction capacitance (depletion and diffusion capacitances) of the PMOSFET and lengthens TDfall. As the Vsb of PMOSFET (Figure 7(c)) drops towards its steady state, this loading effect gradually disappears and TDfall settles to a slightly lower value due to higher steady-state NMOS-Vbs (Figure 7(b)) caused by gatecurrent charging. Figure 7(a) demonstrates that the range of TDfall difference between case A (defined in Figure 5) and
2.0
time (nsec)
Vout 1.0
Vdd
1.5
Vin (V)
Vin
0.0
Vin
VCp' δVbn (due to leakier NMOSFET junctions). When Vin starts at Vdd, on the other hand, the forward-bias loading effect is smaller than the risinginput case because δVbn < δVbp. Contrary to the long time constant it takes for TDrise to converge to its steady state due to small diode current of the PMOSFET, the gate current enlarges the history dependence of TDrise substantially. This is also reflected in the frequency dependence of the TDrise range (Figure 10), which occurs between case C (defined in Figure 5) and case D. Notice the 2X increase in delay range for (Vdd = 1.5 V, Tox = 20 Å, frequency = 500 MHz) resulting from the presence of the tunneling current.
V in s ta rts a t V d d 0 .0 2 0 Ig M o d = 0 Ig M o d = 1
0
500
1000
1500
35
r a n g e o f f a llt im e - d e la y ( % )
case B
0 .0 1 8
2000
tim e (n s e c )
0 .60
(b )
Ig M o d = 0 Ig M o d = 1
NMOS V p rio r to bs
ris in g -in p u t tra n sitio n (V )
0 .55 0 .50
δV bn
0 .45
V in sta rts a t V d d
0 .40
25 Ig M o d = 1 20
15
10
5
0 .30
V C n -V b 0 n
0
0 .25
Ig M o d = 0
0
500
1000
1500
(c )
2000
0 .3
V in s ta rts a t 0
δV bp
0 .1 0 .0 -0 .1 V in s ta rts a t V d d
-0 .2 -0 .3
100
1000
Figure 8. Frequency dependence of the falltime-delay range shows the deleterious impact of gate tunneling (Tox = 14.5 Å).
5. Conclusion
Ig M o d = 0 Ig M o d = 1
0 .4
0 .2
10
V in sta rts a t 0
tim e (n se c ) 0 .5
1
fr e q u e n c y ( M H z )
0 .15
PMOS V p rio r to sb
30
0 .35
0 .20
ris in g -in p u t tra n s itio n (V )
: V dd= 1 .5 V : V dd= 1 .4 V : V dd= 1 .3 V
0
500
1000
1500
2000
tim e (n s e c )
Figure 7. History dependence of (a) falltime-delay, (b) NFET-Vbs and (c) PFET-Vsb. Notice the crossover in (a) when Vin starts at 0.
Similarly, the initial forward bias δVbp improves the current drive of the PMOSFET and thus shortens the
We have investigated and analyzed the impact of gate tunneling on dynamic behaviors of SOI CMOS with the aid of BSIMPD. We examined the impact of gate tunneling on the floating-body effect, especially the history and frequency dependence of inverter delays. This study suggests that gate tunneling has a strong impact on the delay range of a PD SOI CMOS inverter. It is crucial for circuit designers to understand and contain this hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism is needed to quantify the effect without undermining the performance benefit of a PD SOI technology. BSIMPD is one model that attempts to enhance the design quality of SOI circuits. It has been implemented in Berkeley SPICE3f4 as well as HSPICE, SPECTRE, SmartSPICE, ELDO and so on.
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
r a n g e o f r is e t im e - d e la y ( % )
0 .0 3 2
(a ) case C
0 .0 2 8
0 .0 2 6
ra n g e o f Tris De
ris e tim e -d e la y (n s e c )
V in s ta rts a t V d d 0 .0 3 0
0 .0 2 4
V in s ta rts a t 0
0 .0 2 2 Ig M o d = 0 Ig M o d = 1
case D
0 .0 2 0
0
500
1000
1500
35 : T o x = 1 4 .5 A : T o x = 1 6 .7 A : T o x = 2 0 .0 A
30
25
20
Ig M o d = 1
15
10
5
Ig M o d = 0
2000
0
tim e (n s e c )
1
10
100
1000
fr e q u e n c y ( M H z )
NMOS V p rio r to bs
fa llin g -in p u t tra n s itio n (V )
0 .3
(c )
Ig M o d = 0 Ig M o d = 1
0 .2
0 .1
δV bn
V in s ta rts a t V d d
7. References
0 .0
-0 .1
V in s ta rts a t 0
-0 .2
-0 .3
0
500
1000
1500
2000
tim e (n s e c )
PMOS V p rio r to sb
0 .8
fa llin g -in p u t tra n s itio n (V )
Figure 10. Frequency dependence of the risetime-delay range shows the deleterious impact of gate tunneling (Vdd = 1.5 V).
(b )
Ig M o d = 0 Ig M o d = 1
0 .7
V in s ta rts a t 0
δV bp 0 .6 0 .5 0 .4
V C p -V b 0 p 0 .3 V in s ta rts a t V d d 0 .2 0
500
1000
1500
2000
tim e (n s e c )
Figure 9. History dependence of (a) risetime-delay, (b) PFET-Vsb and (c) NFET-Vbs. Notice the crossover in (a) when Vin starts at Vdd.
[1] G. Shahidi et al., Tech. Digest ISSCC, p. 426, 1999. [2] I. Yang et al., Tech. Digest IEDM, pp. 431-434, 1999. [3] C. Chuang et al., Proc. IEEE, vol. 86, p. 689, 1998. [4] F. Assaderaghi et al., The 12th Int. Conf. on Microelectronics, p. 201, 2000. [5] K. Shepard et al., IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 20, no. 7, p. 888, July 2001. [6] K. Shepard et al., IEEE 2001 2nd International Symposium on Quality Electronic Design, pp. 105-110, 2001. [7] C. Hu, Tech. Digest IEDM, pp. 319-322, 1996. [8] W. Lee et al., Symposium on VLSI Tech, pp.198-199, 2000. [9] A. Shanware et al., Tech. Digest IEDM, pp. 815-818, 1999. [10] P. Su et al., Tech. Digest CICC, pp. 197-200, 2000. [11] www-device.eecs.berkeley.edu/~bsimsoi [12] P. Su et al., Int. SOI Conf., pp. 50-51, 1999. [13] S. Fung et al., Symposium on VLSI Tech, pp. 206-207, 2000. [14] H. Nakayama et al., Tech. Digest CICC, pp. 381-384, 2001. [15] K. Goto et al., Int. SOI Conf., pp. 55-56, 2001. [16] A. Wei et al., IEEE EDL, vol. 16, p. 494, Nov. 1995. [17] J. Gautier et al., IEEE EDL, vol. 16, p. 497, Nov. 1995. [18] A. Wei et al., Tech. Digest IEDM, pp. 411-414, 1997. [19] P. Su et al., Int. SOI Conf., pp 31-32, 2001. [20] S. Fung et al., Tech. Digest IEDM, pp. 231-234, 2000.
6. Acknowledgement This work is supported by the SRC under contract 2000NJ-795.
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
In this work, we investigate and analyze the impact of gate tunneling on dynamic behaviors of partially depleted SOI CMOS with the aid of the physically accurate BSIMPD model. We examine in particular the impact of gate tunneling on the history dependence of inverter delays. The examination reveals key requirements for capturing the history effect in SPICE modeling. This study suggests that gate tunneling has a strong impact on the delay range and should be considered in SOI circuit simulation. It is crucial for circuit designers to understand and contain the hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism should be used to quantify the effect without undermining the performance benefit of a partially depleted SOI technology. BSIMPD is one model that attempts to bridge the gap between advanced SOI technologies and circuit design. With its built-in floating-body, self-heating and body-contact modules, BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI chips. BSIMPD has been implemented in Berkeley SPICE3f4 and other commercial SPICE simulators. It may also be the basis for computing the look-up tables used for higher-level timing simulation.
individual blocks [3, 4, 5, 6]. Due to the self-biasing of the floating body, PD SOI circuits present idiosyncratic dynamic behaviors (e.g., history and frequency dependence of switching speed) that may increase the risk of inadequate circuit designs. With oxide scaling, the tunneling current [7, 8, 9] between the gate and the body introduces an element of complication to the history effect. BSIMPD (Berkeley Short-Channel IGFET Model Partial Depletion) [10, 11] is one SPICE model that attempts to fill the gap. With its built-in floating-body, self-heating and body-contact modules [10, 12], BSIMPD captures SOI-specific effects and therefore is able to raise the design quality of PD SOI circuits. The accuracy and robustness of BSIMPD have been verified and tested extensively in industry [13, 14, 15]. Since BSIMPD is physically accurate, we may further utilize it as a tool to study the impact of gate tunneling on SOI CMOS so that circuit designers may gain insight to fully exploit the performance leverage offered by SOI. In this paper we investigate the dynamic behavior of a static CMOS inverter, the basic building block of higher order logic circuits, with the aid of BSIMPD. Through a comparison of the circuit behavior, with and without gate current, we examine the impact of oxide tunneling current on dynamic behaviors of PD SOI CMOS circuits.
1. Introduction
2. Tunneling Mechanism
Scaling for high performance has set the stage for partially depleted (PD) SOI to become an important CMOS technology [1, 2]. PD SOI provides a performance gain of 20 to 35 percent over bulk CMOS [1] due to the reduction of junction capacitance and the absence of the body-bias effect in series connected devices, e.g. in NAND and NOR gates. With the same performance (constant delay), SOI can operate at a lower voltage and therefore emerges as a strong contender for low power applications as well. The main barrier to the acceptance of PD SOI by circuit designers, however, is the requirement of careful analysis for the impact of floating body effects on
The origin of SOI dynamic behaviors is the history dependence [16, 17, 18] of the floating body potential. Since the time constant of body charging is different for capacitive coupling, thermal generation and recombination, gate-induced-drain-leakage (GIDL), impact ionization [19], and oxide tunneling, the circuit representation of the floating body in Figure 1 is used in BSIMPD to capture the dynamic behavior of SOI. Among all the body currents, the oxide tunneling, Igb, is playing an increasingly crucial role as the oxide thickness is scaled down (below 25Å) [20]. Figure 2 shows the dominant tunneling mechanism (direct valence-band electron tunneling) responsible for the
Abstract
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
charging of the SOI floating body. The current density is shown in Figure 3. In this work we employ calibrated model parameters which are representative of state-ofthe-art PD SOI technologies (L = 0.13 µm, TSi = 160 nm, Tbox = 150 nm) to examine the impact of Igb.
4), since time constant (tp) for the PMOSFET to reach steady state is longer than tn due to smaller recombination current, net charge injection (the integration of net body current in Figure 4(c)) for the PMOSFET and thus the induced forward bias δVbp is larger than δVbn for NMOSFET.
Gate dQ g dt
Igb
I ii
Body
Drain 2
I bd dQs dt
dQd dt I bjt
dQ bg dt
BackGate
Figure 1. Circuit representation of the floating body. Igb: oxide tunneling current. Iii: impact ionization current. Igidl: gate induced drain leakage. Ibjt: bipolar current. Ibs: recombination current. Ibd: junction leakage.
P substrate
Jgb
10
2
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
m e as ure m en t B S IM P D
1 4.5A
1 6.7A
T o x= 2 0A
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
V g (V )
Figure 3. Oxide tunneling current model used in this study. Jgb depends on Vg (Vdd) and physical oxide thickness Tox and agrees well with data [9]. P+ poly
Jgb
IgMod=0 IgMod=1
0.4
5µs
Vdd
Vdd
0
0
0
0.2
Vdd
Vdd
δVbn
0.1
0.0
0.0 (b)
(a) 0
5
10
15
0
5
time (µsec)
3. Impact on Transient Responses of MOSFETS
10
15
time (µsec)
(c)
tn
1.5
body current (nA)
Figure 4 shows the step turn-on response of a MOSFET. Without oxide tunneling, body charge falls off due to carrier recombination after the gate-to-body capacitive coupling is shielded by the surface inversion layer. With oxide tunneling current, Igb, body charging continues until Igb is counterbalanced by forward junction current after a finite amount of time. This time constant depends on the forward IV characteristics of body-source/drain diodes (for a given Igb), and determines the degree of body potential, δVbn and δVbp, of the MOSFETs in steady state. In this study (Figure
δVbp
0.2
0.1
Figure 2. Band diagrams showing the dominant oxide tunneling mechanism responsible for charging the floating body – valence-band electron tunneling.
5µs
0.3
NMOS V bs (V)
N substrate
IgMod=0 IgMod=1
0.4
0
0.3
N+ poly
3
PMOS V sb (V)
I bs
J g b (A /c m)
Source
I gidl
10
1.0
NMOS
tp
PMOS
0.5 recombination current
0.0
oxide tunneling current
0
5
10
15
time (µsec)
Figure 4. Impact of gate tunneling (IgMod=1) on the transient behavior of (a) NMOSFET, (b) PMOSFET, and (c) body current. (Vdd = 1.5 V, Tox = 14.5 Å, W = 5 µm)
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
0.8
(a)
0.6
NMOS V bs (V)
Two 500 MHz input signals (with a 0.1 nanosecond slew and 0.9 nanosecond pulse width), one starting from DC GND and one from Vdd, are applied sequentially to a CMOS inverter (Figure 5). Figure 6 shows the body voltages of the MOSFETs in the inverter through the first cycle. Both Vb0n in Figure 6(a) and Vb0p in Figure 6(c) are determined by diode IV characteristics (a balance between the reverse leakage current from the diode across the body to drain junction and the forward bias current of the diode across the body to source junction). Contrary to the transistors starting at OFF state, the body voltages of the transistors starting at ON state are raised by the gate current as shown in Figure 6(b) and (d).
1.0
0.4
0.2
0.5
Vb0n 0.0
0.0 -0.2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
time (nsec) (b)
NMOS V bs (V)
1.5 Vin
Vbs@IgMod=0 Vbs@IgMod=1
0.6
1.0
0.4
0.2
VCn
δVbn
0.5
Vin (V)
0.8
Vdd
D
1.5
Vin
Vbs@IgMod=0 Vbs@IgMod=1
Vin (V)
4. Impact on Dynamic Behaviors of CMOS Circuits
0.0 0.0 -0.2
PFET
0.5
1.0
2.5
Vsb@IgMod=0 Vsb@IgMod=1
(c) 0.8
C (V)
NFET
PMOS V
sb
B
0 Case A: the first switch (low-to-high) when Vin starts at 0 Case B: the second switch (low-to-high) when Vin starts at Vdd Case C: the first switch (high-to-low) when Vin starts at Vdd Case D: the second switch (high-to-low) when Vin starts at 0
3.0
Vin 1.5
0.6
1.0
0.4 0.5
0.2
Vb0p
0.0
0.0
-0.2
Figure 5. The inverter delay depends on the history of the applied signal. The first switch starts at 0.9 nsec with a 0.1 nsec slew. The pulse width is 0.9 nsec.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
time (nsec) 1.0
(d)
Vsb@IgMod=0 Vsb@IgMod=1
sb
(V)
0.8
PMOS V
The impact on the inverter falltime-delay (TDfall) is shown in Figure 7(a). When the input signal Vin starts at Vdd, the initial forward bias δVbn lowers VT and enhances the current drive of the NMOSFET and therefore shortens TDfall. As the Vbs prior to rising-input transition (Figure 7(b)) drifts to the steady state value due to junction diode current, TDfall becomes insensitive to the presence of oxide tunneling. On the other hand, when Vin starts at 0 the initial forward bias δVbp raises the junction capacitance (depletion and diffusion capacitances) of the PMOSFET and lengthens TDfall. As the Vsb of PMOSFET (Figure 7(c)) drops towards its steady state, this loading effect gradually disappears and TDfall settles to a slightly lower value due to higher steady-state NMOS-Vbs (Figure 7(b)) caused by gatecurrent charging. Figure 7(a) demonstrates that the range of TDfall difference between case A (defined in Figure 5) and
2.0
time (nsec)
Vout 1.0
Vdd
1.5
Vin (V)
Vin
0.0
Vin
VCp' δVbn (due to leakier NMOSFET junctions). When Vin starts at Vdd, on the other hand, the forward-bias loading effect is smaller than the risinginput case because δVbn < δVbp. Contrary to the long time constant it takes for TDrise to converge to its steady state due to small diode current of the PMOSFET, the gate current enlarges the history dependence of TDrise substantially. This is also reflected in the frequency dependence of the TDrise range (Figure 10), which occurs between case C (defined in Figure 5) and case D. Notice the 2X increase in delay range for (Vdd = 1.5 V, Tox = 20 Å, frequency = 500 MHz) resulting from the presence of the tunneling current.
V in s ta rts a t V d d 0 .0 2 0 Ig M o d = 0 Ig M o d = 1
0
500
1000
1500
35
r a n g e o f f a llt im e - d e la y ( % )
case B
0 .0 1 8
2000
tim e (n s e c )
0 .60
(b )
Ig M o d = 0 Ig M o d = 1
NMOS V p rio r to bs
ris in g -in p u t tra n sitio n (V )
0 .55 0 .50
δV bn
0 .45
V in sta rts a t V d d
0 .40
25 Ig M o d = 1 20
15
10
5
0 .30
V C n -V b 0 n
0
0 .25
Ig M o d = 0
0
500
1000
1500
(c )
2000
0 .3
V in s ta rts a t 0
δV bp
0 .1 0 .0 -0 .1 V in s ta rts a t V d d
-0 .2 -0 .3
100
1000
Figure 8. Frequency dependence of the falltime-delay range shows the deleterious impact of gate tunneling (Tox = 14.5 Å).
5. Conclusion
Ig M o d = 0 Ig M o d = 1
0 .4
0 .2
10
V in sta rts a t 0
tim e (n se c ) 0 .5
1
fr e q u e n c y ( M H z )
0 .15
PMOS V p rio r to sb
30
0 .35
0 .20
ris in g -in p u t tra n s itio n (V )
: V dd= 1 .5 V : V dd= 1 .4 V : V dd= 1 .3 V
0
500
1000
1500
2000
tim e (n s e c )
Figure 7. History dependence of (a) falltime-delay, (b) NFET-Vbs and (c) PFET-Vsb. Notice the crossover in (a) when Vin starts at 0.
Similarly, the initial forward bias δVbp improves the current drive of the PMOSFET and thus shortens the
We have investigated and analyzed the impact of gate tunneling on dynamic behaviors of SOI CMOS with the aid of BSIMPD. We examined the impact of gate tunneling on the floating-body effect, especially the history and frequency dependence of inverter delays. This study suggests that gate tunneling has a strong impact on the delay range of a PD SOI CMOS inverter. It is crucial for circuit designers to understand and contain this hysteretic delay variations caused by gate current. An accurate SPICE model that includes the oxide tunneling mechanism is needed to quantify the effect without undermining the performance benefit of a PD SOI technology. BSIMPD is one model that attempts to enhance the design quality of SOI circuits. It has been implemented in Berkeley SPICE3f4 as well as HSPICE, SPECTRE, SmartSPICE, ELDO and so on.
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
r a n g e o f r is e t im e - d e la y ( % )
0 .0 3 2
(a ) case C
0 .0 2 8
0 .0 2 6
ra n g e o f Tris De
ris e tim e -d e la y (n s e c )
V in s ta rts a t V d d 0 .0 3 0
0 .0 2 4
V in s ta rts a t 0
0 .0 2 2 Ig M o d = 0 Ig M o d = 1
case D
0 .0 2 0
0
500
1000
1500
35 : T o x = 1 4 .5 A : T o x = 1 6 .7 A : T o x = 2 0 .0 A
30
25
20
Ig M o d = 1
15
10
5
Ig M o d = 0
2000
0
tim e (n s e c )
1
10
100
1000
fr e q u e n c y ( M H z )
NMOS V p rio r to bs
fa llin g -in p u t tra n s itio n (V )
0 .3
(c )
Ig M o d = 0 Ig M o d = 1
0 .2
0 .1
δV bn
V in s ta rts a t V d d
7. References
0 .0
-0 .1
V in s ta rts a t 0
-0 .2
-0 .3
0
500
1000
1500
2000
tim e (n s e c )
PMOS V p rio r to sb
0 .8
fa llin g -in p u t tra n s itio n (V )
Figure 10. Frequency dependence of the risetime-delay range shows the deleterious impact of gate tunneling (Vdd = 1.5 V).
(b )
Ig M o d = 0 Ig M o d = 1
0 .7
V in s ta rts a t 0
δV bp 0 .6 0 .5 0 .4
V C p -V b 0 p 0 .3 V in s ta rts a t V d d 0 .2 0
500
1000
1500
2000
tim e (n s e c )
Figure 9. History dependence of (a) risetime-delay, (b) PFET-Vsb and (c) NFET-Vbs. Notice the crossover in (a) when Vin starts at Vdd.
[1] G. Shahidi et al., Tech. Digest ISSCC, p. 426, 1999. [2] I. Yang et al., Tech. Digest IEDM, pp. 431-434, 1999. [3] C. Chuang et al., Proc. IEEE, vol. 86, p. 689, 1998. [4] F. Assaderaghi et al., The 12th Int. Conf. on Microelectronics, p. 201, 2000. [5] K. Shepard et al., IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 20, no. 7, p. 888, July 2001. [6] K. Shepard et al., IEEE 2001 2nd International Symposium on Quality Electronic Design, pp. 105-110, 2001. [7] C. Hu, Tech. Digest IEDM, pp. 319-322, 1996. [8] W. Lee et al., Symposium on VLSI Tech, pp.198-199, 2000. [9] A. Shanware et al., Tech. Digest IEDM, pp. 815-818, 1999. [10] P. Su et al., Tech. Digest CICC, pp. 197-200, 2000. [11] www-device.eecs.berkeley.edu/~bsimsoi [12] P. Su et al., Int. SOI Conf., pp. 50-51, 1999. [13] S. Fung et al., Symposium on VLSI Tech, pp. 206-207, 2000. [14] H. Nakayama et al., Tech. Digest CICC, pp. 381-384, 2001. [15] K. Goto et al., Int. SOI Conf., pp. 55-56, 2001. [16] A. Wei et al., IEEE EDL, vol. 16, p. 494, Nov. 1995. [17] J. Gautier et al., IEEE EDL, vol. 16, p. 497, Nov. 1995. [18] A. Wei et al., Tech. Digest IEDM, pp. 411-414, 1997. [19] P. Su et al., Int. SOI Conf., pp 31-32, 2001. [20] S. Fung et al., Tech. Digest IEDM, pp. 231-234, 2000.
6. Acknowledgement This work is supported by the SRC under contract 2000NJ-795.
Proceedings of the International Symposium on Quality Electronic Design (ISQED’02) 0-7695-1561-4/02 $17.00 © 2002 IEEE
