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APPLIED PHYSICS LETTERS 101, 193109 (2012)

The selective removal of metallic carbon nanotubes from As-grown arrays on insulating substrates Andrew Tunnell,1,2 Vincent Ballarotto,1 and John Cumings3 1

Laboratory for Physical Sciences, University of Maryland, College Park, Maryland 20742, USA Department of Physics, University of Maryland, College Park, Maryland 20742, USA 3 Department of Materials Science and Engineering, University of Maryland, College Park, Maryland 20742, USA 2

(Received 9 September 2012; accepted 18 October 2012; published online 9 November 2012) We present a method of selectively removing metallic single-walled carbon nanotubes (SWCNTs) from as-grown arrays on quartz substrates. The process utilizes an external silicon piece as a temporary global top gate to increase the resistance of the semiconducting SWCNTs while current is passed through the metallic SWCNTs, causing electrical breakdown through joule heating. The resulting SWCNT field-effect transistors (FETs) consistently produce on/off current ratios greater than 1000. Additionally, we find that the high frequency parasitic losses between 1 GHz and 6 GHz on the completed SWCNT FETs are significantly lower than on comparable SWCNT FETs fabricated C 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4765661] on silicon substrates. V The unique electronic properties of single-walled carbon nanotubes (SWCNTs) have made them a leading candidate for nanoelectronic devices. Common techniques for synthesizing SWCNTs (arc discharge,1 laser ablation,2 and chemical vapor deposition (CVD)3–6) produce a mixture of tubes which typically contain twice as many semiconducting tubes as metallic tubes.7 However, the presence of metallic SWCNTs in the active channel of a device can be problematic, producing a low on/off current ratio, typically near three for most as-grown SWCNT networks. For certain applications, a larger on/off ratio may be necessary for proper transistor operation. The presence of metallic tubes also means that an undesirable amount of current can leak through the channel even when the semiconducting SWCNTs are gated off. The inability of the transistor to be properly turned off means that appreciable power drain can arise, a concern for potential low power applications. One method of increasing the as-grown on/off ratio is to use low density (10 000, while that of the as-grown device was 103). Nevertheless, the losses in the high frequency range (1 to 6 GHz) of the completed devices on quartz are significantly improved in comparison with as-grown SWCNT FETs on silicon. The procedure presented here is robust and can be scaled to wafer-sized processes. It is also general enough to be used with other insulating substrates. Furthermore, high on/off SWCNT FETs can be fabricated on substrates that are more compatible with high frequency applications than silicon, and thus enabling potential low power SWCNT FET technology in the high frequency regime. 1

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