Translinear Loop Principle and Identification of the ... - Semantic Scholar
Translinear Loop Principle and Identification of the Translinear Loops Cheng Yuhua, Wu Xiaobo, Yan Xiaolang Institute of VLSI Design, Zhejiang University Hangzhou 310027, China Email: {chengyh, wuxb, yan}j vlsi.zju.edu.cn Abstract The principle of hybrid translinear (HTL) loop was presented, which made the principle of translinear (TL) loop be more complete. By proposing a method of decomposing an MOS transistor operated in triode region into two MOS transistors operated in saturation region, the principle of TL loop was simplified and the graphical equivalent topology was extended. In addition, the topological method to identify TL loops involved in translinear cell was successfully extended to all types of TL loops especially to HTL loop.
Keywords translinear loop principle, hybrid integrated circuit, transistor model, topological method
I.
INTRODUCTION
The translinear (TL) principle proposed by Gilbert in 1975 is one of the important contributions to circuit theory in the electronics era, which provides a way to analyze and synthesize circuits in BJTs that exploit the exponential current-voltage characteristic [1]. With the development of CMOS technology, the translinear principle of MOS transistors in weak inversion exploiting exponential current-voltage characteristic and in strong inversion exploiting square current-voltage are also presented [2]-[4]. The characteristic of MOS transistors in weak inversion is similar to BJTs for they all obey exponential law. Usually MOS transistors are seldom designed to work in weak inversion since the limited dynamic range and quite low speed. But in low voltage low power applications it has bright prospect. The dynamic translinear circuits were presented in some papers like [5], but they are beyond this paper. Now, due to the rapid development of the Integrated Circuit technology including BiCMOS technology, hybrid translinear (HTL) circuits [9] which comprise both BJTs and MOS transistors are becoming more and more important for their high performance of combining the merits of BJTs and MOS transistors. So it is necessary to analyze the principle of HTL circuits. In this paper, the principles of three types of TL circuit: BJTs translinear (BTL) circuits, MOS transistors translinear (MTL) circuits and HTL circuits, are all given out in section II which are simplified by the modes of transistors in section III. This work is sponsored by the National Natural Science Foundation of China under grant No.50237030 and 90207001. It also gains support from the National Semiconductor Corp. (NSC).
A graphical representation and topological method to identify the multiple static translinear is presented in [6] in which the MOS transistors are in weak inversion. In section III the graphical representation is extended to MOS transistors in strong inversion and the topological method is extended to all the TL circuits especially to HTL circuits in section IV. II. TANSLINEAR LooP PRINCIPLE As well known, there are two topologies of TL circuits, updown and stacked topology [7]. They obey the same principle according to KVL. For simplicity the body effect of MOS transistors is not considered because it can be canceled by connecting the source to substrate.
A. BTL Circuit Principle The BTL circuit principle has been derived by Gilbert [1]. In a BTL loop with equal numbers of transistors arranged clockwise and counterclockwise. This is an essential requirement. From KVL, the BTL loop follows
ZVbe cw
(1)
ccw
Where, cw and ccw refer to the connected directions of the devices, clockwise and counterclockwise respectively. Substitute the expression of Vb, to (1),
ZVT ln(Ic/I) JVT ln(Ic /I). cw
(2)
ccw
Where IC and IS are collector current and saturation current, respectively. VT is the thermal voltage approximately 26mV at room temperature. For simplicity, all the Is are equal, so = tI I(3) HI~HIc cw
ccw
B. MTL Circuit Principle MOS transistor can work in weak inversion or in strong inversion and can work in saturated region or triode region. So there are many types of MTL circuit in theoretically. Usually, the MOS transistors are in saturated region and strong inversion, but as the requirement of low voltage the MOS transistors in triode region or weak inversion are used. The weak inversion transistors and strong inversion transistors have
1667
1-4244-0387-1/06/$20.00 (@2006 IEEE
ZVbe
not been in a TL loop until now. So we can focus on the weak inversion MTL loop or strong inversion MTL loop. The usage of transistors in triode region is few especially in TL loop for the limit of the disadvantage like nonlinearity, low gain and the drain current is not only related to the gate-source voltage but also the drain-source voltage. The transistors in triode region the current-voltage characteristic is more complex than in saturated region ones. Fortunately, triode region transistor (regardless in weak inversion or strong inversion) can be decomposed to two saturate devices as shown in section III. The expense is that the two devices will not in the same TL loop, but it simplify the analysis and is suited to some application [8]. As a result, there are only two types of MOS principle. The MTL circuit principle in weak inversion [6] is
IVgs =ZV cw
K ln(Id
(4)
I,) =K ln(Id /IIo)
(5)
Where K is equal to nVT, n approximates 1.5. Id and IO are the drain current and transistor current (similar to IS in BJT), respectively. Similar to BTL circuit, (5) is simplified to (6) if all lo s are equal.
(6)
= J7d
J'd
The MTL circuit principle in strong inversion derived in [4] is shown in (7) Where VTH is the threshold voltage and , is the coefficient of device. cw
Z('VTH +
VTH + 21d)
ccw
/2d lA)
(7)
For simplicity, all the MOS transistors are NMOS and the are all equal respectively.
VTH, ,
=d
Z cw
Z Vgs cw + n
g
(8)
ccw
Today, transistors working in strong inversion have an I-V relationship that is frequently no longer given by a pure quadratic relationship. More generally it is a power function:
Id = 0. 5,: (v s VTH )*(9)
Y (Id ) cw
=
Y (Id )
lln
(10)
ccw
C. HTL Circuit Principle Hybrid translinear loop contains BJTs and MOS transistors. Because of the different laws BJTs and MOS transistors obeyed, the HTL loop will be complex. Usually the numbers of BJTs or MOS transistors in clockwise and counterclockwise are equal for symmetry. Theoretically, bipolar transistors in saturated region will not be used in analog circuit in generally. And the MOS transistors in HTL loop work in weak inversion or strong inversion whose application is much more popular,
1668
Vbecw
=
E
n
Vgs,ccw +
E
m
Vbe,ccw
Y (vg"cw Vgs,ccw ) Y (Vbe,ccw Vbe,cw )
(11)
(12)
=
n
m
For the situation the MOS transistors in weak inversion,
KY[n In
Io,
I
In
Io,cw
Id
KZ[(lnI d),, -(lnId)]
s c ws"I,w
=Vi [lnn ijn
m
(13)
(ln)]. (14)
V Z(ln)
n
m
For the situation the MOS transistors in strong inversion, 2
P
1
[(j ),. (Cd )". ]
=
V, Y m
In
II, c
""
-
(15)
I Inc
is
C',
A2 f )w()c;V (1 C)C 1 C)0
( 16)
Now, the principles of three types are all given out. The BTL and MTL principle have been presented before and the HTL principle is important and useful as the development of BiCMOS technology. The HTL principle has been applied in
[9].
III. MODELS FOR TRANSISTORS The graphical equivalents for BJTs and MOS transistors in weak inversion have been depicted in [6]. MOS transistors can work in saturation or triode region regardless in weak inversion or strong inversion. The MOS transistor in triode region can be decomposed into two saturated devices connected anti-parallel regardless in weak inversion which has been given out in [8] or strong inversion which will be presented as follow. The drain current of the MOS transistor can be expressed as (17) and (18), corresponding to the device in saturated and triode region in strong inversion respectively.
Id =0 .5(V VTH) JIO= .502(Vgs VTH )L H V2]
The principle is modified to (10) easily through replacing the square root 1/2 with 1 n in this condition. lln
E
m
Where n is the number of MOS transistor in clockwise or counterclockwise, and m is the number referred to BJTs. Changing (1 1) to (12) will be benefit.
ccw
ccw
cw
resulting in that the principle is different in form. Both situations follow
(17) (18)
Through a simple change of (18), there is an iiinteresting result.
IdO= 0.56L (vg VTH ) (vgd VTH)2
(19)
That means the drain current of a triode region MOS transistor is equal to the drain current difference of two MOS transistors operated in saturated region: (20) Id = Idl Id2' So the decomposition method in Fig. 1 is approved to be reasonable.
APCCAS 2006
This result reduces the complexity of principle of TL loop and also the graphical equivalent of MOS transistor. A. Graphical Equivalentfor BJTs The graphical equivalent of NPN BJT contains an edge shown in Fig. 2. PNP BJT has similar equivalent besides the inverted direction of the edge. B. Graphical Equivalentfor MOS transistors The MOS transistor in weak inversion can be represented by a pair of edges in saturated region shown in Fig. 3(a) and by a set of four edges in triode region shown in Fig. 3(b). The graphical equivalent of MOS transistor in strong inversion is similar to the MOS transistor in weak inversion. The saturated and triode region transistors are represented in Fig. 4(a) and Fig. 4(b). IV. IDENTIFYING THE TRANSLINEAR Loop In the base of the graphical equivalent of bipolar and MOS transistors, the translinear loop can be depicted by different edges and vertexes. This topology method uniforms three types of TL loop in form. In actually, they are uniformed according S
D
D
.
G
G S
G 1
S
(a)
X S (c)
(b)
Figure 1. (a) Triode region NMOS transistor (b) Two saturated region NMOS transistors connected anti-parallel (c) Another form of (b) C B
E
DBE E
D
G G
D G
G
B
S
EGS
EBS
G-
I.
D
G
S
EBS
S B (b) Triode region (a) Saturated region Figure 3. Graphical equivalent for NMOS transsistor in weak inversion S B
FGS
FGD G
B
FBS
(a) Saturated region
D
FGS
G
S B
FBD FBS
S
(b) Triode region
Figure 4. Graphical equivalent for NMOS transistor in strong inversion
to the characteristic of BJT differential pair and MOS transistor differential pair in [9]. BJT differential pair and MOS differential pair can replace each other qualitatively. Because a TL loop can be decomposed to two differential pairs, so the three types of TL loop are uniformed in circuit analysis and also in topology. Using the topological method, it is convenient to identify the devices involved in each translinear loop [6]. Although [6] is not complete, the definitions and propertied in [6] all can be extended to the MTL loop in saturated region of strong inversion and HTL loop. Considering to the MTL loop whose transistors are in triode region, they are used in low voltage low power applications. Some applications are presented in [8]. As a simple example of HTL loop, a class AB output stage containing two HTL loops is drawn in Fig. 5 [9]. The three HTL loops M1-Q11-M14-Q12, M1-Q11-M13-Q9 and M14Q12-M13-Q9 realize the quiescent current control and get better effect than onefold BTL or MTL loops. In analysis, the HTL loops cell can be abstracted from the output stage using the topology method shown in Fig. 6. There are two fundamental translinear loops according to the property [6]: The number of fundamental translinear loop L is given by L = NTE - NV 1 where NTE is the number of translinear elements and NV is the number of vertices of the circuit. Here L = 6 - 5 + 1 = 2. So one TL loop is trivial and the other two TL loops are fundamental which are coupled directly. The definitions of fundamental and trivial TL loop are shown in [6]. So in actually it just needs two TL loops in analysis which simplify the analysis. Fig. 7 shows the two TL loops. And finally the quiescent current and residual current can be driven out through the two HTL loops [9]. V.
EGD EBD _EGD, EBO EGS
S
(S B
Figure 2. Graphical equivalent NPN bi[polar transistor
D
D
CONCLUSION
In this paper the principle of HTL circuit was presented in detail. It made the principles of TL circuits be more complete. And a new method was proposed to decompose the MOS transistor operated in triode region into two transistors operated in saturated region and simplified this principles. On the other hand, the topological method to identify the TL loops was extended to all of the three types of TL loops especially to HTL one, which is based on the graphical equivalents of transistors. Finally, as an example, an HTL circuit applied to quiescent current control of class AB output stage was analyzed.
APCCAS 2006
1669
R. V. Bemal, A. S. Reyes and W. A. Serdijn, "Identifying translinear loops in the circuit topology," ISCAS 2000 IEEE International Symposium on Circuits and Systems, May 28-31, 2000. [7] R. J. Wiegerink, Analysis and synthesis of MOS translinear circuits. Norwell, MA: Kluwer, 1993. E. Seevinck, E. Vittoz, M. du Plessis, T.-H. Joubert, and WBeetge, . "CMOS translinear circuits for minimum supply voltage," IEEE Transactions on Circuits and Systems 11, 47(12):1560 1564, December 2000. [9] Cheng Yuhua, Wu Xiaobo, Yan Xiaolang, "Analysis of hybrid translinear circuit and its application," International MultiConference of Engineers and Computer Scientists 2006, Hong Kong, June 20-22, 2006.
[6]
vcc
0
_
IV13
.
07
r5
06
04
S
,;
'
A
htL14 A
........[8] Vout
08 QS
VEE
Figure 5. Class AB output stage
DBE9
DBEI
ESG13
DBE12I
ESG1 ESG14 Figure 6. Translinear loops in the circuit of Fig. 5
DBE9
DBE9 DBE1I
ESG13
ESG13
ESGl
DBE12
ESG14
Figure 7. Two fundamental translinear loops in Fig. 6
ACKNOWLEDGMENT
The author would like to thank Mr. David Pace and Mr. Kalon Chu, the senior engineers of NSC, for their useful discussion and instruction. REFERENCES [1] [2]
[3]
[4] [5]
B. Gilbert, "Translinear circuits: a proposed classification," Electron. Lett., vol. 11, no. 1, pp. 14-16, 1975. T. S. Gotarredona, B. L. Barranco, and A. G. Andreou, "A general subthreshold MOS translinear theorem," in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI, vol. 2. Piscataway, NJ: IEEE, 1999, pp. 302-305. T. S. Gotarredona, B. L. Barranco, and A. G. Andreou, "A general translinear principle for subthreshold MOS transistors," IEEE Transcactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 46, no. 5, May 1999. E. Seevinck and R. J. Wiegerink, "Generalized translinear circuit principle," IEEE J. Solid-State Circuits, vol. 26, no. 8, August 1991. J. Mulder, W. A. Serdijn, A. C. Vander Woerd, "A generalized class of dynamic translinear circuits," IEEE Transcactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, no. 5, May 2001.
1670
APCCAS 2006
Keywords translinear loop principle, hybrid integrated circuit, transistor model, topological method
I.
INTRODUCTION
The translinear (TL) principle proposed by Gilbert in 1975 is one of the important contributions to circuit theory in the electronics era, which provides a way to analyze and synthesize circuits in BJTs that exploit the exponential current-voltage characteristic [1]. With the development of CMOS technology, the translinear principle of MOS transistors in weak inversion exploiting exponential current-voltage characteristic and in strong inversion exploiting square current-voltage are also presented [2]-[4]. The characteristic of MOS transistors in weak inversion is similar to BJTs for they all obey exponential law. Usually MOS transistors are seldom designed to work in weak inversion since the limited dynamic range and quite low speed. But in low voltage low power applications it has bright prospect. The dynamic translinear circuits were presented in some papers like [5], but they are beyond this paper. Now, due to the rapid development of the Integrated Circuit technology including BiCMOS technology, hybrid translinear (HTL) circuits [9] which comprise both BJTs and MOS transistors are becoming more and more important for their high performance of combining the merits of BJTs and MOS transistors. So it is necessary to analyze the principle of HTL circuits. In this paper, the principles of three types of TL circuit: BJTs translinear (BTL) circuits, MOS transistors translinear (MTL) circuits and HTL circuits, are all given out in section II which are simplified by the modes of transistors in section III. This work is sponsored by the National Natural Science Foundation of China under grant No.50237030 and 90207001. It also gains support from the National Semiconductor Corp. (NSC).
A graphical representation and topological method to identify the multiple static translinear is presented in [6] in which the MOS transistors are in weak inversion. In section III the graphical representation is extended to MOS transistors in strong inversion and the topological method is extended to all the TL circuits especially to HTL circuits in section IV. II. TANSLINEAR LooP PRINCIPLE As well known, there are two topologies of TL circuits, updown and stacked topology [7]. They obey the same principle according to KVL. For simplicity the body effect of MOS transistors is not considered because it can be canceled by connecting the source to substrate.
A. BTL Circuit Principle The BTL circuit principle has been derived by Gilbert [1]. In a BTL loop with equal numbers of transistors arranged clockwise and counterclockwise. This is an essential requirement. From KVL, the BTL loop follows
ZVbe cw
(1)
ccw
Where, cw and ccw refer to the connected directions of the devices, clockwise and counterclockwise respectively. Substitute the expression of Vb, to (1),
ZVT ln(Ic/I) JVT ln(Ic /I). cw
(2)
ccw
Where IC and IS are collector current and saturation current, respectively. VT is the thermal voltage approximately 26mV at room temperature. For simplicity, all the Is are equal, so = tI I(3) HI~HIc cw
ccw
B. MTL Circuit Principle MOS transistor can work in weak inversion or in strong inversion and can work in saturated region or triode region. So there are many types of MTL circuit in theoretically. Usually, the MOS transistors are in saturated region and strong inversion, but as the requirement of low voltage the MOS transistors in triode region or weak inversion are used. The weak inversion transistors and strong inversion transistors have
1667
1-4244-0387-1/06/$20.00 (@2006 IEEE
ZVbe
not been in a TL loop until now. So we can focus on the weak inversion MTL loop or strong inversion MTL loop. The usage of transistors in triode region is few especially in TL loop for the limit of the disadvantage like nonlinearity, low gain and the drain current is not only related to the gate-source voltage but also the drain-source voltage. The transistors in triode region the current-voltage characteristic is more complex than in saturated region ones. Fortunately, triode region transistor (regardless in weak inversion or strong inversion) can be decomposed to two saturate devices as shown in section III. The expense is that the two devices will not in the same TL loop, but it simplify the analysis and is suited to some application [8]. As a result, there are only two types of MOS principle. The MTL circuit principle in weak inversion [6] is
IVgs =ZV cw
K ln(Id
(4)
I,) =K ln(Id /IIo)
(5)
Where K is equal to nVT, n approximates 1.5. Id and IO are the drain current and transistor current (similar to IS in BJT), respectively. Similar to BTL circuit, (5) is simplified to (6) if all lo s are equal.
(6)
= J7d
J'd
The MTL circuit principle in strong inversion derived in [4] is shown in (7) Where VTH is the threshold voltage and , is the coefficient of device. cw
Z('VTH +
VTH + 21d)
ccw
/2d lA)
(7)
For simplicity, all the MOS transistors are NMOS and the are all equal respectively.
VTH, ,
=d
Z cw
Z Vgs cw + n
g
(8)
ccw
Today, transistors working in strong inversion have an I-V relationship that is frequently no longer given by a pure quadratic relationship. More generally it is a power function:
Id = 0. 5,: (v s VTH )*(9)
Y (Id ) cw
=
Y (Id )
lln
(10)
ccw
C. HTL Circuit Principle Hybrid translinear loop contains BJTs and MOS transistors. Because of the different laws BJTs and MOS transistors obeyed, the HTL loop will be complex. Usually the numbers of BJTs or MOS transistors in clockwise and counterclockwise are equal for symmetry. Theoretically, bipolar transistors in saturated region will not be used in analog circuit in generally. And the MOS transistors in HTL loop work in weak inversion or strong inversion whose application is much more popular,
1668
Vbecw
=
E
n
Vgs,ccw +
E
m
Vbe,ccw
Y (vg"cw Vgs,ccw ) Y (Vbe,ccw Vbe,cw )
(11)
(12)
=
n
m
For the situation the MOS transistors in weak inversion,
KY[n In
Io,
I
In
Io,cw
Id
KZ[(lnI d),, -(lnId)]
s c ws"I,w
=Vi [lnn ijn
m
(13)
(ln)]. (14)
V Z(ln)
n
m
For the situation the MOS transistors in strong inversion, 2
P
1
[(j ),. (Cd )". ]
=
V, Y m
In
II, c
""
-
(15)
I Inc
is
C',
A2 f )w()c;V (1 C)C 1 C)0
( 16)
Now, the principles of three types are all given out. The BTL and MTL principle have been presented before and the HTL principle is important and useful as the development of BiCMOS technology. The HTL principle has been applied in
[9].
III. MODELS FOR TRANSISTORS The graphical equivalents for BJTs and MOS transistors in weak inversion have been depicted in [6]. MOS transistors can work in saturation or triode region regardless in weak inversion or strong inversion. The MOS transistor in triode region can be decomposed into two saturated devices connected anti-parallel regardless in weak inversion which has been given out in [8] or strong inversion which will be presented as follow. The drain current of the MOS transistor can be expressed as (17) and (18), corresponding to the device in saturated and triode region in strong inversion respectively.
Id =0 .5(V VTH) JIO= .502(Vgs VTH )L H V2]
The principle is modified to (10) easily through replacing the square root 1/2 with 1 n in this condition. lln
E
m
Where n is the number of MOS transistor in clockwise or counterclockwise, and m is the number referred to BJTs. Changing (1 1) to (12) will be benefit.
ccw
ccw
cw
resulting in that the principle is different in form. Both situations follow
(17) (18)
Through a simple change of (18), there is an iiinteresting result.
IdO= 0.56L (vg VTH ) (vgd VTH)2
(19)
That means the drain current of a triode region MOS transistor is equal to the drain current difference of two MOS transistors operated in saturated region: (20) Id = Idl Id2' So the decomposition method in Fig. 1 is approved to be reasonable.
APCCAS 2006
This result reduces the complexity of principle of TL loop and also the graphical equivalent of MOS transistor. A. Graphical Equivalentfor BJTs The graphical equivalent of NPN BJT contains an edge shown in Fig. 2. PNP BJT has similar equivalent besides the inverted direction of the edge. B. Graphical Equivalentfor MOS transistors The MOS transistor in weak inversion can be represented by a pair of edges in saturated region shown in Fig. 3(a) and by a set of four edges in triode region shown in Fig. 3(b). The graphical equivalent of MOS transistor in strong inversion is similar to the MOS transistor in weak inversion. The saturated and triode region transistors are represented in Fig. 4(a) and Fig. 4(b). IV. IDENTIFYING THE TRANSLINEAR Loop In the base of the graphical equivalent of bipolar and MOS transistors, the translinear loop can be depicted by different edges and vertexes. This topology method uniforms three types of TL loop in form. In actually, they are uniformed according S
D
D
.
G
G S
G 1
S
(a)
X S (c)
(b)
Figure 1. (a) Triode region NMOS transistor (b) Two saturated region NMOS transistors connected anti-parallel (c) Another form of (b) C B
E
DBE E
D
G G
D G
G
B
S
EGS
EBS
G-
I.
D
G
S
EBS
S B (b) Triode region (a) Saturated region Figure 3. Graphical equivalent for NMOS transsistor in weak inversion S B
FGS
FGD G
B
FBS
(a) Saturated region
D
FGS
G
S B
FBD FBS
S
(b) Triode region
Figure 4. Graphical equivalent for NMOS transistor in strong inversion
to the characteristic of BJT differential pair and MOS transistor differential pair in [9]. BJT differential pair and MOS differential pair can replace each other qualitatively. Because a TL loop can be decomposed to two differential pairs, so the three types of TL loop are uniformed in circuit analysis and also in topology. Using the topological method, it is convenient to identify the devices involved in each translinear loop [6]. Although [6] is not complete, the definitions and propertied in [6] all can be extended to the MTL loop in saturated region of strong inversion and HTL loop. Considering to the MTL loop whose transistors are in triode region, they are used in low voltage low power applications. Some applications are presented in [8]. As a simple example of HTL loop, a class AB output stage containing two HTL loops is drawn in Fig. 5 [9]. The three HTL loops M1-Q11-M14-Q12, M1-Q11-M13-Q9 and M14Q12-M13-Q9 realize the quiescent current control and get better effect than onefold BTL or MTL loops. In analysis, the HTL loops cell can be abstracted from the output stage using the topology method shown in Fig. 6. There are two fundamental translinear loops according to the property [6]: The number of fundamental translinear loop L is given by L = NTE - NV 1 where NTE is the number of translinear elements and NV is the number of vertices of the circuit. Here L = 6 - 5 + 1 = 2. So one TL loop is trivial and the other two TL loops are fundamental which are coupled directly. The definitions of fundamental and trivial TL loop are shown in [6]. So in actually it just needs two TL loops in analysis which simplify the analysis. Fig. 7 shows the two TL loops. And finally the quiescent current and residual current can be driven out through the two HTL loops [9]. V.
EGD EBD _EGD, EBO EGS
S
(S B
Figure 2. Graphical equivalent NPN bi[polar transistor
D
D
CONCLUSION
In this paper the principle of HTL circuit was presented in detail. It made the principles of TL circuits be more complete. And a new method was proposed to decompose the MOS transistor operated in triode region into two transistors operated in saturated region and simplified this principles. On the other hand, the topological method to identify the TL loops was extended to all of the three types of TL loops especially to HTL one, which is based on the graphical equivalents of transistors. Finally, as an example, an HTL circuit applied to quiescent current control of class AB output stage was analyzed.
APCCAS 2006
1669
R. V. Bemal, A. S. Reyes and W. A. Serdijn, "Identifying translinear loops in the circuit topology," ISCAS 2000 IEEE International Symposium on Circuits and Systems, May 28-31, 2000. [7] R. J. Wiegerink, Analysis and synthesis of MOS translinear circuits. Norwell, MA: Kluwer, 1993. E. Seevinck, E. Vittoz, M. du Plessis, T.-H. Joubert, and WBeetge, . "CMOS translinear circuits for minimum supply voltage," IEEE Transactions on Circuits and Systems 11, 47(12):1560 1564, December 2000. [9] Cheng Yuhua, Wu Xiaobo, Yan Xiaolang, "Analysis of hybrid translinear circuit and its application," International MultiConference of Engineers and Computer Scientists 2006, Hong Kong, June 20-22, 2006.
[6]
vcc
0
_
IV13
.
07
r5
06
04
S
,;
'
A
htL14 A
........[8] Vout
08 QS
VEE
Figure 5. Class AB output stage
DBE9
DBEI
ESG13
DBE12I
ESG1 ESG14 Figure 6. Translinear loops in the circuit of Fig. 5
DBE9
DBE9 DBE1I
ESG13
ESG13
ESGl
DBE12
ESG14
Figure 7. Two fundamental translinear loops in Fig. 6
ACKNOWLEDGMENT
The author would like to thank Mr. David Pace and Mr. Kalon Chu, the senior engineers of NSC, for their useful discussion and instruction. REFERENCES [1] [2]
[3]
[4] [5]
B. Gilbert, "Translinear circuits: a proposed classification," Electron. Lett., vol. 11, no. 1, pp. 14-16, 1975. T. S. Gotarredona, B. L. Barranco, and A. G. Andreou, "A general subthreshold MOS translinear theorem," in Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI, vol. 2. Piscataway, NJ: IEEE, 1999, pp. 302-305. T. S. Gotarredona, B. L. Barranco, and A. G. Andreou, "A general translinear principle for subthreshold MOS transistors," IEEE Transcactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 46, no. 5, May 1999. E. Seevinck and R. J. Wiegerink, "Generalized translinear circuit principle," IEEE J. Solid-State Circuits, vol. 26, no. 8, August 1991. J. Mulder, W. A. Serdijn, A. C. Vander Woerd, "A generalized class of dynamic translinear circuits," IEEE Transcactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 48, no. 5, May 2001.
1670
APCCAS 2006
