ultra-low voltage tunable transconductor based on ... - Semantic Scholar
Journal of Circuits, Systems, and Computers Vol. 22, No. 8 (2013) 1350073 (13 pages) # .c World Scienti¯c Publishing Company DOI: 10.1142/S0218126613500734
ULTRA-LOW VOLTAGE TUNABLE TRANSCONDUCTOR BASED ON BULK-DRIVEN ¤ QUASI-FLOATING-GATE TECHNIQUE
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FABIAN KHATEB†,¶, NABHAN KHATIB†,||, PIPAT PROMMEE‡,**, WINAI JAIKLA§,†† and LUKAS FUJCIK†,‡‡ †
Department of Microelectronics, Brno University of Technology, Technick a 10, Brno, Czech Republic ‡Department
of Telecommunications Engineering, Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520, Thailand §
Department of Engineering Education, Faculty of Industrial Education, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520, Thailand ¶ [email protected] || [email protected] **[email protected] ††[email protected] ‡‡ [email protected] Received 15 March 2013 Accepted 22 July 2013 Published 28 August 2013 This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-°oatinggate technique (BD-QFG). This technique leads to signi¯cant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of 300 mV and low power consumption of 18 W. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm -C multifunction ¯lter is presented as one of the possible applications. The simulation results using 0.18 m CMOS N-Well process from TSMC show the attractive features of the proposed circuit. Keywords: Floating-gate MOST; quasi-°oating-gate MOST; bulk-driven MOST; transconductor.
*This
paper was recommended by Regional Editor Piero Malcovati.
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1. Introduction Among variety of analog design techniques that used to achieve acceptable circuit performances under low-voltage (LV) condition belong: bulk-driven (BD), °oatinggate (FG) and quasi-°oating-gate (QFG) techniques.1–43,49–52 As a matter of fact these techniques have proven widespread applicability in LV area. Various LV active elements have been designed via these techniques, such as voltage follower (VF),9,10 operational ampli¯er (Op-Amp),11,20 operational transconductance ampli¯er (OTA),12–15,21–23,28,43 second generation current conveyor (CCII),16,38–40,42,43 current di®erencing transconductance ampli¯er (CDTA),17 di®erential-input bu®ered and external transconductance ampli¯er (DBeTA),32 current mirror (CM),30,33 di®erential voltage current conveyor (DVCC),41 winner-take-all (WTA) circuit,49 and others. However, the aforementioned techniques su®er from some limitations. The transconductance value of the QFG (gm-QFG ), FG (gmFG ) and of the BD (gmb ) transistors are less than the transconductance value of the conventional gate driven (GD) transistor (gm ), respectively, i.e., gm > gm-QFG > gm-FG > gmb . The FG and QFG MOS transistors can process only AC signals; hence the DC applications for these two techniques are overlooked. Therefore, two new techniques appear as promising way to suppress the limitations of the upper mentioned techniques.44,45 The two new techniques are named as bulk-driven °oating-gate (BD-FG) and bulk-driven quasi-°oating-gate (BD-QFG) and they ensure high transconductance value close to the transconductance value of the conventional gate driven transistor, high bandwidth and they enable the capability of processing both AC and DC signals, all under ultra-LV supply voltage.44,45 This paper presents the BD-QFG principle and a tunable transconductor based on it; the transconductance value is tunable by external resistor in a wide range. Also, a second-order Gm -C multifunction ¯lter is presented as possible application.
2. BD-QFG MOST Principle To illustrate the principle of the BD-QFG MOST using N-well technology Fig. 1 shows its symbol and the realization in MOS technology. As shown in Fig. 1(a) the bias-gate \Gbias " must be connected to a suitable bias voltage through a large resistor value \Rb " which is practically realized by MOST operating in the cuto® region \Mb " as shown in Fig. 1(b). The input terminal \Gin " is capacitively coupled via Cin to the quasi-°oating gate terminal from one side and directly coupled to the bulk terminal from other side. As a result the total transistor transconductance (gm;BD-QFG Þ is increased.44,45 The BD-QFG MOST transconductance is given by the sum of BD and QFG transconductances i.e., gm;BD-QFG ¼ gmb þ gm;QFG :
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
Gin
Gin
S
Cin
B
MBD-QFG D
Rb
S B
QFG
MBD-QFG
Mb
D
Gbias
Gbias (a)
(b)
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Fig. 1. BD-QFG MOST: (a) symbol and (b) realization in MOS technology.
Consequently, the transient frequency is also increased: fT ;BD-QFG ¼
gmb þ gm;QFG ; 2ðCbs þ Cbsub þ Cgs Þ
ð2Þ
where gmb and gm;QFG are the bulk transconductance and the e®ective transconductance of the BD-QFG MOST, respectively. Also, Cbs , Cbsub and Cgs are the bulksource, bulk-substrate and the gate-source capacitances of the MOST, respectively.
3. Ultra-LV BD-QFG Transconductor The transconductor is one of the most important building blocks in analog and mixed-mode circuits, including continuous-time Gm -C ¯lter, voltage controlled oscillator, and continuous-time sigma-delta modulator. The symbol of the transconductor is presented in Fig. 2. It has two input terminals with very high impedance (inverting \" and noninverting \þ") and one output terminal \out" with high impedance. The terminal \set" is connected to output passive resistor Rset , and it is used to set the value of the e®ective transconductance Gm , where Gm 1=Rset . For applications requiring electronic control of
in+ in-
Vin +
+ Gm _
Iout out
set
Vin_ IRset=Iout
Rset
VRset
Fig. 2. Electrical symbol of the tunable transconductor.
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VDD inIbias
M6 C4
M11
M5
in+ C3
C2
VSS
C1
M11c
M12c
VSS
M4
M2 Mb4
M12 VSS
Mb3 M3
VDD
M1 Mb2
Mb1
M9c
out set M10c Rset
M13
M8
M7
M9
M10
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VSS Fig. 3. CMOS structure of the transconductor based on new BD-QFG technique.
the transconductance, the passive resistor Rset can be replaced by commonly used voltage-controlled resistance based on simple CMOS circuitry. The internal CMOS structure of the BD-QFG transconductor is shown in Fig. 3. The circuit consists of two di®erential BD-QFG transistors i.e., M1, M2 and M3, M4. The gates of these transistors are connected to the negative supply voltage through high value resistors created by transistors Mb1 , Mb2 , Mb3 , Mb4 , respectively, which are operating in cuto® region. The input terminals of M1, M2, M3 and M4 are capacitively coupled (via C1, C2, C3 and C4 Þ, respectively, to their quasi-°oating gate terminals from one side and directly coupled to their bulk terminals from other side. Transistors M7, M8, M9, M10 and M13 are used to create the current biasing for the circuit. Transistors M5 and M6 act as tail current sources for the ¯rst and second di®erential input stages, respectively. Transistors M9c , M10c , M11 , M11c , M12 and M12c create the output stage of the transconductor and they ensure equal currents passing through terminals \set" and \out" i.e., Iout ¼ IRset . Finally, Ibias is the current bias for the circuit and the external resistor Rset is used to set the value of the transconductance. It is worth mentioning here that due to the internal negative feedback, created by the connection between the drains of M9c , M11c and the input of M1, the linearity of the transconductor is signi¯cantly improved in comparison with the conventional method of modifying the bias current of the transistors operating in the Gm stage.17 Furthermore, this internal negative feedback provides the voltage transfers between the input terminals and the \set" one. The self-transconductance (i.e., without negative feedback and with grounding the input terminal of M1 in similar manner as M3 Þ of the transconductor is gm and it is given by: gm ¼
Iout : Vin
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
By providing the negative feedback and connecting external Rset to \set" terminal as shown in Fig. 3 a simple analysis yields: Vin VRset ¼ Vin ¼
Iout ; gm
ð4Þ
Iout I 1 þ VRset ¼ out þ Rset Iout ¼ Iout þ Rset : gm gm gm
ð5Þ
From Eq. (5) the e®ective transconductance Gm can be obtained as:
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Gm ¼
Iout 1 1 ¼ 1 Rset Vin þ Rset gm
if Rset
1 : gm
ð6Þ
It is worth noting here that similar principle of controlling the Gm value via external resistor is presented in Refs. 17 and 43. However, the proposed circuit structure in this paper is simpler with minimum count of transistors in contrast to the structure presented in Ref. 43. Note that the °ipped voltage follower is used to bias the two di®erential BD-QFG transistors similar to Refs. 16 and 49; hence, the minimum voltage supply for this structure is given by: VDDmin ¼ VGS;M5;M6 þ VDS;M7;M8 :
ð7Þ
Equation (7) proves that the proposed structure has the capability to operate under extremely low voltage supply. The input terminals inþ and in possess high input impedance. The output impedance is also signi¯cantly high due to using the cascode technique at the output stage and it is given by: Rout
1 ; go;M10 go;M10c go;M12 go;M12c þ ðgm;M10c þ gmb;M10c Þ ðgm;M12c þ gmb;M12c Þ
ð8Þ
where go is the transistor output conductance. 4. Second-Order Gm-C Multifunction Filter based on BD-QFG Transconductor Figure 4 shows a second-order Gm -C multifunction ¯lter based on two BD-QFG transconductors and two capacitors to realize the low-pass (LP), high-pass (HP) and band-pass (BP) responses. Analysis of the proposed ¯lter circuit yields the following equation: Vout ¼
s 2 VinHP þ sðGm2 =C2 ÞVinBP þ ðGm1 Gm2 =C1 C2 ÞVinLP : s 2 þ sðGm2 =C2 Þ þ ðGm1 Gm2 =C1 C2 Þ
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Vin-LP
_
_
Gm1 +
G Gm2 m2 +
Vout
C2
C1
Rset2
Rset1
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Vin-BP
Vin-HP
Fig. 4. Second-order Gm -C multifunction ¯lter based on two BD-QFG transconductors and two capacitors.
It is clearly obtained from Eq. (6) that: The low-pass response can be obtained when Vin ¼ Vin-LP and Vin-HP ¼ Vin-BP ¼ 0 (grounded). . The band-pass response can be obtained when Vin ¼ Vin-BP and Vin-HP ¼ Vin-LP ¼ 0. . The high-pass response can be obtained when Vin ¼ Vin-HP and Vin-LP ¼ Vin-BP ¼ 0. .
The following relations are valid for the pole frequency and the quality factor: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Gm1 Gm2 =C1 C2 ; pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Q ¼ ðGm1 C2 =Gm2 C1 Þ :
!0 ¼
ð10Þ ð11Þ
From Eqs. (10) and (11) it is obvious that if Gm1 ¼ Gm2 ¼ Gm then the parameter !o can be controlled by Gm without disturbing Q. Also, the sensitivities of the parameters !o and Q are calculated as shown in Table 1 where it is evident that the active and passive sensitivities are calculated as 0.5 in magnitude.
Table 1. Sensitivities of circuit components. X
S x!o
S xQ
Gm1 Gm2 C1 C2
0.5 0.5 0.5 0.5
0.5 0.5 0.5 0.5
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The proposed BD-QFG transconductor was designed and simulated using 0.18 m CMOS process from TSMC.46 The supply voltage is VDD ¼ VSS ¼ 300 mV, the bias current Ibias ¼ 5 A and the total power consumption is 18 W. The transistors aspect ratios W =L of the transistors are M1, M2, M3, M4 ¼ 10 m/0.3 m, M5, M6 ¼ 50 m/0.3 m, M7, M8, M13 ¼ 4 m/0.3 m, M9, M10 , Mb1 , Mb2 , Mb3 , Mb4 ¼ 8 m/0.3 m, M9c , M10c ¼ 45 m/2 m, M11 , M12 ¼ 100 m/0.3 m, M11c , M12c ¼ 100 m/2 m, and C1 , C2 , C3 , C4 ¼ 0:1 pF. To demonstrate the wide linear range and the tunability of the BD-QFG transconductance value of the transconductor, the DC output current versus input voltage with stepping Rset from 80 to 320 k with 40 k step is shown in Fig. 5. It is evident the wide range of operation. The simulated inputs and output impedances versus frequency are shown in Fig. 6. The Rout as expected is signi¯cantly high and its value is about 10 M. The relation between the simulated and the calculated transconductance based on Eq. (6) is illustrated in Fig. 7. It is notable that with increasing the value of Rset (i.e., Rset 1=gm Þ the simulated and calculated values of Gm become more identical. Figure 8 shows the frequency and phase responses of the second-order Gm -C ¯lter presented in Fig. 4. By setting C1 ¼ C2 ¼ 20 pF and Rset1 ¼ Rset2 ¼ 265 k, which yield f0 ¼ 30 kHz and Q ¼ 1. It is evident that the simulation results are in agreement with theory. The total power consumption of the ¯lter is 37 W. Figure 9 shows the total harmonic distortion (THD) of the low-pass ¯lter by applying a sinusoidal signal of various amplitudes and frequencies of 1 kHz and 10 kHz. The THD is below 2.5% for input voltage up to 160 mV (peak-to-peak).
2 Rset
DC output current [µA]
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5. Simulation Results
1
0 Rset -1
-2 -200
-100
0 Vin [mV]
100
200
Fig. 5. DC output current versus input voltage with stepping Rset from 80 to 320 k with 40 k step.
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Impedance
1T
Zin+
Zin-
100M
10k 1
100
10k
1M
100M
Frequency [Hz]
Fig. 6. Input and output impedances versus frequency.
A performance comparison of BD-QFG transconductor with other proposals in the literature is shown in Table 2. The comparison is done with transconductor based on BD technique with transconductance enhancement presented in Ref. 12, with transconductor based on QFG technique presented in Ref. 43 and with two transconductors based on the conventional GD technique in Refs. 47 and 48. It is obvious that the transconductor based on BD-QFG technique has the best trade-o® between ultra-low voltage low-power and bandwidth. Finally, based on the above mentioned discussion yields that using the BD-QFG MOST o®ers mainly the following advantages: .
High transconductance value close to the gate-driven one, resulting in increase of the bandwidth and reducing the input referred noise of the proposed circuit. 30 Calculated
25
Transconductance [µs]
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Zout
20
Simulated
15 10 5 0 0
100
200
300
400
500
Rset
Fig. 7. Simulated and calculated transconductance value versus Rset .
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG 200 BP
Phase [º]
100
HP 0
-100 LP -200 20
Magnitude [dB]
BP -20
LP
-40
-60 1k
3k
10k
30k Frequency [Hz]
100k
300k
1M
Fig. 8. The frequency and phase responses of the second-order Gm -C multifunction ¯lter.
2.5
THD [%]
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HP 0
2 10 kHz 1.5
1 1 kHz 0.5
0 10
20
40 80 Input voltage (peak-to-peak) [mV]
120
160
Fig. 9. Dependence of the output harmonic distortion of the second-order LP ¯lter on the input voltage with 1 kHz and 10 kHz.
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Technology (m) Voltage supply (V) Power consumption (W) Input impedance (G) Output impedance (MÞ Gm (A/V) Bandwidth (MHz) Obtained results
This work
BD12
QFG43
GD47
GD48
0.18 0.3 18 118 10 1–40 14 Simulated
0.35 1 200 — — 100 10 Simulated
0.5 3.3 230 — — 250 12 Measured
0.5 2.5 5700 — — 34–105 — Simulated
0.35 3.3 10,500 — — 70–160 — Measured
.
Ultra-low-voltage low-power operation capability,
.
Simple circuitry and Extended input voltage range nearly rail-to-rail.
.
6. Conclusion The aim of this paper is to present a new technique for analog circuit design implementation that able to compete with pleasurable behaviors of the conventional gate driven transistor with extra bene¯t that the whole circuit is working under low voltage low power area. This paper presents a new ultra-low voltage transconductor based on BD-QFG technique. The low supply voltage, low power consumption and the wide dynamic range are the main attractive features of the proposed circuit. As a possible application a second-order multifunction Gm -C ¯lter is presented to prove the validation of the described technique. Acknowledgments The described research was performed in laboratories supported by the SIX project; the registration number CZ.1.05/2.1.00/03.0072, the operational program Research and Development for Innovation and has been supported by Czech Science Foundation project No.: GA102/11/1379, also by Ministry of Industry and Commerce under the contract FR-TI3/485.
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
44. F. Khateb and N. Khatib, Connection of FG MOS and QFG MOS transistors for analogous integrated circuits, National utility model application registered by the Industrial Property O±ce in the Czech Republic under registration number 23091 (2011), http:// isdv.upv.cz/portal/pls/portal/portlets.pts.det?xprim¼1693188&lan¼en. 45. F. Khateb and N. Khatib, Connection of FG MOS and QFG MOS transistors for analogous integrated circuits, National patent application registered by the Industrial Property O±ce in the Czech Republic under registration number 303698 (2013), http:// spisy.upv.cz/Patents/FullDocuments/303/303698.pdf. 46. http://www.mosis.com/pages/Technical/Testdata/tsmc-018-prm 47. S. Koziel and S. Szczepanski, Design of highly linear tunable CMOS OTA for continuoustime ¯lters, IEEE Trans. Circuits Syst. I 49 (2002) 110–122. 48. A. Lewinski and J. Silva-Martinez, OTA linearity enhancement technique for high frequency applications with IM3 below 65 dB, Custom Integrated Circuits Conf. (2003), pp. 9–12. 49. F. Khateb and S. Vlassis, Low-voltage bulk-driven recti¯er for biomedical applications, Microelectron. J. 44 (2013) 642–648. 50. T. Lehmann and M. Cassia, 1 V OTA using current driven bulk circuits, J. Circ., Syst. Comput. 11 (2002) 81–91. 51. F. Khateb, S. Bay Abo Dabbous and S. Vlassis, A survey of non-conventional techniques for low-voltage low-power analog circuit design, Radioengineering 22 (2013) 415–427. 52. M. Kumngern, F. Khateb, K. Dejhan, P. Phasukkit and S. Tungjitkusolmun, Voltagemode multifunction biquadratic ¯lters using new ultra-low-power di®erential di®erence current conveyors, Radioengineering 22 (2013) 448–457.
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ULTRA-LOW VOLTAGE TUNABLE TRANSCONDUCTOR BASED ON BULK-DRIVEN ¤ QUASI-FLOATING-GATE TECHNIQUE
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FABIAN KHATEB†,¶, NABHAN KHATIB†,||, PIPAT PROMMEE‡,**, WINAI JAIKLA§,†† and LUKAS FUJCIK†,‡‡ †
Department of Microelectronics, Brno University of Technology, Technick a 10, Brno, Czech Republic ‡Department
of Telecommunications Engineering, Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520, Thailand §
Department of Engineering Education, Faculty of Industrial Education, King Mongkut's Institute of Technology Ladkrabang, Bangkok 10520, Thailand ¶ [email protected] || [email protected] **[email protected] ††[email protected] ‡‡ [email protected] Received 15 March 2013 Accepted 22 July 2013 Published 28 August 2013 This paper presents ultra-low voltage transconductor using a new bulk-driven quasi-°oatinggate technique (BD-QFG). This technique leads to signi¯cant increase in the transconductance and the bandwidth values of the MOS transistor (MOST) under ultra-low voltage condition. The proposed CMOS structure of the transconductor is capable to work with ultra-low supply voltage of 300 mV and low power consumption of 18 W. The transconductance value of the transconductor is tunable by external resistor with wide linear range. To prove the validation of the new described technique a second-order Gm -C multifunction ¯lter is presented as one of the possible applications. The simulation results using 0.18 m CMOS N-Well process from TSMC show the attractive features of the proposed circuit. Keywords: Floating-gate MOST; quasi-°oating-gate MOST; bulk-driven MOST; transconductor.
*This
paper was recommended by Regional Editor Piero Malcovati.
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1. Introduction Among variety of analog design techniques that used to achieve acceptable circuit performances under low-voltage (LV) condition belong: bulk-driven (BD), °oatinggate (FG) and quasi-°oating-gate (QFG) techniques.1–43,49–52 As a matter of fact these techniques have proven widespread applicability in LV area. Various LV active elements have been designed via these techniques, such as voltage follower (VF),9,10 operational ampli¯er (Op-Amp),11,20 operational transconductance ampli¯er (OTA),12–15,21–23,28,43 second generation current conveyor (CCII),16,38–40,42,43 current di®erencing transconductance ampli¯er (CDTA),17 di®erential-input bu®ered and external transconductance ampli¯er (DBeTA),32 current mirror (CM),30,33 di®erential voltage current conveyor (DVCC),41 winner-take-all (WTA) circuit,49 and others. However, the aforementioned techniques su®er from some limitations. The transconductance value of the QFG (gm-QFG ), FG (gmFG ) and of the BD (gmb ) transistors are less than the transconductance value of the conventional gate driven (GD) transistor (gm ), respectively, i.e., gm > gm-QFG > gm-FG > gmb . The FG and QFG MOS transistors can process only AC signals; hence the DC applications for these two techniques are overlooked. Therefore, two new techniques appear as promising way to suppress the limitations of the upper mentioned techniques.44,45 The two new techniques are named as bulk-driven °oating-gate (BD-FG) and bulk-driven quasi-°oating-gate (BD-QFG) and they ensure high transconductance value close to the transconductance value of the conventional gate driven transistor, high bandwidth and they enable the capability of processing both AC and DC signals, all under ultra-LV supply voltage.44,45 This paper presents the BD-QFG principle and a tunable transconductor based on it; the transconductance value is tunable by external resistor in a wide range. Also, a second-order Gm -C multifunction ¯lter is presented as possible application.
2. BD-QFG MOST Principle To illustrate the principle of the BD-QFG MOST using N-well technology Fig. 1 shows its symbol and the realization in MOS technology. As shown in Fig. 1(a) the bias-gate \Gbias " must be connected to a suitable bias voltage through a large resistor value \Rb " which is practically realized by MOST operating in the cuto® region \Mb " as shown in Fig. 1(b). The input terminal \Gin " is capacitively coupled via Cin to the quasi-°oating gate terminal from one side and directly coupled to the bulk terminal from other side. As a result the total transistor transconductance (gm;BD-QFG Þ is increased.44,45 The BD-QFG MOST transconductance is given by the sum of BD and QFG transconductances i.e., gm;BD-QFG ¼ gmb þ gm;QFG :
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
Gin
Gin
S
Cin
B
MBD-QFG D
Rb
S B
QFG
MBD-QFG
Mb
D
Gbias
Gbias (a)
(b)
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Fig. 1. BD-QFG MOST: (a) symbol and (b) realization in MOS technology.
Consequently, the transient frequency is also increased: fT ;BD-QFG ¼
gmb þ gm;QFG ; 2ðCbs þ Cbsub þ Cgs Þ
ð2Þ
where gmb and gm;QFG are the bulk transconductance and the e®ective transconductance of the BD-QFG MOST, respectively. Also, Cbs , Cbsub and Cgs are the bulksource, bulk-substrate and the gate-source capacitances of the MOST, respectively.
3. Ultra-LV BD-QFG Transconductor The transconductor is one of the most important building blocks in analog and mixed-mode circuits, including continuous-time Gm -C ¯lter, voltage controlled oscillator, and continuous-time sigma-delta modulator. The symbol of the transconductor is presented in Fig. 2. It has two input terminals with very high impedance (inverting \" and noninverting \þ") and one output terminal \out" with high impedance. The terminal \set" is connected to output passive resistor Rset , and it is used to set the value of the e®ective transconductance Gm , where Gm 1=Rset . For applications requiring electronic control of
in+ in-
Vin +
+ Gm _
Iout out
set
Vin_ IRset=Iout
Rset
VRset
Fig. 2. Electrical symbol of the tunable transconductor.
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VDD inIbias
M6 C4
M11
M5
in+ C3
C2
VSS
C1
M11c
M12c
VSS
M4
M2 Mb4
M12 VSS
Mb3 M3
VDD
M1 Mb2
Mb1
M9c
out set M10c Rset
M13
M8
M7
M9
M10
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VSS Fig. 3. CMOS structure of the transconductor based on new BD-QFG technique.
the transconductance, the passive resistor Rset can be replaced by commonly used voltage-controlled resistance based on simple CMOS circuitry. The internal CMOS structure of the BD-QFG transconductor is shown in Fig. 3. The circuit consists of two di®erential BD-QFG transistors i.e., M1, M2 and M3, M4. The gates of these transistors are connected to the negative supply voltage through high value resistors created by transistors Mb1 , Mb2 , Mb3 , Mb4 , respectively, which are operating in cuto® region. The input terminals of M1, M2, M3 and M4 are capacitively coupled (via C1, C2, C3 and C4 Þ, respectively, to their quasi-°oating gate terminals from one side and directly coupled to their bulk terminals from other side. Transistors M7, M8, M9, M10 and M13 are used to create the current biasing for the circuit. Transistors M5 and M6 act as tail current sources for the ¯rst and second di®erential input stages, respectively. Transistors M9c , M10c , M11 , M11c , M12 and M12c create the output stage of the transconductor and they ensure equal currents passing through terminals \set" and \out" i.e., Iout ¼ IRset . Finally, Ibias is the current bias for the circuit and the external resistor Rset is used to set the value of the transconductance. It is worth mentioning here that due to the internal negative feedback, created by the connection between the drains of M9c , M11c and the input of M1, the linearity of the transconductor is signi¯cantly improved in comparison with the conventional method of modifying the bias current of the transistors operating in the Gm stage.17 Furthermore, this internal negative feedback provides the voltage transfers between the input terminals and the \set" one. The self-transconductance (i.e., without negative feedback and with grounding the input terminal of M1 in similar manner as M3 Þ of the transconductor is gm and it is given by: gm ¼
Iout : Vin
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
By providing the negative feedback and connecting external Rset to \set" terminal as shown in Fig. 3 a simple analysis yields: Vin VRset ¼ Vin ¼
Iout ; gm
ð4Þ
Iout I 1 þ VRset ¼ out þ Rset Iout ¼ Iout þ Rset : gm gm gm
ð5Þ
From Eq. (5) the e®ective transconductance Gm can be obtained as:
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Gm ¼
Iout 1 1 ¼ 1 Rset Vin þ Rset gm
if Rset
1 : gm
ð6Þ
It is worth noting here that similar principle of controlling the Gm value via external resistor is presented in Refs. 17 and 43. However, the proposed circuit structure in this paper is simpler with minimum count of transistors in contrast to the structure presented in Ref. 43. Note that the °ipped voltage follower is used to bias the two di®erential BD-QFG transistors similar to Refs. 16 and 49; hence, the minimum voltage supply for this structure is given by: VDDmin ¼ VGS;M5;M6 þ VDS;M7;M8 :
ð7Þ
Equation (7) proves that the proposed structure has the capability to operate under extremely low voltage supply. The input terminals inþ and in possess high input impedance. The output impedance is also signi¯cantly high due to using the cascode technique at the output stage and it is given by: Rout
1 ; go;M10 go;M10c go;M12 go;M12c þ ðgm;M10c þ gmb;M10c Þ ðgm;M12c þ gmb;M12c Þ
ð8Þ
where go is the transistor output conductance. 4. Second-Order Gm-C Multifunction Filter based on BD-QFG Transconductor Figure 4 shows a second-order Gm -C multifunction ¯lter based on two BD-QFG transconductors and two capacitors to realize the low-pass (LP), high-pass (HP) and band-pass (BP) responses. Analysis of the proposed ¯lter circuit yields the following equation: Vout ¼
s 2 VinHP þ sðGm2 =C2 ÞVinBP þ ðGm1 Gm2 =C1 C2 ÞVinLP : s 2 þ sðGm2 =C2 Þ þ ðGm1 Gm2 =C1 C2 Þ
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Vin-LP
_
_
Gm1 +
G Gm2 m2 +
Vout
C2
C1
Rset2
Rset1
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Vin-BP
Vin-HP
Fig. 4. Second-order Gm -C multifunction ¯lter based on two BD-QFG transconductors and two capacitors.
It is clearly obtained from Eq. (6) that: The low-pass response can be obtained when Vin ¼ Vin-LP and Vin-HP ¼ Vin-BP ¼ 0 (grounded). . The band-pass response can be obtained when Vin ¼ Vin-BP and Vin-HP ¼ Vin-LP ¼ 0. . The high-pass response can be obtained when Vin ¼ Vin-HP and Vin-LP ¼ Vin-BP ¼ 0. .
The following relations are valid for the pole frequency and the quality factor: pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Gm1 Gm2 =C1 C2 ; pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Q ¼ ðGm1 C2 =Gm2 C1 Þ :
!0 ¼
ð10Þ ð11Þ
From Eqs. (10) and (11) it is obvious that if Gm1 ¼ Gm2 ¼ Gm then the parameter !o can be controlled by Gm without disturbing Q. Also, the sensitivities of the parameters !o and Q are calculated as shown in Table 1 where it is evident that the active and passive sensitivities are calculated as 0.5 in magnitude.
Table 1. Sensitivities of circuit components. X
S x!o
S xQ
Gm1 Gm2 C1 C2
0.5 0.5 0.5 0.5
0.5 0.5 0.5 0.5
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
The proposed BD-QFG transconductor was designed and simulated using 0.18 m CMOS process from TSMC.46 The supply voltage is VDD ¼ VSS ¼ 300 mV, the bias current Ibias ¼ 5 A and the total power consumption is 18 W. The transistors aspect ratios W =L of the transistors are M1, M2, M3, M4 ¼ 10 m/0.3 m, M5, M6 ¼ 50 m/0.3 m, M7, M8, M13 ¼ 4 m/0.3 m, M9, M10 , Mb1 , Mb2 , Mb3 , Mb4 ¼ 8 m/0.3 m, M9c , M10c ¼ 45 m/2 m, M11 , M12 ¼ 100 m/0.3 m, M11c , M12c ¼ 100 m/2 m, and C1 , C2 , C3 , C4 ¼ 0:1 pF. To demonstrate the wide linear range and the tunability of the BD-QFG transconductance value of the transconductor, the DC output current versus input voltage with stepping Rset from 80 to 320 k with 40 k step is shown in Fig. 5. It is evident the wide range of operation. The simulated inputs and output impedances versus frequency are shown in Fig. 6. The Rout as expected is signi¯cantly high and its value is about 10 M. The relation between the simulated and the calculated transconductance based on Eq. (6) is illustrated in Fig. 7. It is notable that with increasing the value of Rset (i.e., Rset 1=gm Þ the simulated and calculated values of Gm become more identical. Figure 8 shows the frequency and phase responses of the second-order Gm -C ¯lter presented in Fig. 4. By setting C1 ¼ C2 ¼ 20 pF and Rset1 ¼ Rset2 ¼ 265 k, which yield f0 ¼ 30 kHz and Q ¼ 1. It is evident that the simulation results are in agreement with theory. The total power consumption of the ¯lter is 37 W. Figure 9 shows the total harmonic distortion (THD) of the low-pass ¯lter by applying a sinusoidal signal of various amplitudes and frequencies of 1 kHz and 10 kHz. The THD is below 2.5% for input voltage up to 160 mV (peak-to-peak).
2 Rset
DC output current [µA]
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5. Simulation Results
1
0 Rset -1
-2 -200
-100
0 Vin [mV]
100
200
Fig. 5. DC output current versus input voltage with stepping Rset from 80 to 320 k with 40 k step.
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Impedance
1T
Zin+
Zin-
100M
10k 1
100
10k
1M
100M
Frequency [Hz]
Fig. 6. Input and output impedances versus frequency.
A performance comparison of BD-QFG transconductor with other proposals in the literature is shown in Table 2. The comparison is done with transconductor based on BD technique with transconductance enhancement presented in Ref. 12, with transconductor based on QFG technique presented in Ref. 43 and with two transconductors based on the conventional GD technique in Refs. 47 and 48. It is obvious that the transconductor based on BD-QFG technique has the best trade-o® between ultra-low voltage low-power and bandwidth. Finally, based on the above mentioned discussion yields that using the BD-QFG MOST o®ers mainly the following advantages: .
High transconductance value close to the gate-driven one, resulting in increase of the bandwidth and reducing the input referred noise of the proposed circuit. 30 Calculated
25
Transconductance [µs]
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Zout
20
Simulated
15 10 5 0 0
100
200
300
400
500
Rset
Fig. 7. Simulated and calculated transconductance value versus Rset .
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG 200 BP
Phase [º]
100
HP 0
-100 LP -200 20
Magnitude [dB]
BP -20
LP
-40
-60 1k
3k
10k
30k Frequency [Hz]
100k
300k
1M
Fig. 8. The frequency and phase responses of the second-order Gm -C multifunction ¯lter.
2.5
THD [%]
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HP 0
2 10 kHz 1.5
1 1 kHz 0.5
0 10
20
40 80 Input voltage (peak-to-peak) [mV]
120
160
Fig. 9. Dependence of the output harmonic distortion of the second-order LP ¯lter on the input voltage with 1 kHz and 10 kHz.
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F. Khateb et al. Table 2. Performance comparison of BD-QFG transconductor with other transconductors based on BD and QFG techniques.
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Technology (m) Voltage supply (V) Power consumption (W) Input impedance (G) Output impedance (MÞ Gm (A/V) Bandwidth (MHz) Obtained results
This work
BD12
QFG43
GD47
GD48
0.18 0.3 18 118 10 1–40 14 Simulated
0.35 1 200 — — 100 10 Simulated
0.5 3.3 230 — — 250 12 Measured
0.5 2.5 5700 — — 34–105 — Simulated
0.35 3.3 10,500 — — 70–160 — Measured
.
Ultra-low-voltage low-power operation capability,
.
Simple circuitry and Extended input voltage range nearly rail-to-rail.
.
6. Conclusion The aim of this paper is to present a new technique for analog circuit design implementation that able to compete with pleasurable behaviors of the conventional gate driven transistor with extra bene¯t that the whole circuit is working under low voltage low power area. This paper presents a new ultra-low voltage transconductor based on BD-QFG technique. The low supply voltage, low power consumption and the wide dynamic range are the main attractive features of the proposed circuit. As a possible application a second-order multifunction Gm -C ¯lter is presented to prove the validation of the described technique. Acknowledgments The described research was performed in laboratories supported by the SIX project; the registration number CZ.1.05/2.1.00/03.0072, the operational program Research and Development for Innovation and has been supported by Czech Science Foundation project No.: GA102/11/1379, also by Ministry of Industry and Commerce under the contract FR-TI3/485.
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Ultra-Low Voltage Tunable Transconductor based on BD-QFG
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