Understanding the Basic Advantages of Bulk FinFETs for Sub-and ...
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 59, NO. 7, JULY 2012
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Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements F. Crupi, Member, IEEE, M. Alioto, Senior Member, IEEE, J. Franco, P. Magnone, M. Togo, N. Horiguchi, and G. Groeseneken, Fellow, IEEE
Abstract—This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and nearthreshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high-k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy. Index Terms—Bulk FinFET, digital circuits, subthreshold CMOS, VLSI.
I. I NTRODUCTION
U
LTRALOW-POWER (ULP) operation of digital integrated circuits has paved the way for many new applications such as wireless sensor networks, biomedical and implantable devices/networks, ambient intelligence, and wearable computing. From a circuit-level perspective, ULP operation is enabled by very aggressive voltage scaling below the threshold voltage [1]–[4]. Operation in subthreshold poses many challenges at various levels of abstraction. In general, ultralow-voltage operation determines a degradation in the dc robustness and strong performance penalty and provides no energy gain below a certain voltage. These issues set the limits to the practical voltages that can be employed in ULP systems.
Fig. 1. Cross-sectional TEM image of the bulk FinFET with fin height of 33 nm and fin width of 14 nm.
Better scalability can be obtained by using devices that are more amenable for aggressive voltage scaling. Among them, the bulk FinFET has been widely shown to be a particularly good candidate [5] and has been announced by Intel to be the replacement of bulk CMOS at 22 nm and below. Since the technology used in ULP applications is set by mainstream applications, it is necessary to understand the impact and the potential advantages that can be brought by FinFETs in this context. In this work, various aspects of ULP CMOS logic circuits operating in subthreshold and near threshold are analyzed through wafer measurements of devices. To this purpose, we adopt and extend a methodology recently proposed to perform an early assessment of a newly developed technology [6]–[8]. To have a fair comparison with CMOS technology, planar devices implemented with the same length and similar gate stack as the FinFETs are also comparatively analyzed. The main focus is on the voltage scalability of FinFET w.r.t. planar devices in terms of dc robustness, performance, and energy. II. F IN FET V ERSUS P LANAR D EVICES
Manuscript received January 28, 2012; revised March 30, 2012; accepted May 11, 2012. Date of publication June 19, 2012; date of current version July 13, 2012. This brief was recommended by Associate Editor T. Zhang. F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica, Università della Calabria, 87036 Rende, Italy (e-mail: [email protected]). M. Alioto is with the Dipartimento di Ingegneria dell’Informazione, Università di Siena, 53100 Siena, Italy. J. Franco and G. Groeseneken are with the Interuniversity Microelectronics Center (imec), 3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven, Belgium. P. Magnone is with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES), Università di Bologna, 40125 Bologna, Italy. M. Togo and N. Horiguchi are with the Interuniversity Microelectronics Center (imec), 3001 Leuven, Belgium. Digital Object Identifier 10.1109/TCSII.2012.2200171
Devices were fabricated at imec using 300-mm (100) Si wafers. A cross-sectional transmission electron microscopy (TEM) image showing the triple-gate FinFET architecture of the device is shown in Fig. 1. The gate length (L) of FinFETs under investigation is 60 nm, the fin height (HFIN ) is 33 nm, and the fin width (WFIN ) is 14 nm. Since the drain current flows on the top and on the sidewalls of the fin and since the devices under investigation consisted of five fingers in parallel (NFIN = 5), the total effective width is computed as W = NFIN × (2HFIN + WFIN ) = 400 nm. The gate stack of the FinFET devices consisted of 5-nm physical vapor deposition TiN metal electrode on 2.1-nm HfSiO high-k dielectric in
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TABLE I D EVICE PARAMETERS OF FinFET AND P LANAR MOSFET S
is justified by the assumption that VT can be adjusted by engineering the gate work function. Since we used n-FinFET as a VT reference, after shifting the curves, all the devices show a |VT | of about 300 mV. In the following, we will explore the bias range between 100 and 400 mV, which corresponds to subthreshold (VDD = 100–300 mV) and near-threshold (VDD = 300–400 mV) regimes. Since the FinFET/planar comparison is performed by shifting VT in order to equalize |ID |/W at fixed |VDS |, the obtained results will not significantly depend on the accuracy in the evaluation of the effective fin width, which is a difficult task for the trigate architecture [9]. The subthreshold current of n-FET is given by [10] λDS VDS VDS 0 −λBS VBS ) W VGS −(VTnV t e nVt 1 − e− Vt (1) ID = I0 e L
Fig. 2. Typical I–V curves measured in FinFET and planar devices in the sub- and near-threshold regimes. FinFETs exhibit a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases and a perfect balance between n- and p-types.
addition to 1-nm thermal interfacial oxide. Fins are undoped. For comparison purposes, we characterized also bulk planar n- and p-type devices with the same gate length and with similar gate stack consisting of 1.2 nm of SiO2 , 1.8 nm of HfO2 , and 2-nm TiN metal gate. It is worth noting that the capacitanceequivalent thickness in inversion (Tinv ) of FinFET and planar devices, evaluated at |VGS | = |VT | + 0.6 V, is almost identical for both types of devices (see Table I). Bulk doping in planar devices is 5 × 1017 cm−3 for n-FET, and it is 1017 cm−3 for p-FET. The VT ’s of the investigated FinFET and planar devices are not optimized and are significantly different (see Table I). In order to perform a fair comparison, we shifted the VT in such a way to equalize the |VGS | value required to have |ID |/W = 100 nA/μm at |VDS | = 300 mV [see Fig. 2(a)]. This procedure
where the gate voltage dependence is described by the parameter n or, alternatively, by the subthreshold slope S = nVt ln(10), the drain voltage dependence is described by the coefficient λDS , the body bias dependence is described by the coefficient λBS , and VT 0 indicates VT at VBS = 0. In the following, we will use the same equations also for p-FET by considering the absolute values of current and voltages. Fig. 2 compares the measured drain current dependence on the gate, the drain, and the body biases between FinFET and planar devices. Two important advantages of the FinFET devices can be observed in Fig. 2(a). The first advantage consists of the steeper slope for both types of FinFET w.r.t. planar counterparts as expected by the superior electrostatics of the triple-gate architecture. As reported in Table I, in spite of the channel length of only 60 nm, S is quite close to the ideal value of 60 mV/dec for both types of FinFET (66.1 mV/dec for n-type and 65.2 mV/dec for p-type), while it is significantly larger for both types of planar FET (77.5 mV/dec for n-type and 85.0 mV/dec for p-type). As the second advantage, the nand the p-FinFETs are perfectly balanced, while the planar devices suffer from a larger imbalance. This observation may be ascribed to the fact that the S values of the two types of FinFET are quite close to the ideal S value and, therefore, are close to each other. This perfect balance cannot be obtained in superthreshold regime due to the different behavior of hole and electron mobilities as a function of the gate bias. As shown in Fig. 2(b) and reported in Table I, the FinFET devices show remarkably lower λDS values (26.9 mV/V for n-type and 17.8 mV/V for p-type) w.r.t. planar devices (92.7 mV/V for n-type and 101.0 mV/V for p-type). Also, this desirable property comes from the better electrostatics of the multigate architecture. Different from planar devices, bulk FinFETs do not exhibit appreciable body effect (see Fig. 2(c) and Table I). The
CRUPI et al.: UNDERSTANDING THE BASIC ADVANTAGES OF BULK FinFETs
Fig. 3. Static characteristics of (a) FinFET and (b) planar inverters in suband near-threshold regimes. The curves have been numerically extracted from device wafer measurements.
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Fig. 5. Ion /Ioff versus VDD for FinFET and planar MOSFETs.
the following analytical equations valid in the subthreshold regime [10]: 1 (2) Av = − V − DD ne 2Vt λDS + VDD −
1−e
ΔVSWING = 2Vt e
−
N ML = N M H
Fig. 4. (a) Maximum voltage gain, (b) difference between VDD and the logic swing normalized w.r.t. VDD , (c) low and high noise margins of FinFET and planar CMOS inverters versus VDD .
physical reason is that the body bias is not able to significantly change the potential inside the narrow fin. As a consequence, design circuit techniques based on adaptive body bias are not effective in bulk FinFET technology. Let us note that, since ID in FinFETs exhibits a small dependence on VDS (for VDS > 4Vt ) and is practically independent from VBS , the perfect balance between n- and p-FinFETs observed in Fig. 2(a) extends also to Fig. 2(b) and (c). III. A DVANTAGES OF F IN FET S IN T ERMS OF S TATIC C HARACTERISTICS OF CMOS I NVERTER Fig. 3(a) and (b) shows the static characteristics of a CMOS inverter as a function of VDD in the sub- and near-threshold regimes for FinFET and planar devices. Note that the curves have been numerically extracted from the measurements of ID as a function of VGS and VDS in n- and p-type transistors, without assuming any analytical model or equation. For each value of VI , we extract the VO value which allows to equalize |ID | in n- and p-FETs by interpolation of the measured data. Superior inverter characteristics are clearly observed for the FinFET inverter. As shown in Fig. 4, the FinFET inverter exhibits remarkably better values of the maximum small-signal voltage gain (Av ), of the difference between VDD and the logic swing (ΔVSWING ) normalized w.r.t. VDD , and of the low and high noise margins (N ML and N MH ), as defined in [10]. By assuming perfectly balanced n- and p-FETs, these inverter parameters can be related to the basic device parameters by
2Vt
VDD nVt
nVt VDD − = 2 2
2 ln +1 . n
(3) (4)
Equations (2)–(4) suggest that the observed improvement of Av is mainly due to the lower λDS , while the improvements of ΔVSWING , N ML , and N MH are due to the lower n. Moreover, the parameters of the planar inverter are further degraded by the larger imbalance between the n- and the p-FETs [10]. These results indicate that the FinFETs have significantly improved voltage scalability from the perspective of dc robustness (i.e., the voltage can be scaled more under the same immunity). It is worth noting that the reported analysis does not take into account the process variations, which will degrade the noise margins and the minimum supply voltage. However, as reported in [11] on similar imec devices, the variability of undoped bulk FinFET is lower w.r.t. doped planar devices; thus, the reported advantages of the FinFET inverter will be further increased. In the same paper [11], it has been reported that undoped SOI FinFETs exhibit a remarkably lower variability, thus suggesting that undoped SOI FinFET represents an interesting option for subthreshold logic. IV. A DVANTAGES OF F IN FET S IN T ERMS OF P ERFORMANCE , E NERGY, AND T HEIR S CALABILITY Since the inversion capacitances of FinFET and planar devices are very similar (see Tinv values in Table I), Ion /Ioff represents a basic metric for the energy–delay tradeoff. As expected, FinFETs exhibit remarkably higher and perfectly balanced Ion /Ioff in the sub- and near-threshold regimes (see Fig. 5). Moreover, as reported in [11] on similar imec devices, FinFETs show moderate junction capacitance in the range or even below that of planar devices. In order to estimate the performance of a ULP VLSI system from device measurements, we extracted the delay of a fanout-of-4 inverter (FO4), i.e., the delay of an inverter driving four identical inverters. Indeed, typical ULP processors (e.g., Umich Phoenix processor or the ARM M3 core) have a cycle time that typically ranges from 100 to 200 FO4; hence, for a given microarchitecture, FO4 defines the speed. In Fig. 6, the resulting FO4 is plotted versus VDD for the FinFET and the planar counterpart. From this figure, FinFET has essentially
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has better energy scalability also from an energy perspective. For example, Fig. 7 shows that FinFET exhibits a 1.5× lower minimum energy per cycle, compared to the planar transistor. Also, the MEP of the FinFET (planar) circuit occurs at 125 mV (200 mV). As another benefit, the minimum of the energy curve for the FinFET is flatter than that for the planar counterpart, which relaxes the need for precise tuning of VDD to minimize the energy of the FinFET circuit. V. C ONCLUSION
Fig. 6. FO4 metrics versus VDD (FinFET and planar counterpart).
Fig. 7. Energy per cycle normalized versus VDD (FinFET and planar counterpart).
the same FO4 as the planar counterpart at very low voltages (on the order of 100 mV) and improves faster than the latter when increasing VDD . As shown in Fig. 6, this translates into a 1.5× performance benefit at 200 mV and 2.3× at 300 mV. Accordingly, a VLSI system based on FinFET is able to operate at a lower voltage for a given performance constraint, which confirms the better voltage scalability from the performance perspective. For example, from Fig. 6, the FinFET can operate at 180 mV while keeping the same performance as the planar working at 200 mV. In regard to the energy, subthreshold voltage scaling is beneficial only above the well-known minimum energy point (MEP) [4]. For lower voltages, VDD reduction actually leads to an energy increase, due to the exponential increase in the cycle time at low voltages, which translates into rapidly increasing leakage energy per cycle at the left of MEP [10]. Fig. 7 shows the trend of the energy per cycle in a simple reference circuit made of cascaded inverters with FO4 loads, assuming typical values for the activity factor (5%) and cycle time (200 FO4). In this figure, energy is actually normalized to the minimum energy obtained with the FinFET, to highlight the energy improvement over the planar counterpart. Despite its simplicity, this circuit can actually capture the impact of voltage scaling on the energy of arbitrarily complex systems [1]. According to Fig. 7, the MEP in FinFET circuits occurs at significantly lower voltages, compared to the planar counterpart. In other words, voltage scaling is more beneficial since it enables a larger energy reduction. This is because FinFET has a lower leakage current, which translates into a smaller leakage energy per cycle, which is exactly the energy contribution that prevents any further energy reduction at the left of the MEP. Hence, FinFET
We have analyzed the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements were performed on imec FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and on bulk planar FETs with the same gate length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. the planar devices. Moreover, FinFETs exhibit perfect balance between n- and p-FETs at any voltage in the sub- and near-threshold regimes. We have shown how these superior device properties translate to improved voltage scalability in logic circuits from the perspective of dc robustness and of performance and energy. R EFERENCES [1] M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3–29, Jan. 2012. [2] A. Chandrakasan, D. C. Daly, D. F. Finchelstein, J. Kwong, Y. K. Ramadass, M. E. Sinangil, V. Sze, N. Verma et al., “Technologies for ultradynamic voltage scaling,” Proc. IEEE, vol. 98, no. 2, pp. 191–214, Feb. 2010. [3] J. Rabaey, J. Ammer, B. Otis, F. Burghardt, Y. H. Chee, N. Pletcher, M. Sheets, and H. Qin, “Ultra-low-power design—The roadmap to disappearing electronics and ambient intelligence,” IEEE Circuits Devices Mag., vol. 22, no. 4, pp. 23–29, Jul./Aug. 2006. [4] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005. [5] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 232–245, Feb. 2010. [6] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, and B. De Jaeger, “Understanding the potential and the limits of germanium pMOSFETs for VLSI circuits from experimental measurements,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 9, pp. 1569–1582, Sep. 2011. [7] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, “Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling,” in Proc. IEEE Int. Symp. Circuits Syst., 2011, pp. 2249–2252. [8] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, “Buried silicon–germanium pMOSFETs: Experimental analysis in VLSI circuits under aggressive voltage scaling,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.. doi:DOI:10.1109/TVLSI.2011.2159870. [9] S.-H. Kim, J. G. Fossum, and V. P. Trivedi, “Bulk inversion in FinFETs and implied insights on effective gate width,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993–1997, Sep. 2005. [10] M. Alioto, “Understanding DC behavior of subthreshold CMOS logic through closed-form analysis,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597–1607, Jul. 2010. [11] T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, and T. Hoffmann, “Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession,” Solid State Electron., vol. 54, no. 9, pp. 855–860, Sep. 2010.
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Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements F. Crupi, Member, IEEE, M. Alioto, Senior Member, IEEE, J. Franco, P. Magnone, M. Togo, N. Horiguchi, and G. Groeseneken, Fellow, IEEE
Abstract—This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and nearthreshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high-k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy. Index Terms—Bulk FinFET, digital circuits, subthreshold CMOS, VLSI.
I. I NTRODUCTION
U
LTRALOW-POWER (ULP) operation of digital integrated circuits has paved the way for many new applications such as wireless sensor networks, biomedical and implantable devices/networks, ambient intelligence, and wearable computing. From a circuit-level perspective, ULP operation is enabled by very aggressive voltage scaling below the threshold voltage [1]–[4]. Operation in subthreshold poses many challenges at various levels of abstraction. In general, ultralow-voltage operation determines a degradation in the dc robustness and strong performance penalty and provides no energy gain below a certain voltage. These issues set the limits to the practical voltages that can be employed in ULP systems.
Fig. 1. Cross-sectional TEM image of the bulk FinFET with fin height of 33 nm and fin width of 14 nm.
Better scalability can be obtained by using devices that are more amenable for aggressive voltage scaling. Among them, the bulk FinFET has been widely shown to be a particularly good candidate [5] and has been announced by Intel to be the replacement of bulk CMOS at 22 nm and below. Since the technology used in ULP applications is set by mainstream applications, it is necessary to understand the impact and the potential advantages that can be brought by FinFETs in this context. In this work, various aspects of ULP CMOS logic circuits operating in subthreshold and near threshold are analyzed through wafer measurements of devices. To this purpose, we adopt and extend a methodology recently proposed to perform an early assessment of a newly developed technology [6]–[8]. To have a fair comparison with CMOS technology, planar devices implemented with the same length and similar gate stack as the FinFETs are also comparatively analyzed. The main focus is on the voltage scalability of FinFET w.r.t. planar devices in terms of dc robustness, performance, and energy. II. F IN FET V ERSUS P LANAR D EVICES
Manuscript received January 28, 2012; revised March 30, 2012; accepted May 11, 2012. Date of publication June 19, 2012; date of current version July 13, 2012. This brief was recommended by Associate Editor T. Zhang. F. Crupi is with the Dipartimento di Elettronica, Informatica e Sistemistica, Università della Calabria, 87036 Rende, Italy (e-mail: [email protected]). M. Alioto is with the Dipartimento di Ingegneria dell’Informazione, Università di Siena, 53100 Siena, Italy. J. Franco and G. Groeseneken are with the Interuniversity Microelectronics Center (imec), 3001 Leuven, Belgium, and also with the Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, 3001 Leuven, Belgium. P. Magnone is with the Advanced Research Center on Electronic Systems for Information and Communication Technologies E. De Castro (ARCES), Università di Bologna, 40125 Bologna, Italy. M. Togo and N. Horiguchi are with the Interuniversity Microelectronics Center (imec), 3001 Leuven, Belgium. Digital Object Identifier 10.1109/TCSII.2012.2200171
Devices were fabricated at imec using 300-mm (100) Si wafers. A cross-sectional transmission electron microscopy (TEM) image showing the triple-gate FinFET architecture of the device is shown in Fig. 1. The gate length (L) of FinFETs under investigation is 60 nm, the fin height (HFIN ) is 33 nm, and the fin width (WFIN ) is 14 nm. Since the drain current flows on the top and on the sidewalls of the fin and since the devices under investigation consisted of five fingers in parallel (NFIN = 5), the total effective width is computed as W = NFIN × (2HFIN + WFIN ) = 400 nm. The gate stack of the FinFET devices consisted of 5-nm physical vapor deposition TiN metal electrode on 2.1-nm HfSiO high-k dielectric in
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TABLE I D EVICE PARAMETERS OF FinFET AND P LANAR MOSFET S
is justified by the assumption that VT can be adjusted by engineering the gate work function. Since we used n-FinFET as a VT reference, after shifting the curves, all the devices show a |VT | of about 300 mV. In the following, we will explore the bias range between 100 and 400 mV, which corresponds to subthreshold (VDD = 100–300 mV) and near-threshold (VDD = 300–400 mV) regimes. Since the FinFET/planar comparison is performed by shifting VT in order to equalize |ID |/W at fixed |VDS |, the obtained results will not significantly depend on the accuracy in the evaluation of the effective fin width, which is a difficult task for the trigate architecture [9]. The subthreshold current of n-FET is given by [10] λDS VDS VDS 0 −λBS VBS ) W VGS −(VTnV t e nVt 1 − e− Vt (1) ID = I0 e L
Fig. 2. Typical I–V curves measured in FinFET and planar devices in the sub- and near-threshold regimes. FinFETs exhibit a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases and a perfect balance between n- and p-types.
addition to 1-nm thermal interfacial oxide. Fins are undoped. For comparison purposes, we characterized also bulk planar n- and p-type devices with the same gate length and with similar gate stack consisting of 1.2 nm of SiO2 , 1.8 nm of HfO2 , and 2-nm TiN metal gate. It is worth noting that the capacitanceequivalent thickness in inversion (Tinv ) of FinFET and planar devices, evaluated at |VGS | = |VT | + 0.6 V, is almost identical for both types of devices (see Table I). Bulk doping in planar devices is 5 × 1017 cm−3 for n-FET, and it is 1017 cm−3 for p-FET. The VT ’s of the investigated FinFET and planar devices are not optimized and are significantly different (see Table I). In order to perform a fair comparison, we shifted the VT in such a way to equalize the |VGS | value required to have |ID |/W = 100 nA/μm at |VDS | = 300 mV [see Fig. 2(a)]. This procedure
where the gate voltage dependence is described by the parameter n or, alternatively, by the subthreshold slope S = nVt ln(10), the drain voltage dependence is described by the coefficient λDS , the body bias dependence is described by the coefficient λBS , and VT 0 indicates VT at VBS = 0. In the following, we will use the same equations also for p-FET by considering the absolute values of current and voltages. Fig. 2 compares the measured drain current dependence on the gate, the drain, and the body biases between FinFET and planar devices. Two important advantages of the FinFET devices can be observed in Fig. 2(a). The first advantage consists of the steeper slope for both types of FinFET w.r.t. planar counterparts as expected by the superior electrostatics of the triple-gate architecture. As reported in Table I, in spite of the channel length of only 60 nm, S is quite close to the ideal value of 60 mV/dec for both types of FinFET (66.1 mV/dec for n-type and 65.2 mV/dec for p-type), while it is significantly larger for both types of planar FET (77.5 mV/dec for n-type and 85.0 mV/dec for p-type). As the second advantage, the nand the p-FinFETs are perfectly balanced, while the planar devices suffer from a larger imbalance. This observation may be ascribed to the fact that the S values of the two types of FinFET are quite close to the ideal S value and, therefore, are close to each other. This perfect balance cannot be obtained in superthreshold regime due to the different behavior of hole and electron mobilities as a function of the gate bias. As shown in Fig. 2(b) and reported in Table I, the FinFET devices show remarkably lower λDS values (26.9 mV/V for n-type and 17.8 mV/V for p-type) w.r.t. planar devices (92.7 mV/V for n-type and 101.0 mV/V for p-type). Also, this desirable property comes from the better electrostatics of the multigate architecture. Different from planar devices, bulk FinFETs do not exhibit appreciable body effect (see Fig. 2(c) and Table I). The
CRUPI et al.: UNDERSTANDING THE BASIC ADVANTAGES OF BULK FinFETs
Fig. 3. Static characteristics of (a) FinFET and (b) planar inverters in suband near-threshold regimes. The curves have been numerically extracted from device wafer measurements.
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Fig. 5. Ion /Ioff versus VDD for FinFET and planar MOSFETs.
the following analytical equations valid in the subthreshold regime [10]: 1 (2) Av = − V − DD ne 2Vt λDS + VDD −
1−e
ΔVSWING = 2Vt e
−
N ML = N M H
Fig. 4. (a) Maximum voltage gain, (b) difference between VDD and the logic swing normalized w.r.t. VDD , (c) low and high noise margins of FinFET and planar CMOS inverters versus VDD .
physical reason is that the body bias is not able to significantly change the potential inside the narrow fin. As a consequence, design circuit techniques based on adaptive body bias are not effective in bulk FinFET technology. Let us note that, since ID in FinFETs exhibits a small dependence on VDS (for VDS > 4Vt ) and is practically independent from VBS , the perfect balance between n- and p-FinFETs observed in Fig. 2(a) extends also to Fig. 2(b) and (c). III. A DVANTAGES OF F IN FET S IN T ERMS OF S TATIC C HARACTERISTICS OF CMOS I NVERTER Fig. 3(a) and (b) shows the static characteristics of a CMOS inverter as a function of VDD in the sub- and near-threshold regimes for FinFET and planar devices. Note that the curves have been numerically extracted from the measurements of ID as a function of VGS and VDS in n- and p-type transistors, without assuming any analytical model or equation. For each value of VI , we extract the VO value which allows to equalize |ID | in n- and p-FETs by interpolation of the measured data. Superior inverter characteristics are clearly observed for the FinFET inverter. As shown in Fig. 4, the FinFET inverter exhibits remarkably better values of the maximum small-signal voltage gain (Av ), of the difference between VDD and the logic swing (ΔVSWING ) normalized w.r.t. VDD , and of the low and high noise margins (N ML and N MH ), as defined in [10]. By assuming perfectly balanced n- and p-FETs, these inverter parameters can be related to the basic device parameters by
2Vt
VDD nVt
nVt VDD − = 2 2
2 ln +1 . n
(3) (4)
Equations (2)–(4) suggest that the observed improvement of Av is mainly due to the lower λDS , while the improvements of ΔVSWING , N ML , and N MH are due to the lower n. Moreover, the parameters of the planar inverter are further degraded by the larger imbalance between the n- and the p-FETs [10]. These results indicate that the FinFETs have significantly improved voltage scalability from the perspective of dc robustness (i.e., the voltage can be scaled more under the same immunity). It is worth noting that the reported analysis does not take into account the process variations, which will degrade the noise margins and the minimum supply voltage. However, as reported in [11] on similar imec devices, the variability of undoped bulk FinFET is lower w.r.t. doped planar devices; thus, the reported advantages of the FinFET inverter will be further increased. In the same paper [11], it has been reported that undoped SOI FinFETs exhibit a remarkably lower variability, thus suggesting that undoped SOI FinFET represents an interesting option for subthreshold logic. IV. A DVANTAGES OF F IN FET S IN T ERMS OF P ERFORMANCE , E NERGY, AND T HEIR S CALABILITY Since the inversion capacitances of FinFET and planar devices are very similar (see Tinv values in Table I), Ion /Ioff represents a basic metric for the energy–delay tradeoff. As expected, FinFETs exhibit remarkably higher and perfectly balanced Ion /Ioff in the sub- and near-threshold regimes (see Fig. 5). Moreover, as reported in [11] on similar imec devices, FinFETs show moderate junction capacitance in the range or even below that of planar devices. In order to estimate the performance of a ULP VLSI system from device measurements, we extracted the delay of a fanout-of-4 inverter (FO4), i.e., the delay of an inverter driving four identical inverters. Indeed, typical ULP processors (e.g., Umich Phoenix processor or the ARM M3 core) have a cycle time that typically ranges from 100 to 200 FO4; hence, for a given microarchitecture, FO4 defines the speed. In Fig. 6, the resulting FO4 is plotted versus VDD for the FinFET and the planar counterpart. From this figure, FinFET has essentially
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has better energy scalability also from an energy perspective. For example, Fig. 7 shows that FinFET exhibits a 1.5× lower minimum energy per cycle, compared to the planar transistor. Also, the MEP of the FinFET (planar) circuit occurs at 125 mV (200 mV). As another benefit, the minimum of the energy curve for the FinFET is flatter than that for the planar counterpart, which relaxes the need for precise tuning of VDD to minimize the energy of the FinFET circuit. V. C ONCLUSION
Fig. 6. FO4 metrics versus VDD (FinFET and planar counterpart).
Fig. 7. Energy per cycle normalized versus VDD (FinFET and planar counterpart).
the same FO4 as the planar counterpart at very low voltages (on the order of 100 mV) and improves faster than the latter when increasing VDD . As shown in Fig. 6, this translates into a 1.5× performance benefit at 200 mV and 2.3× at 300 mV. Accordingly, a VLSI system based on FinFET is able to operate at a lower voltage for a given performance constraint, which confirms the better voltage scalability from the performance perspective. For example, from Fig. 6, the FinFET can operate at 180 mV while keeping the same performance as the planar working at 200 mV. In regard to the energy, subthreshold voltage scaling is beneficial only above the well-known minimum energy point (MEP) [4]. For lower voltages, VDD reduction actually leads to an energy increase, due to the exponential increase in the cycle time at low voltages, which translates into rapidly increasing leakage energy per cycle at the left of MEP [10]. Fig. 7 shows the trend of the energy per cycle in a simple reference circuit made of cascaded inverters with FO4 loads, assuming typical values for the activity factor (5%) and cycle time (200 FO4). In this figure, energy is actually normalized to the minimum energy obtained with the FinFET, to highlight the energy improvement over the planar counterpart. Despite its simplicity, this circuit can actually capture the impact of voltage scaling on the energy of arbitrarily complex systems [1]. According to Fig. 7, the MEP in FinFET circuits occurs at significantly lower voltages, compared to the planar counterpart. In other words, voltage scaling is more beneficial since it enables a larger energy reduction. This is because FinFET has a lower leakage current, which translates into a smaller leakage energy per cycle, which is exactly the energy contribution that prevents any further energy reduction at the left of the MEP. Hence, FinFET
We have analyzed the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements were performed on imec FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and on bulk planar FETs with the same gate length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. the planar devices. Moreover, FinFETs exhibit perfect balance between n- and p-FETs at any voltage in the sub- and near-threshold regimes. We have shown how these superior device properties translate to improved voltage scalability in logic circuits from the perspective of dc robustness and of performance and energy. R EFERENCES [1] M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3–29, Jan. 2012. [2] A. Chandrakasan, D. C. Daly, D. F. Finchelstein, J. Kwong, Y. K. Ramadass, M. E. Sinangil, V. Sze, N. Verma et al., “Technologies for ultradynamic voltage scaling,” Proc. IEEE, vol. 98, no. 2, pp. 191–214, Feb. 2010. [3] J. Rabaey, J. Ammer, B. Otis, F. Burghardt, Y. H. Chee, N. Pletcher, M. Sheets, and H. Qin, “Ultra-low-power design—The roadmap to disappearing electronics and ambient intelligence,” IEEE Circuits Devices Mag., vol. 22, no. 4, pp. 23–29, Jul./Aug. 2006. [4] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310–319, Jan. 2005. [5] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 232–245, Feb. 2010. [6] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, and B. De Jaeger, “Understanding the potential and the limits of germanium pMOSFETs for VLSI circuits from experimental measurements,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 9, pp. 1569–1582, Sep. 2011. [7] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, “Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling,” in Proc. IEEE Int. Symp. Circuits Syst., 2011, pp. 2249–2252. [8] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, and T. Y. Hoffmann, “Buried silicon–germanium pMOSFETs: Experimental analysis in VLSI circuits under aggressive voltage scaling,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.. doi:DOI:10.1109/TVLSI.2011.2159870. [9] S.-H. Kim, J. G. Fossum, and V. P. Trivedi, “Bulk inversion in FinFETs and implied insights on effective gate width,” IEEE Trans. Electron Devices, vol. 52, no. 9, pp. 1993–1997, Sep. 2005. [10] M. Alioto, “Understanding DC behavior of subthreshold CMOS logic through closed-form analysis,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1597–1607, Jul. 2010. [11] T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, and T. Hoffmann, “Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession,” Solid State Electron., vol. 54, no. 9, pp. 855–860, Sep. 2010.
