Verification of Digitally-Intensive Analog Circuits ... - Semantic Scholar
Verification of Digitally-Intensive Analog Circuits via Kernel Ridge Regression and Hybrid Reachability Analysis Honghuang Lin
Peng Li
Chris J. Myers
Texas A&M University [email protected]
Texas A&M University [email protected]
University of Utah [email protected]
ABSTRACT The emergence of digitally-intensive analog circuits introduces new challenges to formal verification due to increased digital design content, and non-ideal digital effects such as finite resolution, round-off error and overflow. We propose a machine learning approach to convert digital blocks to conservative analog approximations via the use of kernel ridge regression. These learned models are then adopted in a hybrid formal reachability analysis framework where the support function based manipulations are developed to efficiently handle the large linear portion of the design and the more general satisfiability modulo theories technique is applied to the remaining nonlinear portion. The efficiency of the proposed method is demonstrated for the locked time verification of a digitally intensive phase locked loop.
1.
INTRODUCTION
Designing analog/mixed-signal (AMS) circuits in highly scaled CMOS technologies is hampered by increasing ProcessVoltage-Temperature (PVT) variations and worsening device characteristics. As a result, the so-called digitally-assisted or digitally-intensive analog (DIA) design methodology has emerged, which minimizes the pure analog content of the design while relying more on digital processing [1]. However, inclusion of increased digital content in such designs adds new complications to the existing challenges of AMS circuit design verification, which are the result of effects such as nonlinear dynamical characteristics and complex interactions between digital and analog signals. This work aims to develop verification techniques for DIA circuits under a formal reachability analysis framework [2] [3] [4]. The interaction between digital (Boolean) and continuousvalued analog signals is intensified in DIA circuits, presenting a key challenge in verification. In addition, to fully capture “digital” effects such as finite resolution (inherent in any analog-to-digital conversion), round-off error and overflow (inherent in additions/multiplications due to finite word length effects), additional state variables need to be introduced, blowing up the dimensionality of the state space and slowing down the reachability analysis. The first main idea of this work is to “unify” the two
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13 May 29 - June 07 2013, Austin, TX, USA Copyright 2013 ACM 978-1-4503-2071-9/13/05 ...$15.00.
types of signals by converting digital signals into approximate analog signals. More precisely, this paper leverages machine learning to find the potential error of the conversion on a given digital block and bound its output using a continuous analog signal and a tight error interval. It turns out kernel based learning methods such as support vector machines [5] [6] are useful tools for this purpose. In particular, this paper adopts kernel ridge regression [7] [8] and the related confidence interval computing algorithm [9] to construct such “analog” models for the digital block and estimate the error interval, the latter of which ensures the conservativeness of this conversion as required by formal verification. The accuracy of this “digital-to-analog” modeling, e.g. the length of the error interval, is tightly controlled in the learning process. Note that approximating (digital) quantization effects by including additive quantization noise has been used to provide empirical noise analysis for analogto-digital converter designs for decades. However, to the best of our knowledge, this is the first time systematically learned “analog” models for digital blocks has been used in formal verification. The second contribution of this work is to further speedup reachability analysis by partitioning an AMS design into a linear and a nonlinear subsystem and adopting efficient support-function based state space manipulations. This paper over-approximates the reachable state space by using tight polyhedral convex sets based on the support function representation. The use of support functions alleviates the resolution problem of the box state space discretization adopted in the simulation-assisted Satisfiability Modulo Theories (SMT) based reachability analysis developed for general AMS circuits [4] [10]. Support functions have been used before for reachability analysis [11], where the entire system is assumed to be linear and efficient progression of support functions are used to track the linear transition of the state space. To verify more general nonlinear AMS circuits, this paper develops a modified support-function approach for the linear sub-system while adopting the more general SMT technique for the remaining nonlinear subsystem. This paper also proposes specific support function manipulation techniques to efficiently track the reachable state space of the linear sub-system. While the second school of our ideas can be applied to generic AMS circuits [12], our experience has shown them to be particularly appealing to DIA circuits. DIA circuits are constructed to have high digital content with minimum use of pure analog-based processing. Digital blocks such as filters are designed to be “linear” and implemented in robust digital logic. However, this linearity disappears in the presence of round-off errors due to finite word length effects. The use of the machine learned conservative analog models re-establishes this lost linearity and allows application
of the proposed support function approach to a more dominant portion of the design, which is modeled as the linear sub-system. This paper demonstrates the proposed techniques to the challenging task of locked time verification of a digitally-intensive phase-locked loop (DI-PLL).
proach is guaranteed by the use of error intervals that are part of the abstract model.
3.
MODEL ABSTRACTION
3.1 2.
VERIFICATION CHALLENGES
The DI-PLL studied in this paper is shown in Fig. 1. The circuit involves an analog feedback path from the digital controlled oscillator (DCO) to the phase detector. The phase detector uses an accumulator and a time-to-digital converter (TDC) to detect the only analog variable, which is the phase difference Δφ between the reference clock REF and the output signal CKV , and then outputs the phase difference to the loop filter to control the DCO. Neglecting the digital effects and assuming all functional blocks have an ideal continuous characteristics, the verification of the system can be performed on a model involving a few state variables such as ones to capture the input/output/internal signals of the loop filter. However, to fully capture those digital effects, more state variables are needed and hence the model has a much higher complexity. WŚĂƐĞĞƚĞĐƚŽƌ н н Z & Ͳ н
>ŽŽƉ&ŝůƚĞƌ //Z
K <s
ĐĐƵŵƵůĂƚŽƌ d
Figure 1: Block diagram for a DI-PLL. For example, a TDC shown in Fig. 2(a) is used to measure the fractional phase difference between CKV and REF . Theoretically, the output of the TDC should be proportional to the fractional phase difference, making the transition of the phase detector linear. However, the finite delay of the inverters limits the achievable resolution of the TDC. As a result, the phase detector with a finite TDC resolution has a staircase transition curve instead of an ideal linear one. Digital filters such as FIR or IIR filters are often designed from a linear z-domain transfer function. To model the ideal transfer function of a second order IIR loop filter shown in Fig. 2(b), four state variables are sufficient. But to fully model the finite word length effects such as overflow and round-off error of the filter, 8 more variables should be assigned to the output nodes of all the internal adders and multipliers. The dimension of the system is thus greatly increased. <s yŶ
ďϬ
н
н
н
н
zŶ
njͲϭ
njͲϭ ďϭ
Z & WƐĞƵĚŽͲdŚĞƌŵŽŵĞƚĞƌͲŽĚĞ ĚŐĞĞƚĞĐƚŽƌ dͺZ/^ dͺ&>>
(a)
njͲϭ
ͲĂϭ njͲϭ
ďϮ
Digital Abstraction with Analog Variables
An AMS system consists of analog and digital variables along with continuous and discrete transitions and state mapping functions. It can generally be defined as: Definition 1. An AMS system is a tuple HAM S = (Xa , Xd , Rres , Fa , Fb ) where: • Xa ⊆ Rn is a set of continuous variables; • Xd ⊂ Rm is a set of discrete variables; • Rres ∈ Rm is the resolution of the discrete variables; • Fa : (Xa , Xd ) → Rn is the mapping functions to the continuous state variables; • Fd : (Xa , Xd , Rres ) → Rm is the mapping functions to the discrete state variables. As discussed in the previous section, the size of Xd and Fd in a DIA system may be large which may blow up the dimension of the state space for verification. From the design perspective, to focus on the key properties of the digital functional blocks, it is common to approximate mapping functions in Fd with continuous mapping functions while independent error variables are added into Xa to cover the approximation error. Fox example, a TDC is routinely modeled to have a linear conversion characteristics and additive quantization errors, the latter of which is used to analyze the TDC induced noise [14]. Motivated by the above design analysis technique, our method converts key variables in Xd into analog variables and approximates Fd with continuous mappings to simplify the system. However, the goal of our method is to find a conservative approximation for the entire reachable state space rather than analyzing the “average” noise behavior of the circuit. This prompts us to find conservative error intervals, ideally tight, for our abstract models. Let us define the abstracted model produced by our proposed method as: Definition 2. An abstraction of HAM S is a tuple HC = (X, F, Eu , El ) where: • X ⊆ RN consists of Xa and continuous approximation of Xd ; • F : X → RN is the set of mapping functions that consists of Fa and continuous approximation of Fd ; • Eu : X → RN is the upper bound of the error intervals of F (X);
ͲĂϮ
(b)
Figure 2: (a) Time-to-digital converter [13]; (b) Second order IIR filter. To address the above verification challenges, this paper proposes to extract an abstract continuous model with a lower dimensionality for a given DIA design through the use of learning-based regression. The correctness of our ap-
• El : X → RN is the lower bound of the error intervals of F (X). To extract an abstract continuous model from the DIPLL, all the digital variables in Xd such as the input/output of the phase detector and the loop filter are approximated by the corresponding continuous variables in X. Then, for all the digital blocks, the transition function will be approximated by the ideal characteristic. For example, the transition of the phase detector is modeled as a linear function that produces an output proportional to the detected phase
difference. The transition of the filter is modeled by its ideal z-domain transfer function, which is also a linear mapping function that maps the input and internal storage of the filter to its output at the next sampling clock cycle. Error accumulation is an inherent problem in reachability analysis. If the system abstraction comes with loose error intervals, i.e. large Eu − El , the reachability analysis may converge slower or, even worse, may no longer converge. If the error intervals are too narrow, i.e. small Eu − El , the abstraction may lose conservativeness and the result of the reachability analysis is not ensured to cover all the possible cases. So it is important and essential to find a tight interval that covers most of the errors with small over approximation. The next subsection leverages kernel ridge regression (KRR) to compute such tight intervals.
ˆ m(x)) B( ˆ = L(x)T m ˆ − m(x) ˆ
(5)
T
where m ˆ = (m(X ˆ 1 ), ..., m(X ˆ n )) . The variance of the prediction at x is given as ˆ 2 L(x) Vˆ (m(x)) ˆ = L(x)T Σ
(6)
ˆ 2 = diag(ˆ σ 2 (X1 ), ..., σ ˆ 2 (Xn )) and where Σ σ ˆ 2 (x) =
L(x)T diag(ˆ ˆT ) T T 1 + L(x) (SS − S − S T )
(7)
S denotes the smoother matrix of the initial smooth and ˆ denotes the residuals of m(X ˆ 1 ), ..., m(X ˆ n ).
Error Interval Estimation via KRR
w,b,e
/^LJƐƚĞŵ
KRR [7], a.k.a. least squares support vector regression (LS-SVR) [8] is a very effective statistical learning method and has been applied to error estimation. It is formulated as: n min wT w + γ e2i (1)
yĂ yĚ &Ă
y
Peng Li
Chris J. Myers
Texas A&M University [email protected]
Texas A&M University [email protected]
University of Utah [email protected]
ABSTRACT The emergence of digitally-intensive analog circuits introduces new challenges to formal verification due to increased digital design content, and non-ideal digital effects such as finite resolution, round-off error and overflow. We propose a machine learning approach to convert digital blocks to conservative analog approximations via the use of kernel ridge regression. These learned models are then adopted in a hybrid formal reachability analysis framework where the support function based manipulations are developed to efficiently handle the large linear portion of the design and the more general satisfiability modulo theories technique is applied to the remaining nonlinear portion. The efficiency of the proposed method is demonstrated for the locked time verification of a digitally intensive phase locked loop.
1.
INTRODUCTION
Designing analog/mixed-signal (AMS) circuits in highly scaled CMOS technologies is hampered by increasing ProcessVoltage-Temperature (PVT) variations and worsening device characteristics. As a result, the so-called digitally-assisted or digitally-intensive analog (DIA) design methodology has emerged, which minimizes the pure analog content of the design while relying more on digital processing [1]. However, inclusion of increased digital content in such designs adds new complications to the existing challenges of AMS circuit design verification, which are the result of effects such as nonlinear dynamical characteristics and complex interactions between digital and analog signals. This work aims to develop verification techniques for DIA circuits under a formal reachability analysis framework [2] [3] [4]. The interaction between digital (Boolean) and continuousvalued analog signals is intensified in DIA circuits, presenting a key challenge in verification. In addition, to fully capture “digital” effects such as finite resolution (inherent in any analog-to-digital conversion), round-off error and overflow (inherent in additions/multiplications due to finite word length effects), additional state variables need to be introduced, blowing up the dimensionality of the state space and slowing down the reachability analysis. The first main idea of this work is to “unify” the two
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DAC’13 May 29 - June 07 2013, Austin, TX, USA Copyright 2013 ACM 978-1-4503-2071-9/13/05 ...$15.00.
types of signals by converting digital signals into approximate analog signals. More precisely, this paper leverages machine learning to find the potential error of the conversion on a given digital block and bound its output using a continuous analog signal and a tight error interval. It turns out kernel based learning methods such as support vector machines [5] [6] are useful tools for this purpose. In particular, this paper adopts kernel ridge regression [7] [8] and the related confidence interval computing algorithm [9] to construct such “analog” models for the digital block and estimate the error interval, the latter of which ensures the conservativeness of this conversion as required by formal verification. The accuracy of this “digital-to-analog” modeling, e.g. the length of the error interval, is tightly controlled in the learning process. Note that approximating (digital) quantization effects by including additive quantization noise has been used to provide empirical noise analysis for analogto-digital converter designs for decades. However, to the best of our knowledge, this is the first time systematically learned “analog” models for digital blocks has been used in formal verification. The second contribution of this work is to further speedup reachability analysis by partitioning an AMS design into a linear and a nonlinear subsystem and adopting efficient support-function based state space manipulations. This paper over-approximates the reachable state space by using tight polyhedral convex sets based on the support function representation. The use of support functions alleviates the resolution problem of the box state space discretization adopted in the simulation-assisted Satisfiability Modulo Theories (SMT) based reachability analysis developed for general AMS circuits [4] [10]. Support functions have been used before for reachability analysis [11], where the entire system is assumed to be linear and efficient progression of support functions are used to track the linear transition of the state space. To verify more general nonlinear AMS circuits, this paper develops a modified support-function approach for the linear sub-system while adopting the more general SMT technique for the remaining nonlinear subsystem. This paper also proposes specific support function manipulation techniques to efficiently track the reachable state space of the linear sub-system. While the second school of our ideas can be applied to generic AMS circuits [12], our experience has shown them to be particularly appealing to DIA circuits. DIA circuits are constructed to have high digital content with minimum use of pure analog-based processing. Digital blocks such as filters are designed to be “linear” and implemented in robust digital logic. However, this linearity disappears in the presence of round-off errors due to finite word length effects. The use of the machine learned conservative analog models re-establishes this lost linearity and allows application
of the proposed support function approach to a more dominant portion of the design, which is modeled as the linear sub-system. This paper demonstrates the proposed techniques to the challenging task of locked time verification of a digitally-intensive phase-locked loop (DI-PLL).
proach is guaranteed by the use of error intervals that are part of the abstract model.
3.
MODEL ABSTRACTION
3.1 2.
VERIFICATION CHALLENGES
The DI-PLL studied in this paper is shown in Fig. 1. The circuit involves an analog feedback path from the digital controlled oscillator (DCO) to the phase detector. The phase detector uses an accumulator and a time-to-digital converter (TDC) to detect the only analog variable, which is the phase difference Δφ between the reference clock REF and the output signal CKV , and then outputs the phase difference to the loop filter to control the DCO. Neglecting the digital effects and assuming all functional blocks have an ideal continuous characteristics, the verification of the system can be performed on a model involving a few state variables such as ones to capture the input/output/internal signals of the loop filter. However, to fully capture those digital effects, more state variables are needed and hence the model has a much higher complexity. WŚĂƐĞĞƚĞĐƚŽƌ н н Z & Ͳ н
>ŽŽƉ&ŝůƚĞƌ //Z
K <s
ĐĐƵŵƵůĂƚŽƌ d
Figure 1: Block diagram for a DI-PLL. For example, a TDC shown in Fig. 2(a) is used to measure the fractional phase difference between CKV and REF . Theoretically, the output of the TDC should be proportional to the fractional phase difference, making the transition of the phase detector linear. However, the finite delay of the inverters limits the achievable resolution of the TDC. As a result, the phase detector with a finite TDC resolution has a staircase transition curve instead of an ideal linear one. Digital filters such as FIR or IIR filters are often designed from a linear z-domain transfer function. To model the ideal transfer function of a second order IIR loop filter shown in Fig. 2(b), four state variables are sufficient. But to fully model the finite word length effects such as overflow and round-off error of the filter, 8 more variables should be assigned to the output nodes of all the internal adders and multipliers. The dimension of the system is thus greatly increased. <s yŶ
ďϬ
н
н
н
н
zŶ
njͲϭ
njͲϭ ďϭ
Z & WƐĞƵĚŽͲdŚĞƌŵŽŵĞƚĞƌͲŽĚĞ ĚŐĞĞƚĞĐƚŽƌ dͺZ/^ dͺ&>>
(a)
njͲϭ
ͲĂϭ njͲϭ
ďϮ
Digital Abstraction with Analog Variables
An AMS system consists of analog and digital variables along with continuous and discrete transitions and state mapping functions. It can generally be defined as: Definition 1. An AMS system is a tuple HAM S = (Xa , Xd , Rres , Fa , Fb ) where: • Xa ⊆ Rn is a set of continuous variables; • Xd ⊂ Rm is a set of discrete variables; • Rres ∈ Rm is the resolution of the discrete variables; • Fa : (Xa , Xd ) → Rn is the mapping functions to the continuous state variables; • Fd : (Xa , Xd , Rres ) → Rm is the mapping functions to the discrete state variables. As discussed in the previous section, the size of Xd and Fd in a DIA system may be large which may blow up the dimension of the state space for verification. From the design perspective, to focus on the key properties of the digital functional blocks, it is common to approximate mapping functions in Fd with continuous mapping functions while independent error variables are added into Xa to cover the approximation error. Fox example, a TDC is routinely modeled to have a linear conversion characteristics and additive quantization errors, the latter of which is used to analyze the TDC induced noise [14]. Motivated by the above design analysis technique, our method converts key variables in Xd into analog variables and approximates Fd with continuous mappings to simplify the system. However, the goal of our method is to find a conservative approximation for the entire reachable state space rather than analyzing the “average” noise behavior of the circuit. This prompts us to find conservative error intervals, ideally tight, for our abstract models. Let us define the abstracted model produced by our proposed method as: Definition 2. An abstraction of HAM S is a tuple HC = (X, F, Eu , El ) where: • X ⊆ RN consists of Xa and continuous approximation of Xd ; • F : X → RN is the set of mapping functions that consists of Fa and continuous approximation of Fd ; • Eu : X → RN is the upper bound of the error intervals of F (X);
ͲĂϮ
(b)
Figure 2: (a) Time-to-digital converter [13]; (b) Second order IIR filter. To address the above verification challenges, this paper proposes to extract an abstract continuous model with a lower dimensionality for a given DIA design through the use of learning-based regression. The correctness of our ap-
• El : X → RN is the lower bound of the error intervals of F (X). To extract an abstract continuous model from the DIPLL, all the digital variables in Xd such as the input/output of the phase detector and the loop filter are approximated by the corresponding continuous variables in X. Then, for all the digital blocks, the transition function will be approximated by the ideal characteristic. For example, the transition of the phase detector is modeled as a linear function that produces an output proportional to the detected phase
difference. The transition of the filter is modeled by its ideal z-domain transfer function, which is also a linear mapping function that maps the input and internal storage of the filter to its output at the next sampling clock cycle. Error accumulation is an inherent problem in reachability analysis. If the system abstraction comes with loose error intervals, i.e. large Eu − El , the reachability analysis may converge slower or, even worse, may no longer converge. If the error intervals are too narrow, i.e. small Eu − El , the abstraction may lose conservativeness and the result of the reachability analysis is not ensured to cover all the possible cases. So it is important and essential to find a tight interval that covers most of the errors with small over approximation. The next subsection leverages kernel ridge regression (KRR) to compute such tight intervals.
ˆ m(x)) B( ˆ = L(x)T m ˆ − m(x) ˆ
(5)
T
where m ˆ = (m(X ˆ 1 ), ..., m(X ˆ n )) . The variance of the prediction at x is given as ˆ 2 L(x) Vˆ (m(x)) ˆ = L(x)T Σ
(6)
ˆ 2 = diag(ˆ σ 2 (X1 ), ..., σ ˆ 2 (Xn )) and where Σ σ ˆ 2 (x) =
L(x)T diag(ˆ ˆT ) T T 1 + L(x) (SS − S − S T )
(7)
S denotes the smoother matrix of the initial smooth and ˆ denotes the residuals of m(X ˆ 1 ), ..., m(X ˆ n ).
Error Interval Estimation via KRR
w,b,e
/^LJƐƚĞŵ
KRR [7], a.k.a. least squares support vector regression (LS-SVR) [8] is a very effective statistical learning method and has been applied to error estimation. It is formulated as: n min wT w + γ e2i (1)
yĂ yĚ &Ă
y
