(VTC) Circuit for Time-Based Analog-to-Digital ... - IEEE Xplore
Highly-Linear Voltage-to-Time Converter (VTC) Circuit for Time-Based Analog-to-Digital Converters (T-ADCs) Hassan Mostafa1 and Yehea I. Ismail2 and Communications Engineering Department, Cairo University, Giza 12613 , Egypt, Center for Nanoelectronics and Devices, AUC and Zewail City of Science and Technology, New Cairo 11835, Egypt. {[email protected], [email protected], [email protected] } 1 Electronics
1,2
Abstract—Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-toTime Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz. Index Terms—Nanometer CMOS technology, voltage-to-time converter, time-based analog-to-digital converter, software radio receivers.
I. I NTRODUCTION A software radio receiver is one of the most important emerging technologies for future wireless Ultra Wide Band (UWB) communication services. In this receiver, the received noisy RF analog signal is directly applied to a wide-band Analog-to-Digital Converter (ADC), followed by the real time Digital Signal Processor (DSP). The high demand for highspeed low-power ADCs for software radio receivers has led to the design of time-based ADCs. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-toDigital Converter (TDC) circuit as portrayed in Figure 1 [1]. The VTC is also referred to as either a Pulse Position Modulator (PPM) or Pulse Width Modulator (PWM), depending on whether the delay is applied to one or both edges of the input clock pulses. The TDC circuit consists of digital logic and counter circuits [2]. The time-based ADC can operate at very high clock and input frequencies while consuming less power and die area compared to other conventional high speed ADC architectures [3]. As CMOS technology continues to scale [4], [5], conventional ADC architectures experience Signal-to-Noise-Ratio (SNR) degradation due to supply voltage reduction. Timebased signals, however, exhibit an improvement in SNR due to the higher switching speeds [6]. Although VTC performance is still limited by reductions in supply voltage due to the ne-
978-1-4799-2452-3/13/$31.00 ©2013 IEEE
Fig. 1. Time-based ADC architecture [1].
cessity of processing an input analog voltage signal, the TDC is not affected by this issue and can be designed to take full advantage of the CMOS high switching speed. Accordingly, the main challenge in time-based ADC design is to produce a low power VTC circuit with good linearity characteristics. In addition, the VTC circuit performance should be insensitive to process and temperature variations. Several Voltage-to-Time Converter (VTC) circuits have been introduced in the literature [3], [7]–[10]. The core of most of these VTC circuits is based on the simple current starved inverter displayed in Figure 2 [3]. In this figure, the input voltage, Vin , controls the delay of the falling edge of the clock signal, Vclk , through the inverter (Transistors M2 and M3) by controlling the discharging current of transistor M1.
Fig. 2. Basic current starved inverter [3].
149
In [7], a basic current starved differential delay cell with
the addition of weak cross coupled inverters is proposed to reduce the transition times of the inverters used in [8]. A similar VTC is presented in [9] but a weak nMOS transistor with its gate tied to the supply voltage is added to ensure that the VTC operates at very low input voltages. In [2], a delay unit consisting of a series of inverters with the pMOS sources tied to the input voltage is introduced. Recently, A VTC circuit that makes use of all the above circuits with a new linearization scheme is proposed in [3], [10]. These previously published VTC circuits are not sufficiently linear and their voltage to time conversion sensitivity is not high enough to be used in high speed, low power, and high resolution time-based ADCs. In this paper, A new VTC circuit, based on the current starved inverter architecture, is proposed. The proposed circuit exhibits higher linearity and low power consumption compared to the previously published VTC circuits. The architecture of the proposed VTC circuit is based on the PWM method and achieves high insensitivity to process and temperature variations. The rest of the paper is organized as follows. In Section II, the circuit design and analysis is proposed. Simulation results and discussions are presented in Section III. Finally, some conclusions are drawn in Section IV. II. C IRCUIT D ESIGN AND A NALYSIS Figure 3 portrays the block diagram of the proposed VTC circuit. The analog input voltage, Vin , is applied to the two current starved circuits denoted by tRISE and tF ALL displayed in Figure 4. In the tRISE current starved circuit, the rise time of the inverter is controlled by Vin through transistor Pb2. Transistor Pb3 is a weak minimum size transistor used to allow an alternative current path when transistor Pb2 is OFF (i.e., when the values of Vin is close to the supply voltage, VDD ). Similarly, In the tF ALL current starved circuit, the fall time of the inverter is controlled by Vin through transistor Na2. Transistor Na1 is a weak minimum size transistor used to allow an alternative current path when transistor Na2 is OFF (i.e., when the values of Vin is less than transistor Na2 threshold voltage). The input clock, VCLK , is applied to the tF ALL current starved circuit and accordingly, the voltage V1 is an inverted version of the clock where only the falling delay is controlled by the input voltage Vin . On the other hand, the input clock is applied to an inverted delay line (i.e., odd number of CMOS inverters) and then applied to the tRISE current starved circuit. Accordingly, the voltage V2 is a delayed version of the input clock where the rising delay is controlled by Vin . The voltages V1 and V2 are applied as inputs to a CMOS XNOR gate that produces the pulse width modulated output voltage, VP W M . Figure 5 shows the timing diagram for a fixed value of Vin . The output voltage of the XNOR gate, VP W M , has two pulses. The first pulse width equals ∆ + tr − tf where ∆ is the inverter delay line timing delay, tr is the current starved inverter tRISE delay that is controlled by Vin , and tf is the current starved inverter tF ALL delay that is controlled by Vin . The second pulse exhibits a fixed pulse width of ∆ that is independent of Vin .
It should be noted that the timing delays tr and tf are inversely controlled by the input voltage Vin . In other words, as Vin value increases, tr increases, because the source-to-gate voltage of the pMOS transistor Pb2 (i.e., VDD -Vin ) decreases, whereas tf is reduced because the gate-to-source voltage of the nMOS transistor Na2 (i.e., Vin ) increases. This VTC circuit will be followed by a TDC circuit that converts the first pulse width, that is controlled by Vin , into a digital word and ignores the second pulse (i.e., the pulse of width ∆). The choice of ∆ is essential to have the first pulse width always larger than zero at all design corners. Correspondingly, the delay ∆ is given by. ∆ = min[(tf |max − tr |min ), 0] + Θ
(1)
Where tf |max is the maximum expected falling delay of the current starved inverter tF ALL , tr |min is the minimum expected rising delay of the current starved inverter tRISE , and Θ is a safety margin which is selected in this design to be the delay of one minimum-size CMOS inverter. The sizing of the tRISE current starved inverter transistors and the tF ALL current starved inverter transistors is chosen to achieve maximum voltage-to-time conversion sensitivity and minimum linearity error. Transistors Pb3 and Na1 are designed as minimum size transistors, transistors Pb2 and Na2 are larger than the minimum size transistors by a factor of 2.5X, transistors Nb1 and Na3 are designed larger than the minimum size by a factor of 10X, and transistors Pb1 and Pa1 are designed larger than the minimum size by a factor of 20X.
Fig. 3. Block diagram of the proposed VTC circuit.
III. S IMULATION R ESULTS AND D ISCUSSIONS A. Voltage Sensitivity and Linearity The voltage sensitivity and linearity of the proposed VTC circuit were simulated by sweeping the DC input voltage, Vin , of the VTC and measuring the output voltage, VP W M , pulse width. These measurements are performed by using transient analysis with industrial hardware-calibrated CMOS 65nm transistor device models, provided by TSMC. Figures
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(a)
(b)
Fig. 4. (a) The tRISE current starved inverter circuit and (b) the tF ALL current starved inverter circuit.
(a)
(b) Fig. 6. The VTC circuit output voltage waveform, VP W M , when (a) Vin = 0.2V and (b) Vin = 0.35V.
Fig. 5. Timing diagram for the proposed VTC circuit for a fixed value of Vin .
6.a and 6.b shows the output voltage waveform when Vin = 0.2V and when Vin = 0.35V, respectively. It is obvious from this figure that the waveform first pulse width is controlled by the change in the input analog voltage, Vin , whereas the second pulse width is constant as claimed in Figure 5. Figure 7 displays the current starved inverter tRISE rising delay, tr , the current starved inverter tF ALL falling delay, tf , and the first pulse width, tP W M , versus the input analog voltage Vin that changes from 0.2V to 0.35V providing a dynamic input voltage range of 150mV. Outside this dynamic range the linearity error is larger than 1%. The sensitivity of this VTC circuit, defined as the slope of the tP W M -Vin curve, denoted by ρ = 3.47 psec/mV. According to Figure 7, the difference between the starved inverter tRISE rising delay, tr , and the starved inverter tF ALL , tf , allows the proposed circuit to provide higher linearity and larger sensitivity because tr and tf are inversely controlled by Vin . B. Maximum Input Frequency If the VTC is used without a sample-and-hold at the input voltage, the maximum input frequency that can be used without having a significant error due to the input signal change during the VTC delay time is an important consideration. The
Fig. 7. The current starved inverter tRISE rising delay, tr , the current starved inverter tF ALL falling delay, tf , and the first pulse width of VP W M , tP W M , versus the input analog voltage Vin
maximum input frequency of the VTC was measured by using sinusoidal input signals at multiples of the clock frequency (i.e., (4/3)*fCLK , 2*fCLK , and 4*fCLK ) as performed in [3]. This allowed the delay at sampling instants where the input signal was at a minimum, and at a maximum, and where the input signal was at its maximum rate of change to be measured [3]. The simulated results are shown in Figure 8 where the delay error is plotted versus the input frequency at the three different sampling instants. The error was calculated as the difference in the output pulse width of the VTC compared to the output pulse width with DC input voltage equal to the sinusoidal input voltage at the sampling instant. The maximum tolerable error due to an input signal changing rapidly during the time when that signal is effectively being sampled is equal to one Least Significant
151
Bit (LSB) of the ADC resolution. For example, for 6 bit ADC resolution with an input dynamic range of 150mV and a sensitivity of 3.46 ps/mV, one LSB corresponds to 2.34mV (=150mV / 26 ) or a 8.1ps (=2.34mV * 3.46psec/mV) pulse width, so the maximum tolerable VTC sampling error is 8.1ps. Several lines indicating the maximum delay error for 5 bit, 6 bit, 7 bit, and 8 bit ADC resolutions are shown in Figure 8.
Fig. 8. Simulated VTC pulse width error versus the input frequency at maximum peak, zero crossing, and minimum peak sampling instants of the input sinusoidal signal
From Figure 8, it is obvious that a 6 bit resolution ADC can be used with an input frequency up to 2.4GHz without the utilization of the sample and hold circuit. If the input frequency is higher than 2.4GHz, a sample and hold circuit must be used. In addition, for an input frequency higher than 5 GHz is to be applied, the ADC resolution is limited to 4 bit unless a sample and hold circuit is adopted. The input frequencies considered here are higher than half the maximum clock frequency of (500MHz/2) so time interleaving of several VTC’s in parallel could be used to avoid sub-sampling the input frequencies (time interleaving is a technique commonly used in flash ADC’s to increase the effective sampling frequency [3], [11]).
hold circuit for analog input frequencies up to 4 GHz. If higher input frequencies are expected, a sample and hold circuit must be used. R EFERENCES [1] A. R. Macpherson, K. A. Townsend, and J. W. Haslett, ”A 5GS/s Voltageto-Time Converter in 90nm CMOS,” Proceedings of the 4th European Microwave Integrated Circuits Conference (EuMIC’09), pp. 254–257, 2009. [2] T. Watanabe, T. Mizuno, and Y. Makino, ”An all-digital analog-to-digital converter with 12 -,uv LSB using moving-average filtering,” IEEE Journal of Solid State Circuits, vol. 38, no. 1, pp. 120–125, Jan. 2003. [3] H. Pekau, A. Yousif, and J. W. Haslett, ”A CMOS Integrated Linear Voltage-to-Pulse-Delay-Time Converter for time-based Analog-to-Digital Converters,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’06), pp. 2373–2376, 2006. [4] Hassan Mostafa, Mohab Anis, and Mohamed Elmasry, ”A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Dieto-Die and Within-Die Variations Compensation,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 10, pp. 18481860, October 2011. [5] Hassan Mostafa, Mohab Anis, and Mohamed Elmasry, ”Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells, ” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 2, pp. 182-195, February 2011. [6] R.B. Staszewski, K. Muhammad, D. Leipold et. al, All-Digital Tx Frequency Synthesizer And Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 22782291, Dec. 2004. [7] A. Djemouai, M. Sawan, and M. Slamani, ”New 200 MHz Frequency Using Notch Filtering at the VTC Input or by Using Switches Locked Loop Based on New Frequency-To-Voltage Converters Approach,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’99), pp. 89–92, 1999. [8] A. Djemouai, M. Sawan, and M. Slamani, ”New CMOS Integrated Pulse Width Modulator for Voltage Conversion Applications,” Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS’00), pp. 116–119, 2000. [9] P. Dudek and S. Szczepanski, ””A High Resolution CMOS Time-toDigital Converter Using a Vernier Delay Line,” IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 240–247, Feb. 2000. [10] A. R. Macpherson, K. A. Townsend, and J. W. Haslett, A 5GS/s Voltage-to-Time Converter in 90nm CMOS, Proceedings of the European Microwave Integrated Circuits Conference, pp. 254257, 2009. [11] A. A. K. El-Sankary and M. Sawan, ”New Sampling Method to Improve the SFDR of Time-Interleaved ADC’s,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’03), pp. 833836, 2003.
IV. ACKNOWLEDGEMENT This research was partially funded by Zewail City of Science and Technology, AUC, the STDF, Intel, Mentor Graphics, MCIT and the Natural Sciences and Engineering Research Council of Canada (NSERC). V. C ONCLUSION In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. The proposed VTC circuit provides a pulse width which is proportional to the analog input voltage. This pulse width is calculated as the difference between the rising delay and the falling delay of two current starved inverters. These two delays are both controlled by the analog input voltage inversely. This diffference techniques allows the new VTC circuit to have higher dynamic range and higher linearity than any of the basic current starved inverters alone. The new VTC circuit can be used in a 5 bit time-based ADC with no sample and
152
1,2
Abstract—Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-toTime Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-to-Digital Converter (TDC) circuit. In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. This new VTC circuit can be used in a 5 bit time-based ADC with no sample and hold circuit for analog input frequencies up to 4 GHz. Index Terms—Nanometer CMOS technology, voltage-to-time converter, time-based analog-to-digital converter, software radio receivers.
I. I NTRODUCTION A software radio receiver is one of the most important emerging technologies for future wireless Ultra Wide Band (UWB) communication services. In this receiver, the received noisy RF analog signal is directly applied to a wide-band Analog-to-Digital Converter (ADC), followed by the real time Digital Signal Processor (DSP). The high demand for highspeed low-power ADCs for software radio receivers has led to the design of time-based ADCs. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using a Time-toDigital Converter (TDC) circuit as portrayed in Figure 1 [1]. The VTC is also referred to as either a Pulse Position Modulator (PPM) or Pulse Width Modulator (PWM), depending on whether the delay is applied to one or both edges of the input clock pulses. The TDC circuit consists of digital logic and counter circuits [2]. The time-based ADC can operate at very high clock and input frequencies while consuming less power and die area compared to other conventional high speed ADC architectures [3]. As CMOS technology continues to scale [4], [5], conventional ADC architectures experience Signal-to-Noise-Ratio (SNR) degradation due to supply voltage reduction. Timebased signals, however, exhibit an improvement in SNR due to the higher switching speeds [6]. Although VTC performance is still limited by reductions in supply voltage due to the ne-
978-1-4799-2452-3/13/$31.00 ©2013 IEEE
Fig. 1. Time-based ADC architecture [1].
cessity of processing an input analog voltage signal, the TDC is not affected by this issue and can be designed to take full advantage of the CMOS high switching speed. Accordingly, the main challenge in time-based ADC design is to produce a low power VTC circuit with good linearity characteristics. In addition, the VTC circuit performance should be insensitive to process and temperature variations. Several Voltage-to-Time Converter (VTC) circuits have been introduced in the literature [3], [7]–[10]. The core of most of these VTC circuits is based on the simple current starved inverter displayed in Figure 2 [3]. In this figure, the input voltage, Vin , controls the delay of the falling edge of the clock signal, Vclk , through the inverter (Transistors M2 and M3) by controlling the discharging current of transistor M1.
Fig. 2. Basic current starved inverter [3].
149
In [7], a basic current starved differential delay cell with
the addition of weak cross coupled inverters is proposed to reduce the transition times of the inverters used in [8]. A similar VTC is presented in [9] but a weak nMOS transistor with its gate tied to the supply voltage is added to ensure that the VTC operates at very low input voltages. In [2], a delay unit consisting of a series of inverters with the pMOS sources tied to the input voltage is introduced. Recently, A VTC circuit that makes use of all the above circuits with a new linearization scheme is proposed in [3], [10]. These previously published VTC circuits are not sufficiently linear and their voltage to time conversion sensitivity is not high enough to be used in high speed, low power, and high resolution time-based ADCs. In this paper, A new VTC circuit, based on the current starved inverter architecture, is proposed. The proposed circuit exhibits higher linearity and low power consumption compared to the previously published VTC circuits. The architecture of the proposed VTC circuit is based on the PWM method and achieves high insensitivity to process and temperature variations. The rest of the paper is organized as follows. In Section II, the circuit design and analysis is proposed. Simulation results and discussions are presented in Section III. Finally, some conclusions are drawn in Section IV. II. C IRCUIT D ESIGN AND A NALYSIS Figure 3 portrays the block diagram of the proposed VTC circuit. The analog input voltage, Vin , is applied to the two current starved circuits denoted by tRISE and tF ALL displayed in Figure 4. In the tRISE current starved circuit, the rise time of the inverter is controlled by Vin through transistor Pb2. Transistor Pb3 is a weak minimum size transistor used to allow an alternative current path when transistor Pb2 is OFF (i.e., when the values of Vin is close to the supply voltage, VDD ). Similarly, In the tF ALL current starved circuit, the fall time of the inverter is controlled by Vin through transistor Na2. Transistor Na1 is a weak minimum size transistor used to allow an alternative current path when transistor Na2 is OFF (i.e., when the values of Vin is less than transistor Na2 threshold voltage). The input clock, VCLK , is applied to the tF ALL current starved circuit and accordingly, the voltage V1 is an inverted version of the clock where only the falling delay is controlled by the input voltage Vin . On the other hand, the input clock is applied to an inverted delay line (i.e., odd number of CMOS inverters) and then applied to the tRISE current starved circuit. Accordingly, the voltage V2 is a delayed version of the input clock where the rising delay is controlled by Vin . The voltages V1 and V2 are applied as inputs to a CMOS XNOR gate that produces the pulse width modulated output voltage, VP W M . Figure 5 shows the timing diagram for a fixed value of Vin . The output voltage of the XNOR gate, VP W M , has two pulses. The first pulse width equals ∆ + tr − tf where ∆ is the inverter delay line timing delay, tr is the current starved inverter tRISE delay that is controlled by Vin , and tf is the current starved inverter tF ALL delay that is controlled by Vin . The second pulse exhibits a fixed pulse width of ∆ that is independent of Vin .
It should be noted that the timing delays tr and tf are inversely controlled by the input voltage Vin . In other words, as Vin value increases, tr increases, because the source-to-gate voltage of the pMOS transistor Pb2 (i.e., VDD -Vin ) decreases, whereas tf is reduced because the gate-to-source voltage of the nMOS transistor Na2 (i.e., Vin ) increases. This VTC circuit will be followed by a TDC circuit that converts the first pulse width, that is controlled by Vin , into a digital word and ignores the second pulse (i.e., the pulse of width ∆). The choice of ∆ is essential to have the first pulse width always larger than zero at all design corners. Correspondingly, the delay ∆ is given by. ∆ = min[(tf |max − tr |min ), 0] + Θ
(1)
Where tf |max is the maximum expected falling delay of the current starved inverter tF ALL , tr |min is the minimum expected rising delay of the current starved inverter tRISE , and Θ is a safety margin which is selected in this design to be the delay of one minimum-size CMOS inverter. The sizing of the tRISE current starved inverter transistors and the tF ALL current starved inverter transistors is chosen to achieve maximum voltage-to-time conversion sensitivity and minimum linearity error. Transistors Pb3 and Na1 are designed as minimum size transistors, transistors Pb2 and Na2 are larger than the minimum size transistors by a factor of 2.5X, transistors Nb1 and Na3 are designed larger than the minimum size by a factor of 10X, and transistors Pb1 and Pa1 are designed larger than the minimum size by a factor of 20X.
Fig. 3. Block diagram of the proposed VTC circuit.
III. S IMULATION R ESULTS AND D ISCUSSIONS A. Voltage Sensitivity and Linearity The voltage sensitivity and linearity of the proposed VTC circuit were simulated by sweeping the DC input voltage, Vin , of the VTC and measuring the output voltage, VP W M , pulse width. These measurements are performed by using transient analysis with industrial hardware-calibrated CMOS 65nm transistor device models, provided by TSMC. Figures
150
(a)
(b)
Fig. 4. (a) The tRISE current starved inverter circuit and (b) the tF ALL current starved inverter circuit.
(a)
(b) Fig. 6. The VTC circuit output voltage waveform, VP W M , when (a) Vin = 0.2V and (b) Vin = 0.35V.
Fig. 5. Timing diagram for the proposed VTC circuit for a fixed value of Vin .
6.a and 6.b shows the output voltage waveform when Vin = 0.2V and when Vin = 0.35V, respectively. It is obvious from this figure that the waveform first pulse width is controlled by the change in the input analog voltage, Vin , whereas the second pulse width is constant as claimed in Figure 5. Figure 7 displays the current starved inverter tRISE rising delay, tr , the current starved inverter tF ALL falling delay, tf , and the first pulse width, tP W M , versus the input analog voltage Vin that changes from 0.2V to 0.35V providing a dynamic input voltage range of 150mV. Outside this dynamic range the linearity error is larger than 1%. The sensitivity of this VTC circuit, defined as the slope of the tP W M -Vin curve, denoted by ρ = 3.47 psec/mV. According to Figure 7, the difference between the starved inverter tRISE rising delay, tr , and the starved inverter tF ALL , tf , allows the proposed circuit to provide higher linearity and larger sensitivity because tr and tf are inversely controlled by Vin . B. Maximum Input Frequency If the VTC is used without a sample-and-hold at the input voltage, the maximum input frequency that can be used without having a significant error due to the input signal change during the VTC delay time is an important consideration. The
Fig. 7. The current starved inverter tRISE rising delay, tr , the current starved inverter tF ALL falling delay, tf , and the first pulse width of VP W M , tP W M , versus the input analog voltage Vin
maximum input frequency of the VTC was measured by using sinusoidal input signals at multiples of the clock frequency (i.e., (4/3)*fCLK , 2*fCLK , and 4*fCLK ) as performed in [3]. This allowed the delay at sampling instants where the input signal was at a minimum, and at a maximum, and where the input signal was at its maximum rate of change to be measured [3]. The simulated results are shown in Figure 8 where the delay error is plotted versus the input frequency at the three different sampling instants. The error was calculated as the difference in the output pulse width of the VTC compared to the output pulse width with DC input voltage equal to the sinusoidal input voltage at the sampling instant. The maximum tolerable error due to an input signal changing rapidly during the time when that signal is effectively being sampled is equal to one Least Significant
151
Bit (LSB) of the ADC resolution. For example, for 6 bit ADC resolution with an input dynamic range of 150mV and a sensitivity of 3.46 ps/mV, one LSB corresponds to 2.34mV (=150mV / 26 ) or a 8.1ps (=2.34mV * 3.46psec/mV) pulse width, so the maximum tolerable VTC sampling error is 8.1ps. Several lines indicating the maximum delay error for 5 bit, 6 bit, 7 bit, and 8 bit ADC resolutions are shown in Figure 8.
Fig. 8. Simulated VTC pulse width error versus the input frequency at maximum peak, zero crossing, and minimum peak sampling instants of the input sinusoidal signal
From Figure 8, it is obvious that a 6 bit resolution ADC can be used with an input frequency up to 2.4GHz without the utilization of the sample and hold circuit. If the input frequency is higher than 2.4GHz, a sample and hold circuit must be used. In addition, for an input frequency higher than 5 GHz is to be applied, the ADC resolution is limited to 4 bit unless a sample and hold circuit is adopted. The input frequencies considered here are higher than half the maximum clock frequency of (500MHz/2) so time interleaving of several VTC’s in parallel could be used to avoid sub-sampling the input frequencies (time interleaving is a technique commonly used in flash ADC’s to increase the effective sampling frequency [3], [11]).
hold circuit for analog input frequencies up to 4 GHz. If higher input frequencies are expected, a sample and hold circuit must be used. R EFERENCES [1] A. R. Macpherson, K. A. Townsend, and J. W. Haslett, ”A 5GS/s Voltageto-Time Converter in 90nm CMOS,” Proceedings of the 4th European Microwave Integrated Circuits Conference (EuMIC’09), pp. 254–257, 2009. [2] T. Watanabe, T. Mizuno, and Y. Makino, ”An all-digital analog-to-digital converter with 12 -,uv LSB using moving-average filtering,” IEEE Journal of Solid State Circuits, vol. 38, no. 1, pp. 120–125, Jan. 2003. [3] H. Pekau, A. Yousif, and J. W. Haslett, ”A CMOS Integrated Linear Voltage-to-Pulse-Delay-Time Converter for time-based Analog-to-Digital Converters,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’06), pp. 2373–2376, 2006. [4] Hassan Mostafa, Mohab Anis, and Mohamed Elmasry, ”A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Dieto-Die and Within-Die Variations Compensation,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 10, pp. 18481860, October 2011. [5] Hassan Mostafa, Mohab Anis, and Mohamed Elmasry, ”Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells, ” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 2, pp. 182-195, February 2011. [6] R.B. Staszewski, K. Muhammad, D. Leipold et. al, All-Digital Tx Frequency Synthesizer And Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 22782291, Dec. 2004. [7] A. Djemouai, M. Sawan, and M. Slamani, ”New 200 MHz Frequency Using Notch Filtering at the VTC Input or by Using Switches Locked Loop Based on New Frequency-To-Voltage Converters Approach,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’99), pp. 89–92, 1999. [8] A. Djemouai, M. Sawan, and M. Slamani, ”New CMOS Integrated Pulse Width Modulator for Voltage Conversion Applications,” Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS’00), pp. 116–119, 2000. [9] P. Dudek and S. Szczepanski, ””A High Resolution CMOS Time-toDigital Converter Using a Vernier Delay Line,” IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 240–247, Feb. 2000. [10] A. R. Macpherson, K. A. Townsend, and J. W. Haslett, A 5GS/s Voltage-to-Time Converter in 90nm CMOS, Proceedings of the European Microwave Integrated Circuits Conference, pp. 254257, 2009. [11] A. A. K. El-Sankary and M. Sawan, ”New Sampling Method to Improve the SFDR of Time-Interleaved ADC’s,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’03), pp. 833836, 2003.
IV. ACKNOWLEDGEMENT This research was partially funded by Zewail City of Science and Technology, AUC, the STDF, Intel, Mentor Graphics, MCIT and the Natural Sciences and Engineering Research Council of Canada (NSERC). V. C ONCLUSION In this paper, a novel VTC circuit is proposed which achieves high linearity and large dynamic analog input range. The proposed VTC circuit provides a pulse width which is proportional to the analog input voltage. This pulse width is calculated as the difference between the rising delay and the falling delay of two current starved inverters. These two delays are both controlled by the analog input voltage inversely. This diffference techniques allows the new VTC circuit to have higher dynamic range and higher linearity than any of the basic current starved inverters alone. The new VTC circuit can be used in a 5 bit time-based ADC with no sample and
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