Engineering and Technology Degree Level: Ph.D Abstract ID# 718
Graduate Category: Engineering and Technology Degree Level: Ph.D Abstract ID# 718
A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Faculty Advisor: Marvin Onabajo and Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
Calibration System and CUT I. Tunable LNA for Low Power Application
PE1
Lg2
Cd
Ld
Cgd2_ext
Subthreshold LNA with inductive source degeneration
Rd
vout
VBIAS
S3
M2 Lg vin
Digitally tunable for linearity enhancement (IM3)
Cgd2_ext3
RBIAS
Cgd2_ext2
Cgs1_ext
S1 Cgd2_ext1 Cgd2_ext0
- Cgd2_ext0 (fixed capacitor) = 90fF - Cgd2_ext1 = 20fF
Reduced radix-4 DIF FFT
II. Envelope Detector and Cascode RF Amplifier Nonlinearity effects on envelope detector and RF amplifier? Calibration is conducted with the same envelope detector and RF amplifier nonlinearity
Advantage RBIAS
Low cost and accurate high frequency signal analysis
vin
Q1
for on-chip testing and calibration
vout IBIAS
vin
•
Two-tone Input
•
Envelope Detector:
Vertical bipolar (NPN) transistors in a standard
CLoad
CMOS technology
Why using cascode common source amplifier?
Registers
Data Signal Control Signal
IM3 Calculator
Frequency down-conversion •
Digital Calibration Unit
M2
NF [dB]
IM3 [dBc]
000
-29.5
12.9
4.42
33.33
001
-26.1
12.9
4.41
32.57
010
-23.9
12.8
4.39
31.89
011
-22.2
12.6
4.39
31.21
100
-28.2
11.7
4.53
35.57
101
-32.9
12.2
4.53
35.49
110
-39.8
12.4
4.50
34.70
111
-37.5
12.7
4.50
34.11
Enhance linearity characteristics
III. IM3 Components Estimation y(t) CUT
IM3 component estimation
Envelope Detector
r(t)
𝑟 𝑡 = 2 ∙ 𝐵1 ∙ 𝑠𝑖𝑛
Conclusion
𝜔𝑏 𝑡 3𝜔𝑏 𝑡 + 2 ∙ 𝐵2 ∙ 𝑠𝑖𝑛 2 2
8 𝐵1 −1 𝑘+1 3𝐵2 −1 𝑘 𝑏𝑘 = + 𝜋 4𝑘 2 − 1 4𝑘 2 − 9
CUT output signal components (B1, B2) can be expressed as a linear combination of harmonic components (b1, b2, b3, …)
𝐴𝑡 𝑟 𝑡 , 𝜔𝑏 = 500kHz
IV. Sampling Frequency Determination How to minimize the size of FFT engine? Minimize leakage for high accuracy Coherent sampling method
Δ𝑓 ∙ 𝑁𝐹𝐹𝑇 𝑓𝑠 = 𝑀𝑐𝑦𝑐𝑙𝑒
IM3 during two-tone testing. No significant performance variations on s11, gain and NF, while tuning the linearity. High tolerance against process variations, reduced manufacturing test costs, and
Frequency down−conversion!
Two-tone test with an envelope detector
• • • •
On-chip closed-loop built-in calibration for linearity optimization by estimating the
product lifetime extension through periodic calibrations.
𝐴𝑡 𝑦 𝑡 , 𝜔0 = 2.4GHz
Minimize area and power overhead
Product lifetime extension
S21 [dB]
devices (12.8dB gain)
Feature
Manufacturing test cost reduction
S11 [dB]
vBIAS1
x(t)
High tolerance against process variations
Code [S3S2S1]
Monte Carlo Simulation for Process Variations
Compensate low current gain (β = 8) on vertical NPN
Ls
Digital Calibration Unit:
On-chip calibration for LNA linearity (IM3) optimization
Simulated Performance of the 2.4GHz Subthreshold LNA (0.13μm CMOS, 1.2V SUPPLY)
CUT is low power application LNA
M1
(down-converter)
Controller
Simulation Results
conditions as the LNA settings are changed to determine the optimum output IM3.
vBIAS2
FFT
Base on 512-point FFT engine Optimize hardware for BIC application Single delay feedback (SDF) facility – advantage on hardware trading off throughput 5 clock cycles latency 4.31mm2 (Conventional) → 0.51mm2 (Optimized) 68.3mW → 5.0mW @ 51.2MHz RAM utilization can achieve power and area reduction
Digital hardware implementation with Verilog-HDL Synthesized using standard 0.13μm CMOS process technology
- Cgd2_ext2 = 40fF - Cgd2_ext3 = 80fF
vout
ADC
Radix-2 DIF FFT signal flow graph of length 16
Digital Calibration Unit Layout
Ls
RL
LNA
IM3 Calculator
Minor effects on other performance (S11, S21 and NF)
S2
M1
Registor
Low power application (Input power: -25 ~ -40dBm)
vBIAS3
Envelope Detector
PE4
Feature
Linearity and dynamic range: BJT > NMOS or diode
Output
PE3
Controller
LNA Calibration Architecture
Input
PE2
190µm
A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a twotone test with 1MHz tone spacing, a 512-point FFT engine, a 10bit analog-to-digital converter (ADC) model, and digital blocks operating with a 51.2MHz clock frequency. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed at transient simulations. The RF/analog and digital blocks were implemented using a standard 0.13μm CMOS technology.
Digital Hardware Implementation
𝑓𝑠 − Sampling frequency Δ𝑓 − Test tone spacing 𝑁𝐹𝐹𝑇 − Size of FFT engine 𝑀𝑐𝑦𝑐𝑙𝑒 − Prime number of cycles in the sample set
References [1] Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim “A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA,” 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Oct 1-3, Amsterdam, Netherlands, pp. 221-226 [2] H. Chauhan, Y. Choi, M. Onabajo, I.-S. Jung, and Y.-B. Kim, “Accurate and efficient on-chip spectral analysis for built-in testing and calibration approaches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 497–506, Mar. 2014
A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Faculty Advisor: Marvin Onabajo and Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
Calibration System and CUT I. Tunable LNA for Low Power Application
PE1
Lg2
Cd
Ld
Cgd2_ext
Subthreshold LNA with inductive source degeneration
Rd
vout
VBIAS
S3
M2 Lg vin
Digitally tunable for linearity enhancement (IM3)
Cgd2_ext3
RBIAS
Cgd2_ext2
Cgs1_ext
S1 Cgd2_ext1 Cgd2_ext0
- Cgd2_ext0 (fixed capacitor) = 90fF - Cgd2_ext1 = 20fF
Reduced radix-4 DIF FFT
II. Envelope Detector and Cascode RF Amplifier Nonlinearity effects on envelope detector and RF amplifier? Calibration is conducted with the same envelope detector and RF amplifier nonlinearity
Advantage RBIAS
Low cost and accurate high frequency signal analysis
vin
Q1
for on-chip testing and calibration
vout IBIAS
vin
•
Two-tone Input
•
Envelope Detector:
Vertical bipolar (NPN) transistors in a standard
CLoad
CMOS technology
Why using cascode common source amplifier?
Registers
Data Signal Control Signal
IM3 Calculator
Frequency down-conversion •
Digital Calibration Unit
M2
NF [dB]
IM3 [dBc]
000
-29.5
12.9
4.42
33.33
001
-26.1
12.9
4.41
32.57
010
-23.9
12.8
4.39
31.89
011
-22.2
12.6
4.39
31.21
100
-28.2
11.7
4.53
35.57
101
-32.9
12.2
4.53
35.49
110
-39.8
12.4
4.50
34.70
111
-37.5
12.7
4.50
34.11
Enhance linearity characteristics
III. IM3 Components Estimation y(t) CUT
IM3 component estimation
Envelope Detector
r(t)
𝑟 𝑡 = 2 ∙ 𝐵1 ∙ 𝑠𝑖𝑛
Conclusion
𝜔𝑏 𝑡 3𝜔𝑏 𝑡 + 2 ∙ 𝐵2 ∙ 𝑠𝑖𝑛 2 2
8 𝐵1 −1 𝑘+1 3𝐵2 −1 𝑘 𝑏𝑘 = + 𝜋 4𝑘 2 − 1 4𝑘 2 − 9
CUT output signal components (B1, B2) can be expressed as a linear combination of harmonic components (b1, b2, b3, …)
𝐴𝑡 𝑟 𝑡 , 𝜔𝑏 = 500kHz
IV. Sampling Frequency Determination How to minimize the size of FFT engine? Minimize leakage for high accuracy Coherent sampling method
Δ𝑓 ∙ 𝑁𝐹𝐹𝑇 𝑓𝑠 = 𝑀𝑐𝑦𝑐𝑙𝑒
IM3 during two-tone testing. No significant performance variations on s11, gain and NF, while tuning the linearity. High tolerance against process variations, reduced manufacturing test costs, and
Frequency down−conversion!
Two-tone test with an envelope detector
• • • •
On-chip closed-loop built-in calibration for linearity optimization by estimating the
product lifetime extension through periodic calibrations.
𝐴𝑡 𝑦 𝑡 , 𝜔0 = 2.4GHz
Minimize area and power overhead
Product lifetime extension
S21 [dB]
devices (12.8dB gain)
Feature
Manufacturing test cost reduction
S11 [dB]
vBIAS1
x(t)
High tolerance against process variations
Code [S3S2S1]
Monte Carlo Simulation for Process Variations
Compensate low current gain (β = 8) on vertical NPN
Ls
Digital Calibration Unit:
On-chip calibration for LNA linearity (IM3) optimization
Simulated Performance of the 2.4GHz Subthreshold LNA (0.13μm CMOS, 1.2V SUPPLY)
CUT is low power application LNA
M1
(down-converter)
Controller
Simulation Results
conditions as the LNA settings are changed to determine the optimum output IM3.
vBIAS2
FFT
Base on 512-point FFT engine Optimize hardware for BIC application Single delay feedback (SDF) facility – advantage on hardware trading off throughput 5 clock cycles latency 4.31mm2 (Conventional) → 0.51mm2 (Optimized) 68.3mW → 5.0mW @ 51.2MHz RAM utilization can achieve power and area reduction
Digital hardware implementation with Verilog-HDL Synthesized using standard 0.13μm CMOS process technology
- Cgd2_ext2 = 40fF - Cgd2_ext3 = 80fF
vout
ADC
Radix-2 DIF FFT signal flow graph of length 16
Digital Calibration Unit Layout
Ls
RL
LNA
IM3 Calculator
Minor effects on other performance (S11, S21 and NF)
S2
M1
Registor
Low power application (Input power: -25 ~ -40dBm)
vBIAS3
Envelope Detector
PE4
Feature
Linearity and dynamic range: BJT > NMOS or diode
Output
PE3
Controller
LNA Calibration Architecture
Input
PE2
190µm
A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a twotone test with 1MHz tone spacing, a 512-point FFT engine, a 10bit analog-to-digital converter (ADC) model, and digital blocks operating with a 51.2MHz clock frequency. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed at transient simulations. The RF/analog and digital blocks were implemented using a standard 0.13μm CMOS technology.
Digital Hardware Implementation
𝑓𝑠 − Sampling frequency Δ𝑓 − Test tone spacing 𝑁𝐹𝐹𝑇 − Size of FFT engine 𝑀𝑐𝑦𝑐𝑙𝑒 − Prime number of cycles in the sample set
References [1] Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim “A Built-In Calibration System with A Reduced FFT Engine for Linearity Optimization of Low Power LNA,” 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Oct 1-3, Amsterdam, Netherlands, pp. 221-226 [2] H. Chauhan, Y. Choi, M. Onabajo, I.-S. Jung, and Y.-B. Kim, “Accurate and efficient on-chip spectral analysis for built-in testing and calibration approaches,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 497–506, Mar. 2014
