Flex-Pass-Gate SRAM Design for Static Noise ... - Semantic Scholar
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology S. O’uchi, M. Masahara, K. Sakamoto, K. Endo, Y.X. Liu, T. Matsukawa, T. Sekigawa, H. Koike and E. Suzuki National Institute of AIST
Outline • Background • Proposal of Flex-Pass-Gate SRAM – Memory cell – Operation in array
• Performance Estimation for hp-32-nm LSTP Applications – Pass gate design strategy – Static noise margin estimation – Variability tolerance
• Conclusion
Background –SRAM Yield Design Margin
WL BL
WM
BLB
Vth Variation Vth,PG
Vth,PG
Conventional 6Tr-SRAM
Increased Variation WM
V2
V2
Trade Off
RM
RM Vth,PG V1
Read Margin, RM
V1
Write Margin, WM
Malfunctions!
Flex-Pass-Gate SRAM Conventional WL
WM
BL
BLB
RM Vth,PG
Fixed Vth,PG Vth,PG for Write Vth-Ctrl
Vth,PG for Read
Vth-Ctrl
WM D
D Gate S
Gate1
S
Gate2
RM Vth,PG
3T-FinFET
4T-FinFET
Flex-PG
3-Terminal and 4-Terminal FinFETs D Gate
VD
S
Gate Separation
D
VD
G1
S
G2
VG1
VG
10-6
10-7 10-8 10-9
Tsi=8.5nm Tox=1.7nm Lg=160nm
10-10 10-11 10-12 -1
-0.5
0 0.5 VG1(V)
1
ID (A/ μm)
ID (A/ μm)
10-6
VD=0.05V
10-7 10-8
.2V
10-5
G2 =1
10-4
VD=0.05V
10-9
10-10
V
10-5
4T-FinFET
V
10-4
VS
VS
G2 =0 V
3T-FinFET
VG2
10-11 10-12 -1
-0.5
0 0.5 VG1(V)
Tsi=8.5nm Tox=1.7nm Lg=160nm 1
+0.2V-step VG2 Increment
Y-X Liu et al. , 2003IEDM, 2004EDL (AIST)
RM and WM Enhancement • Using Dynamic VG2 Control VG2
VG2
VG2,R
VG2,W 0.40
Lowering VG2
Raising VG2 1.0
V2 (V)
1.0
V2 (V)
RM
V2 BLB
0.5
0.15
WM
VG2=1.0 -0.5
0
0.5
1.0
VG2 (V) -0.15
VG2=-0.5
0.0 0.0
0.5
0.30
Margin (V)
BL V1
0.5
V1 (V)
RM
1.0
0.0 0.0
0.5
V1 (V)
WM
1.0
Margins vs. VG2
Cell Layout and Area Overhead PG(４T-FinFET) 8F
Selective Gate Separation Contact of Vth-Ctrl Line
120F2
15F
VSS
VthVthBL Ctrl VDD Ctrl BLB VSS
3rd Layer (Vth-Ctrl, VDD, VSS, BL) 2rd Layer (WL) 1st Layer (Intra-Cell, not shown)
WL
3 Metal Layers Enough for Interconnection
Selective Gate Separation Gate1
Etching Stopper Fin
Fin Top P.R. Source
Drain
Gate BOX sub
Gate2
100nm
Side Wall
Top View
G1 HFin=100nm
DG Separation by Etching-Back Process
G2 ＴFin=25nm
100nm
Cross-Sectional View
K. Endo et al., 2007 IEEE EDL (AIST)
Array Configuration • Column-by-Column VG2 Control Column Address Column Peripheral
Row Peripheral
Row Address
WE
MC
MC
MC
MC
WLs
WL BL
Vth-Ctrl
Vth-Ctrl
BLs
BLs
Vth-Ctrl
Memory Cell
BLB Vth-Ctrl
Read Operation • Stable Read PG: On, High Vth Column Peripheral
WL
Row Peripheral
BL
R
R
Hld
Hld
L
L
H L
Vth-Ctrl
BLB Vth-Ctrl
Write Operation • Fast/Stable Write
PG: On, Low Vth WL
Column Peripheral BLB
Row Peripheral
BL
R Hld
W
H
Hld
L
Vth-Ctrl
Vth-Ctrl
PG: Off, Low Vth WL BL
L
H L
Vth-Ctrl
PG-Leakage Current Reduction 1. Negative Low-Level on WL 2. Thicker Second-Gate Oxide
BLB Vth-Ctrl
Performance Estimation Model • Technology assumption: hp-32-nm LSTP LG = 20 nm Gate1
tox1 = 1.2 nm
Drain
Source
tox2: Variable Gate2 10-nm G-S/D Underlap + S/D Doping Profile (σ = 3 nm)
Device Model
Drain Current (μA/μm)
10
4
10
|VDD| = 0.05, 1.0 V
10 3
4
10 3
10 0
10 0
PMOS
NMOS 10-3
10-3
tox1 = tox2 10-6
10-6 -1.00
-0.50
0.00
0.50
Gate Voltage (V)
Simulated ID-VG of 3T-FinFET
1.00
PG Design for Write Margin VG1,RW = 1.0 V
500
Write Margin (mV)
D: tox2 = 7.0 tox1 400
VDD=1.0 V
C: tox2 = 4.0 tox1 B: tox2 = 2.5 tox1
300
A: tox2 = tox1
0.0 V
200
100
0 0.00
Ticker tox2 0.50
1.00
VG2,W
Larger VG2,W 1.50
Second Gate Voltage for Write, VG2,W (V)
tox2
1.0 V
103
Write Condition A: tox2 = tox1, VG2,W = 0.70 V B: tox2 = 2.5tox1, VG2,W = 0.85 V C: tox2 = 4.0tox1 , VG2,W = 1.00 V D: tox2 = 7.0tox1 , VG2,W = 1.25 V
Hld
Hld
Hld
R
W
R
VWL,L VWL,H VWL,L
500 Hld
Hld
Hld
VG2,W
VG2,R
HM 400 100
PG Leakage
300
200 10-3
Ticker tox2 10-6 -1.75 -1.50
-1.00
Hold Margin (mV)
PG Leakage Current (μA/μm)
PG Design for Hold Margin and Leakage Current
VG2,R
VWL,L VDD=1.0 V
100
Less Leakage -0.50
PG Leakage
0 0.00
Low Level of WL Signal, VWL,L (V)
0.0 V
VG2,W
1.0 V
PG Design for RM and Readout Current 750
500
Readout Current 500 300
RM 200 250 B: tox2 = 2.5tox1 C: tox2 = 4.0tox1 D: tox2 = 7.0tox1
-1.00
-0.75
Hld
R
R
R
VWL,H VWL,L
Hld
400
0 -1.25
Hld
Larger Current
Read Margin (mV)
PG Readout Current (μA/μm)
Ticker tox2
Hld
VWL,L
VG2,R
Hld
Hld
VG2,R
VG2,R
VWL,H = 1.0 V VDD=1.0 V
100
-0.50
-0.25
PG Readout
0 0.00
Second Gate Voltage for Read, VG2,R (V)
1.0 V
VG2,R
1.0 V
Summary of PG Design Thicker tox2 • Larger Readout Current • Less Leakage Current
• Larger VG2 for Sufficient WM
Signal Levels for PGs with tox2 = 4.0 tox1 Low Level
High Level
WL Signal VWL (V)
VWL,L / -1.0
VWL,H / 1.0
Vth-Ctrl Signal VG2 (V)
VG2,R / -1.0
VG2,W / 1.0
Additional Peripheral Circuits Column Address
VDD
VDD
VSS[=0]
Column Dec.
VG1,Hld
WE LS Row Dec.
Row Address
Level Shifter LS
LS MC
MC
MC
MC
Vth-Ctrl
Vth-Ctrl
LS
BLs
BLs
WLs
STEM images of the fabricated independent doublegate 4T-FinFETs
Asymmetric-Oxide DG tox1 = tox2 =1.7 nm
Gate-1 tox1
Gate-2 tox2
tox1 < tox2 Hfin = 192 nm Hfin/TSi = 18
Gate-1 tox1 = 1.7 nm
TiN
tox1
tox2 TSi
Gate-2 tox2 = 3.4 nm
TiN TSi = 12 nm
60 nm
Symmetric tox 4T-FinFET
TSi = 11 nm
80 nm
Asymmetric tox 4T-FinFET
Y.X. Liu et al., 2006 IEDM, 2007 IEEE EDL (AIST)
Asymmetric-Oxide DG Lg = 1 μm
tox1 = tox2 = 1.7 nm 10-3
10-3
10-4
VD = 0.05 V
10-5
I D [ A/ μ m ]
tox1 = 1.7 nm tox2 = 3.4 nm
10-4
VD = 0.05 V
10-5
10-6
10-6
10-7
10-7
10-8
10-8
10-9
10-9
10-10
10-10
10-11
10-11
10-12
10-12
10-13 -0.5
10-13 -0.5
0
0.5
1
1.5
V G1 [ V ]
Symmetric tox 4T-FinFET
0
0.5
1
1.5
V G1 [ V ]
Asymmetric tox 4T-FinFET
Y.X. Liu et al., 2006 IEDM, 2007 IEEE EDL (AIST)
RM/WM Enhancement by Flex-PG βPD/βPG = 2
βPD/βPG = 2
Flex-PG
Margin (mV)
400
Read Write 300
200
Both RM and WM are Enhanced
100
0
Planar Bulk
3T-FinFET
Flex-PG
Nominal Margins
Variability in Vth D G
G
60
Device-Level Variability Suppression by Using an Undoped Body
Parameter
Fluctuation
Gate Length Fin Thickness
Gaussian 3σ = 0.2 LG
Channel Dopant Number
Poisson μ = Nchan
μ = 410 mV
μ = 330 mV
40
S
Planar Bulk
3T-FinFET
Frequency
Fluctuation Model
D
S
3σ = 95 mV
3σ = 39 mV
20
0 100
200
300
400
500
Threshold Voltage (mV) * Number of Samples: 200
600
Variability in RM and WM 40
3T-FinFET
Frequency
RM
70-mV Gain of Margin for 6σ Variation
30
Planar Bulk
20
Flex-PG
6σ 10 0 0
100
200
300
400
40
Frequency
WM
3T-FinFET
Comparable Margin for 6σ Variation
30 20
Flex-PG
Planar Bulk
10
6σ
0 0
100
200
300
Read/Write Margin (mV)
400
* Number of Samples: 100
Conclusion • Flex-PG SRAM enhances both RM and WM independently. • Asymmetric 4T-FinFET improves the performance of the Flex-PG SRAM. • Flex-PG SRAM is applicable to hp-32nm LSTP applications, with sufficient tolerance for 6-σ variability.
Outline • Background • Proposal of Flex-Pass-Gate SRAM – Memory cell – Operation in array
• Performance Estimation for hp-32-nm LSTP Applications – Pass gate design strategy – Static noise margin estimation – Variability tolerance
• Conclusion
Background –SRAM Yield Design Margin
WL BL
WM
BLB
Vth Variation Vth,PG
Vth,PG
Conventional 6Tr-SRAM
Increased Variation WM
V2
V2
Trade Off
RM
RM Vth,PG V1
Read Margin, RM
V1
Write Margin, WM
Malfunctions!
Flex-Pass-Gate SRAM Conventional WL
WM
BL
BLB
RM Vth,PG
Fixed Vth,PG Vth,PG for Write Vth-Ctrl
Vth,PG for Read
Vth-Ctrl
WM D
D Gate S
Gate1
S
Gate2
RM Vth,PG
3T-FinFET
4T-FinFET
Flex-PG
3-Terminal and 4-Terminal FinFETs D Gate
VD
S
Gate Separation
D
VD
G1
S
G2
VG1
VG
10-6
10-7 10-8 10-9
Tsi=8.5nm Tox=1.7nm Lg=160nm
10-10 10-11 10-12 -1
-0.5
0 0.5 VG1(V)
1
ID (A/ μm)
ID (A/ μm)
10-6
VD=0.05V
10-7 10-8
.2V
10-5
G2 =1
10-4
VD=0.05V
10-9
10-10
V
10-5
4T-FinFET
V
10-4
VS
VS
G2 =0 V
3T-FinFET
VG2
10-11 10-12 -1
-0.5
0 0.5 VG1(V)
Tsi=8.5nm Tox=1.7nm Lg=160nm 1
+0.2V-step VG2 Increment
Y-X Liu et al. , 2003IEDM, 2004EDL (AIST)
RM and WM Enhancement • Using Dynamic VG2 Control VG2
VG2
VG2,R
VG2,W 0.40
Lowering VG2
Raising VG2 1.0
V2 (V)
1.0
V2 (V)
RM
V2 BLB
0.5
0.15
WM
VG2=1.0 -0.5
0
0.5
1.0
VG2 (V) -0.15
VG2=-0.5
0.0 0.0
0.5
0.30
Margin (V)
BL V1
0.5
V1 (V)
RM
1.0
0.0 0.0
0.5
V1 (V)
WM
1.0
Margins vs. VG2
Cell Layout and Area Overhead PG(４T-FinFET) 8F
Selective Gate Separation Contact of Vth-Ctrl Line
120F2
15F
VSS
VthVthBL Ctrl VDD Ctrl BLB VSS
3rd Layer (Vth-Ctrl, VDD, VSS, BL) 2rd Layer (WL) 1st Layer (Intra-Cell, not shown)
WL
3 Metal Layers Enough for Interconnection
Selective Gate Separation Gate1
Etching Stopper Fin
Fin Top P.R. Source
Drain
Gate BOX sub
Gate2
100nm
Side Wall
Top View
G1 HFin=100nm
DG Separation by Etching-Back Process
G2 ＴFin=25nm
100nm
Cross-Sectional View
K. Endo et al., 2007 IEEE EDL (AIST)
Array Configuration • Column-by-Column VG2 Control Column Address Column Peripheral
Row Peripheral
Row Address
WE
MC
MC
MC
MC
WLs
WL BL
Vth-Ctrl
Vth-Ctrl
BLs
BLs
Vth-Ctrl
Memory Cell
BLB Vth-Ctrl
Read Operation • Stable Read PG: On, High Vth Column Peripheral
WL
Row Peripheral
BL
R
R
Hld
Hld
L
L
H L
Vth-Ctrl
BLB Vth-Ctrl
Write Operation • Fast/Stable Write
PG: On, Low Vth WL
Column Peripheral BLB
Row Peripheral
BL
R Hld
W
H
Hld
L
Vth-Ctrl
Vth-Ctrl
PG: Off, Low Vth WL BL
L
H L
Vth-Ctrl
PG-Leakage Current Reduction 1. Negative Low-Level on WL 2. Thicker Second-Gate Oxide
BLB Vth-Ctrl
Performance Estimation Model • Technology assumption: hp-32-nm LSTP LG = 20 nm Gate1
tox1 = 1.2 nm
Drain
Source
tox2: Variable Gate2 10-nm G-S/D Underlap + S/D Doping Profile (σ = 3 nm)
Device Model
Drain Current (μA/μm)
10
4
10
|VDD| = 0.05, 1.0 V
10 3
4
10 3
10 0
10 0
PMOS
NMOS 10-3
10-3
tox1 = tox2 10-6
10-6 -1.00
-0.50
0.00
0.50
Gate Voltage (V)
Simulated ID-VG of 3T-FinFET
1.00
PG Design for Write Margin VG1,RW = 1.0 V
500
Write Margin (mV)
D: tox2 = 7.0 tox1 400
VDD=1.0 V
C: tox2 = 4.0 tox1 B: tox2 = 2.5 tox1
300
A: tox2 = tox1
0.0 V
200
100
0 0.00
Ticker tox2 0.50
1.00
VG2,W
Larger VG2,W 1.50
Second Gate Voltage for Write, VG2,W (V)
tox2
1.0 V
103
Write Condition A: tox2 = tox1, VG2,W = 0.70 V B: tox2 = 2.5tox1, VG2,W = 0.85 V C: tox2 = 4.0tox1 , VG2,W = 1.00 V D: tox2 = 7.0tox1 , VG2,W = 1.25 V
Hld
Hld
Hld
R
W
R
VWL,L VWL,H VWL,L
500 Hld
Hld
Hld
VG2,W
VG2,R
HM 400 100
PG Leakage
300
200 10-3
Ticker tox2 10-6 -1.75 -1.50
-1.00
Hold Margin (mV)
PG Leakage Current (μA/μm)
PG Design for Hold Margin and Leakage Current
VG2,R
VWL,L VDD=1.0 V
100
Less Leakage -0.50
PG Leakage
0 0.00
Low Level of WL Signal, VWL,L (V)
0.0 V
VG2,W
1.0 V
PG Design for RM and Readout Current 750
500
Readout Current 500 300
RM 200 250 B: tox2 = 2.5tox1 C: tox2 = 4.0tox1 D: tox2 = 7.0tox1
-1.00
-0.75
Hld
R
R
R
VWL,H VWL,L
Hld
400
0 -1.25
Hld
Larger Current
Read Margin (mV)
PG Readout Current (μA/μm)
Ticker tox2
Hld
VWL,L
VG2,R
Hld
Hld
VG2,R
VG2,R
VWL,H = 1.0 V VDD=1.0 V
100
-0.50
-0.25
PG Readout
0 0.00
Second Gate Voltage for Read, VG2,R (V)
1.0 V
VG2,R
1.0 V
Summary of PG Design Thicker tox2 • Larger Readout Current • Less Leakage Current
• Larger VG2 for Sufficient WM
Signal Levels for PGs with tox2 = 4.0 tox1 Low Level
High Level
WL Signal VWL (V)
VWL,L / -1.0
VWL,H / 1.0
Vth-Ctrl Signal VG2 (V)
VG2,R / -1.0
VG2,W / 1.0
Additional Peripheral Circuits Column Address
VDD
VDD
VSS[=0]
Column Dec.
VG1,Hld
WE LS Row Dec.
Row Address
Level Shifter LS
LS MC
MC
MC
MC
Vth-Ctrl
Vth-Ctrl
LS
BLs
BLs
WLs
STEM images of the fabricated independent doublegate 4T-FinFETs
Asymmetric-Oxide DG tox1 = tox2 =1.7 nm
Gate-1 tox1
Gate-2 tox2
tox1 < tox2 Hfin = 192 nm Hfin/TSi = 18
Gate-1 tox1 = 1.7 nm
TiN
tox1
tox2 TSi
Gate-2 tox2 = 3.4 nm
TiN TSi = 12 nm
60 nm
Symmetric tox 4T-FinFET
TSi = 11 nm
80 nm
Asymmetric tox 4T-FinFET
Y.X. Liu et al., 2006 IEDM, 2007 IEEE EDL (AIST)
Asymmetric-Oxide DG Lg = 1 μm
tox1 = tox2 = 1.7 nm 10-3
10-3
10-4
VD = 0.05 V
10-5
I D [ A/ μ m ]
tox1 = 1.7 nm tox2 = 3.4 nm
10-4
VD = 0.05 V
10-5
10-6
10-6
10-7
10-7
10-8
10-8
10-9
10-9
10-10
10-10
10-11
10-11
10-12
10-12
10-13 -0.5
10-13 -0.5
0
0.5
1
1.5
V G1 [ V ]
Symmetric tox 4T-FinFET
0
0.5
1
1.5
V G1 [ V ]
Asymmetric tox 4T-FinFET
Y.X. Liu et al., 2006 IEDM, 2007 IEEE EDL (AIST)
RM/WM Enhancement by Flex-PG βPD/βPG = 2
βPD/βPG = 2
Flex-PG
Margin (mV)
400
Read Write 300
200
Both RM and WM are Enhanced
100
0
Planar Bulk
3T-FinFET
Flex-PG
Nominal Margins
Variability in Vth D G
G
60
Device-Level Variability Suppression by Using an Undoped Body
Parameter
Fluctuation
Gate Length Fin Thickness
Gaussian 3σ = 0.2 LG
Channel Dopant Number
Poisson μ = Nchan
μ = 410 mV
μ = 330 mV
40
S
Planar Bulk
3T-FinFET
Frequency
Fluctuation Model
D
S
3σ = 95 mV
3σ = 39 mV
20
0 100
200
300
400
500
Threshold Voltage (mV) * Number of Samples: 200
600
Variability in RM and WM 40
3T-FinFET
Frequency
RM
70-mV Gain of Margin for 6σ Variation
30
Planar Bulk
20
Flex-PG
6σ 10 0 0
100
200
300
400
40
Frequency
WM
3T-FinFET
Comparable Margin for 6σ Variation
30 20
Flex-PG
Planar Bulk
10
6σ
0 0
100
200
300
Read/Write Margin (mV)
400
* Number of Samples: 100
Conclusion • Flex-PG SRAM enhances both RM and WM independently. • Asymmetric 4T-FinFET improves the performance of the Flex-PG SRAM. • Flex-PG SRAM is applicable to hp-32nm LSTP applications, with sufficient tolerance for 6-σ variability.
