Flip-Chip Bonding on 6-um Pitch using Thin-Film ... - Semantic Scholar
Flip-Chip Bonding on 6-um Pitch using Thin-Film Microspring Technology
Donald L. Smith, David K. Fork, Robert L. Thornton, Andrew S. Alimonda, Christopher L. Chua, Clarence Dunnrowicz, and Jackson Ho Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
Copyright © 1998 Institute of Electrical and Electronics Engineers. Reprinted from Proceedings, 48th Electronic Components and Technology Conference; Seattle, Washington (May, 1998); ©1998 IEEE.
This material is posted here with permission of the IEEE Internal or personal use of this material is permitted. How purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by sending a blank email message to [email protected].
By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Flip-Chip Bonding on 6-um Pitch using Thin-Film Microspring Technology Donald L. Smith, David K. Fork, Robert L. Thornton, Andrew S. Alimonda, Christopher L. Chua, Clarence Dunnrowicz, and Jackson Ho Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304 Abstract Bonding-pad densities on high-performance integratedcircuit chips are beginning to exceed the limits of available interconnect technologies. Also, stresses due to thermal mismatch in flip-chipped packages are reducing time to contact failure. We have addressed both of these problems by microlithographically fabricating highly elastic cantilever springs in linear arrays on pitches down to 6 µm. We have soldered test arrays of 52 springs on this pitch to Si chips with 100% contact yield and good solder wetting to every spring. The fine-pitch capability also facilitates off-chip routing; the very high compliance of the springs should avoid thermal fatigue; and the low thermal conductance along the springs should allow fast-cycle soldering of chips to multi-chip modules as well as replacement of chips subsequently testing faulty. Background As chip density and pad counts increase in the pursuit of higher clock speed and functionality, the spacing between pads has to become smaller. This spacing is currently pressing the limits of available technologies to provide electrical isolation between adjacent pads and sufficient mechanical compliance to prevent fatigue failure from thermal and mechanical stress cycling.1 Recently2, two of us demonstrated a thin-film microlithographic technique for making arrays of cantilevered spring fingers on 80-µm pitch for application to both wafer probing and flip-chip bonding. We report here on the extension of this technology to 6-µm pitch and on the soldering of test arrays to mating chips. Compared to other reported technologies, the microsprings offer 10x finer pitch, improved impedance matching, and very high compliance. In addition, the structure is expected to facilitate de-soldering and replacement of bad chips in a mutlti-chip module (MCM) without disturbing the module or damaging the fingers, thus potentially bypassing prepackaging known-good-die (KGD) testing. Fabrication The microspring structure is shown schematically in Fig. 1, with L greatly foreshortened for clarity. Fabrication and mechanics are described in detail elsewhere2,3 and summarized here. Glass substrates were used, but others are possible too. Glass has the advantage of combining transparency, smoothness, low cost, and familiarity from use in flat-panel displays. The elastic (springy), refractory alloy Mo0.8Cr0.2 is sputter-deposited onto a substrate pre-coated with a “release” layer of plasma-deposited Si nitride. By gradually increasing Ar pressure during deposition, a very large and closely controlled intrinsic-stress gradient (• σ/h) can be grown into the MoCr film: from over 1000 MPa compressive at the
bottom to over 1000 MPa tensile at the top of the 1-µm-thick film. To improve conductivity and solderability, about 200 nm of Au is sputtered over the MoCr before breaking vacuum. The film is patterned with photolithography and wet etching into rows of parallel fingers. The fingertip is shown pointed, but it can be any desired shape. Then a passivation dielectric can be deposited if desired. Finally, a second mask is applied that leaves windows exposing the outer 100 µm or so of the fingers. Upon dipping in buffered HF solution, the Si nitride etches out from under the fingers in these regions. Thereupon, the fingers curl up to a radius of about 150 um to relax the stress gradient, leaving their tips lifted about 35 µm above the substrate surface.
,, ,, ,, F
MoCr
passivation Au
,,
substrate
L
r w h ∆σ
Figure 1: Perspective view of spring finger, showing released and stress-relaxed cantilever portion within passivation window, and showing anchored portion to the right.
Our current test mask set provides and has produced defect-free microspring arrays of 1000 fingers on 80 and 24µm pitch, 26 on 12-µm, and 52 on 6-µm pitch. Fig. 2 shows a scanning electron micrograph (SEM) of one complete array on 12-µm pitch and part of a second, and Fig. 3 shows part of an array on 6-µm pitch. In both figures, the right-hand 2/3 of the 150-µm-long fingers is lifted towards you from the substrate, and the remainder is anchored. In Fig. 2, the shadow of the rectangular release-etching window can be seen framing the lifted area. For end-to-end electrical continuity testing, we have made dummy Si chips having linear arrays of bonding pads spanning two fingertips each, and we have flip-chip mounted them to the above arrays of fingers connected in pairs in a “daisy chain” as shown in Fig. 4. The contact between fingertips and pads was observed directly through the glass substrate while the chip, mounted on a vacuum chuck, was manipulated into alignment and the fingers were compressed.
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Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 3: SEM photo of the center portion of a 52-finger microspring array on 6-µm pitch. Lifted fingertips are to the far right.
solder
adhesive
Figure 2: SEM photo of 26-finger microspring array on 12-µm pitch. Fingertips just to the right of center are lifted 35 µm up from the glass substrate, and slightly grayer left-hand 1/3 of the finger length is anchored to the substrate
solder pad
150 µm 3 µm
Figure 5: Proposed encapsulation can, applied after chip soldering, provides support, protection, and heat-sinking through backside fins.
alone and required no other support for testing. In a product, they would need to be secured by a glued-on can as shown in Fig. 5 or otherwise.
anchored finger
lifted finger
Figure 4: Geometry for flip-chip bonding, corresponding to the photos in Fig’s. 6 and 7. Here, lifted fingers are pointing away from you, and solder pads are on the mating Si chip underneath them.
Compression produces a force F at the fingertips (Fig. 1) which increases roughly linearly with compression. Chips having sputtered Au bonding pads were contacted to the fingers by F alone and were secured by mounting their backs to Kovar cans that were then glued to the substrate with UV-curing acrylic cement, as shown in Fig. 5 (less the fins). Other chips having pads of 1.5-µm-thick evaporated In were soldered to the fingertips by heating the vacuum chuck. To avoid the messiness and potential corrosion problems of solder flux, both exacerbated by the fine pitch, the In native oxide skin was skimmed from the molten solder using the fingertips themselves. Soldered 2x2-mm chips having two each of the 12 and 6-µm-pitch arrays hung by the fingertips
Results Chips having Au fingertips pressure-contacted to Au pads gave 100% initial electrical contact for 200-finger arrays on 80-µm pitch. However, conductivity became sensitive to shock after a few weeks and finally failed. Unreliable Au-Au contacts have also been observed by others4 using atomic force microscope-type tips of 80-nm radius, and we both attribute it to the deposition of insulating contaminants from the environment. Contamination probably does not intrude directly into the contacted area because of the very high contact pressure. However, a slight shift in the contact point, due to vibration or to tilting caused by thermal expansion, could cause a fingertip to shift up onto adjacent contaminated surface. The much larger-area Au-Au pressure contacts reliably and widely used in electrical connectors may be surviving only because they never shift enough to disconnect all of the initial clean contact area. Soldered contacts are not subject to the above problem, though corrosion and metallurgical reactions over lifetime
2
Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 6: Optical micrograph of soldered flip-chip assembly on 12-µm pitch, taken through the glass substrate. Layout is the same as in Fig. 4.
need to be examined. Fig’s. 6 and 7 show arrays of fingers on 12 and 6-µm pitch, respectively, soldered to a Si test chip as described above. We are looking through the back of the glass substrate at the fingertips curling away from us. The orientation and geometry are the same as in Fig. 4, with the glass-anchored finger ends to the left and the solder pads to the right. The fingers’ appearance changes from bright to dark moving to the right because their tilt with respect to the
Figure 7: As Fig. 6, but on 6-µm pitch.
microscope’s coaxial illumination is becoming so large that no light reflects back into the objective lens. The shiny solder pads can be seen between alternate pairs of fingers; the pads extend 25 µm or so to the left of the fingertips and also to the right edge of the photographs. The 12-µm-pitch fingers are evenly spaced and well aligned to the pads. The 6-µm ones are less even than in the unsoldered array of Fig. 3. Presumably they were pulled around somewhat by surface tension during soldering, being much less stiff laterally than the wider fingers.
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Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 8: SEM photo of broken fingertips from the 6-µm array, left embedded in solder pad after removal of soldered chip.
Figure 10: Bottom-view (Au side) SEM of a typical fingertip that pulled out of the 6-µm array. EDX showed good In wetting.
End-to-end electrical contact was obtained for both of the soldered arrays shown. For the 52 fingers on 6-µm pitch, resistance was 530 • , which is roughly accounted for by the 0.24 • /square sheet resistivity of the Au/MoCr film. On the 12-µm array, one of the probe pads was occluded by the Si chip, making it difficult to reach so that we were unable to obtain a reliable contact. For closer examination of the soldered fingertips and chip pads, the chip was pried off to allow SEM beam access. Most fingers broke off just to the left of the soldered area, leaving the tips embedded in the solder. That position is where the maximum bending stress would have developed during the prying operation, since the fingers would have been bent the most backwards there. On the 12-µm array, 4 of the 26 fingers pulled out of the solder instead of breaking off, and on the 6µm array, 9 of 52 did so. Fig. 8 shows a typical pair of embedded fingertips on the 6-µm array. The In oxide skin can
Figure 9: Close-up SEM of one broken-off fingertip from the 6-µm array, showing pulling up of a mesa of In solder onto the bottom of the finger.
Figure 11: Bottom-view (Au side) SEM of a typical finger whose tip broke off and remained in the solder as in Fig. 8.
be seen plowed up over the fingertips to the right. On the bottom of the fingers, around their break-off points to the left, can be seen the lighter and wider thin Au film. The Au is wider because of the undercut experienced by the MoCr during wet-etch patterning. Fig. 9 shows a closer view of another finger from the same array in which the In appears to have been either wicked up onto the finger during soldering or stretched up during chip removal. In either case it demonstrates good bonding. All of the fingertips that pulled out of the 6-µm array were analyzed for In, Au, and MoCr by x-ray (EDX) in the SEM. A 10-nm Au overcoat to avoid charging compromised Au analysis. Fig. 10 shows a typical pulled-out fingertip. The wide, flat surface to the far left is the unwetted Au film. Moving to the right, the cauliflower-textured band is In (4100 counts of the Lα1 peak) and Au (5500 counts of Mα1,2). The region further to the right, extending to the tip and narrower across the finger, is 600 counts of Mo-Lα1, 500 Au, 350 In,
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Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
and 50 Cr-Kα1. All 9 pull-outs contained similar amounts of In, showing that good solder wetting was obtained in all cases. Thus, the 9 fingers pulled out because the In fractured and not because the In failed to wet these fingers. Fig. 11 shows a typical broken-off fingertip from the 6-µm array. The cauliflower region again analyzes as In-Au. The chip pads also showed no bridging of solder between pads on either array, so the resistances quoted above represent the whole daisy chain and do not involve shorts. Evaluation and Prospects The 100% soldering yield for the above arrays is promising, and further testing is underway to see how it scales for higher pincounts. Harder solders and other fluxless soldering techniques and finger metals are also being investigated. Some refractory, elastic metals are plasma etchable, and these would allow anisotropic etching that would prevent finger narrowing, thus making them less subject to the lateral deflection seen on the 6-µm pitch and probably extending the pitch capability to 3 µm. Shorter fingers could be used to increase stiffness, decrease pitch in the finger direction, and decrease series resistance, provided that chip-substrate coplanarity was sufficient so that less than 35 µm of lift and compliance was needed. Lift scales as L2/h (see Fig. 1 and ref. 2). Resistance can also be lowered by increasing the Au thickness. Because Au is much softer than MoCr, it cannot be deposited highly tensile, but on the other hand it does not seem to reduce MoCr curling very much either. Current- carrying capacity can be increased further for the high-power connections to a chip by distributing the load among many fingers around the chip, thus also reducing series-resistance losses within the chip. The fine pitch also leaves room for ground lines between every signal line for reduced crosstalk. These and/or underlying ground planes could be structured for impedance matching all the way up to the finger lift-off point, and grounded fingers could even be extended to the chip if desired. The very small chip pad area compared to conventional pads also reduces parasitic capacitance. Because of the very high compliance and elasticity of the microsprings compared to contacts used in other flip-chip technologies, they should greatly improve shock resistance and reduce thermal-fatigue failure on thermally mismatched substrates such as glass or ceramic MCMs or GaAs-based devices used for optical interconnects or laser print bars5. The transparency of glass substrates provides the advantages of simplifying alignment optics and allowing joint inspection after soldering. After full electrical testing and burn-in of an MCM, individual faulty chips could be melted off and replaced using a heated vacuum chuck on a micromanipulator without disturbing neighboring chips, because of the high thermal resistance along the fingers from the solder joints to the module substrate. This rework capability would likely represent a considerable cost savings over full KGD testing before MCM assembly. All of this could be done with the chips held only by the soldered fingers. Finally, encapsulation cans could be applied as shown in Fig. 5 to provide ruggedness, protection from contamination, and heat-sinking through fins on the can.
Conclusions We have made a preliminary demonstration of a flip-chip packaging technology that has much finer pitch and higher mechanical compliance than existing technologies. This should allow direct connection of high-density peripheral chip pads to thermally mismatched substrates without the use of fan-ins to area arrays, underfill stiffeners, or intermediate carriers. The high elasticity of the microsprings should also avoid thermal-fatigue failure when coupled with a hard solder. Fine pitch and microlithographic fabrication will allow leadout designs giving good impedance match, low crosstalk, and low parasitic inductance and capacitance. Inherent ease of rework may avoid the need for KDG testing.
Acknowledgments The authors are grateful to David Horine for enlightening discussions about packaging technology and comments on the manuscript, Bill Mosby for indium depositions, and the waferline crew for expert processing.
References 1. Lau, J. H., ed., Flip-Chip Technologies, McGraw-Hill (New York, 1996). 2. Smith, D. L., and A. S. Alimonda, “A New Flip-Chip Technology for High-Density Packaging”, Proc 46th Electronic Components and Technology Conf. (Orlando, Florida, May 1996), pp. 1069-1073. 3. Smith, D. L., and A. S. Alimonda, “Photolithographically Patterned Spring Contact”, U. S. Patent #5,613,861 (1997). [Other patents pending.] 4. Beale, J., and R. F. Pease, “Limits of High-Density, LowForce Pressure Contacts”, IEEE Trans-CPMT-A, Vol. 17, No. 2 (1994), pp. 257-262. 5. Chua, C. L., R. L. Thornton, and D. W. Treat, “Planar Laterally Oxidized Vertical-Cavity Lasers for LowThreshold High-Density Top-Surface-Emitting Arrays”, IEEE Photon. Technol. Lett., Vol. 9, No. 8 (1997), pp. 1060-1062.
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Donald L. Smith, David K. Fork, Robert L. Thornton, Andrew S. Alimonda, Christopher L. Chua, Clarence Dunnrowicz, and Jackson Ho Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
Copyright © 1998 Institute of Electrical and Electronics Engineers. Reprinted from Proceedings, 48th Electronic Components and Technology Conference; Seattle, Washington (May, 1998); ©1998 IEEE.
This material is posted here with permission of the IEEE Internal or personal use of this material is permitted. How purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by sending a blank email message to [email protected].
By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Flip-Chip Bonding on 6-um Pitch using Thin-Film Microspring Technology Donald L. Smith, David K. Fork, Robert L. Thornton, Andrew S. Alimonda, Christopher L. Chua, Clarence Dunnrowicz, and Jackson Ho Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304 Abstract Bonding-pad densities on high-performance integratedcircuit chips are beginning to exceed the limits of available interconnect technologies. Also, stresses due to thermal mismatch in flip-chipped packages are reducing time to contact failure. We have addressed both of these problems by microlithographically fabricating highly elastic cantilever springs in linear arrays on pitches down to 6 µm. We have soldered test arrays of 52 springs on this pitch to Si chips with 100% contact yield and good solder wetting to every spring. The fine-pitch capability also facilitates off-chip routing; the very high compliance of the springs should avoid thermal fatigue; and the low thermal conductance along the springs should allow fast-cycle soldering of chips to multi-chip modules as well as replacement of chips subsequently testing faulty. Background As chip density and pad counts increase in the pursuit of higher clock speed and functionality, the spacing between pads has to become smaller. This spacing is currently pressing the limits of available technologies to provide electrical isolation between adjacent pads and sufficient mechanical compliance to prevent fatigue failure from thermal and mechanical stress cycling.1 Recently2, two of us demonstrated a thin-film microlithographic technique for making arrays of cantilevered spring fingers on 80-µm pitch for application to both wafer probing and flip-chip bonding. We report here on the extension of this technology to 6-µm pitch and on the soldering of test arrays to mating chips. Compared to other reported technologies, the microsprings offer 10x finer pitch, improved impedance matching, and very high compliance. In addition, the structure is expected to facilitate de-soldering and replacement of bad chips in a mutlti-chip module (MCM) without disturbing the module or damaging the fingers, thus potentially bypassing prepackaging known-good-die (KGD) testing. Fabrication The microspring structure is shown schematically in Fig. 1, with L greatly foreshortened for clarity. Fabrication and mechanics are described in detail elsewhere2,3 and summarized here. Glass substrates were used, but others are possible too. Glass has the advantage of combining transparency, smoothness, low cost, and familiarity from use in flat-panel displays. The elastic (springy), refractory alloy Mo0.8Cr0.2 is sputter-deposited onto a substrate pre-coated with a “release” layer of plasma-deposited Si nitride. By gradually increasing Ar pressure during deposition, a very large and closely controlled intrinsic-stress gradient (• σ/h) can be grown into the MoCr film: from over 1000 MPa compressive at the
bottom to over 1000 MPa tensile at the top of the 1-µm-thick film. To improve conductivity and solderability, about 200 nm of Au is sputtered over the MoCr before breaking vacuum. The film is patterned with photolithography and wet etching into rows of parallel fingers. The fingertip is shown pointed, but it can be any desired shape. Then a passivation dielectric can be deposited if desired. Finally, a second mask is applied that leaves windows exposing the outer 100 µm or so of the fingers. Upon dipping in buffered HF solution, the Si nitride etches out from under the fingers in these regions. Thereupon, the fingers curl up to a radius of about 150 um to relax the stress gradient, leaving their tips lifted about 35 µm above the substrate surface.
,, ,, ,, F
MoCr
passivation Au
,,
substrate
L
r w h ∆σ
Figure 1: Perspective view of spring finger, showing released and stress-relaxed cantilever portion within passivation window, and showing anchored portion to the right.
Our current test mask set provides and has produced defect-free microspring arrays of 1000 fingers on 80 and 24µm pitch, 26 on 12-µm, and 52 on 6-µm pitch. Fig. 2 shows a scanning electron micrograph (SEM) of one complete array on 12-µm pitch and part of a second, and Fig. 3 shows part of an array on 6-µm pitch. In both figures, the right-hand 2/3 of the 150-µm-long fingers is lifted towards you from the substrate, and the remainder is anchored. In Fig. 2, the shadow of the rectangular release-etching window can be seen framing the lifted area. For end-to-end electrical continuity testing, we have made dummy Si chips having linear arrays of bonding pads spanning two fingertips each, and we have flip-chip mounted them to the above arrays of fingers connected in pairs in a “daisy chain” as shown in Fig. 4. The contact between fingertips and pads was observed directly through the glass substrate while the chip, mounted on a vacuum chuck, was manipulated into alignment and the fingers were compressed.
1
Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 3: SEM photo of the center portion of a 52-finger microspring array on 6-µm pitch. Lifted fingertips are to the far right.
solder
adhesive
Figure 2: SEM photo of 26-finger microspring array on 12-µm pitch. Fingertips just to the right of center are lifted 35 µm up from the glass substrate, and slightly grayer left-hand 1/3 of the finger length is anchored to the substrate
solder pad
150 µm 3 µm
Figure 5: Proposed encapsulation can, applied after chip soldering, provides support, protection, and heat-sinking through backside fins.
alone and required no other support for testing. In a product, they would need to be secured by a glued-on can as shown in Fig. 5 or otherwise.
anchored finger
lifted finger
Figure 4: Geometry for flip-chip bonding, corresponding to the photos in Fig’s. 6 and 7. Here, lifted fingers are pointing away from you, and solder pads are on the mating Si chip underneath them.
Compression produces a force F at the fingertips (Fig. 1) which increases roughly linearly with compression. Chips having sputtered Au bonding pads were contacted to the fingers by F alone and were secured by mounting their backs to Kovar cans that were then glued to the substrate with UV-curing acrylic cement, as shown in Fig. 5 (less the fins). Other chips having pads of 1.5-µm-thick evaporated In were soldered to the fingertips by heating the vacuum chuck. To avoid the messiness and potential corrosion problems of solder flux, both exacerbated by the fine pitch, the In native oxide skin was skimmed from the molten solder using the fingertips themselves. Soldered 2x2-mm chips having two each of the 12 and 6-µm-pitch arrays hung by the fingertips
Results Chips having Au fingertips pressure-contacted to Au pads gave 100% initial electrical contact for 200-finger arrays on 80-µm pitch. However, conductivity became sensitive to shock after a few weeks and finally failed. Unreliable Au-Au contacts have also been observed by others4 using atomic force microscope-type tips of 80-nm radius, and we both attribute it to the deposition of insulating contaminants from the environment. Contamination probably does not intrude directly into the contacted area because of the very high contact pressure. However, a slight shift in the contact point, due to vibration or to tilting caused by thermal expansion, could cause a fingertip to shift up onto adjacent contaminated surface. The much larger-area Au-Au pressure contacts reliably and widely used in electrical connectors may be surviving only because they never shift enough to disconnect all of the initial clean contact area. Soldered contacts are not subject to the above problem, though corrosion and metallurgical reactions over lifetime
2
Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 6: Optical micrograph of soldered flip-chip assembly on 12-µm pitch, taken through the glass substrate. Layout is the same as in Fig. 4.
need to be examined. Fig’s. 6 and 7 show arrays of fingers on 12 and 6-µm pitch, respectively, soldered to a Si test chip as described above. We are looking through the back of the glass substrate at the fingertips curling away from us. The orientation and geometry are the same as in Fig. 4, with the glass-anchored finger ends to the left and the solder pads to the right. The fingers’ appearance changes from bright to dark moving to the right because their tilt with respect to the
Figure 7: As Fig. 6, but on 6-µm pitch.
microscope’s coaxial illumination is becoming so large that no light reflects back into the objective lens. The shiny solder pads can be seen between alternate pairs of fingers; the pads extend 25 µm or so to the left of the fingertips and also to the right edge of the photographs. The 12-µm-pitch fingers are evenly spaced and well aligned to the pads. The 6-µm ones are less even than in the unsoldered array of Fig. 3. Presumably they were pulled around somewhat by surface tension during soldering, being much less stiff laterally than the wider fingers.
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Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
Figure 8: SEM photo of broken fingertips from the 6-µm array, left embedded in solder pad after removal of soldered chip.
Figure 10: Bottom-view (Au side) SEM of a typical fingertip that pulled out of the 6-µm array. EDX showed good In wetting.
End-to-end electrical contact was obtained for both of the soldered arrays shown. For the 52 fingers on 6-µm pitch, resistance was 530 • , which is roughly accounted for by the 0.24 • /square sheet resistivity of the Au/MoCr film. On the 12-µm array, one of the probe pads was occluded by the Si chip, making it difficult to reach so that we were unable to obtain a reliable contact. For closer examination of the soldered fingertips and chip pads, the chip was pried off to allow SEM beam access. Most fingers broke off just to the left of the soldered area, leaving the tips embedded in the solder. That position is where the maximum bending stress would have developed during the prying operation, since the fingers would have been bent the most backwards there. On the 12-µm array, 4 of the 26 fingers pulled out of the solder instead of breaking off, and on the 6µm array, 9 of 52 did so. Fig. 8 shows a typical pair of embedded fingertips on the 6-µm array. The In oxide skin can
Figure 9: Close-up SEM of one broken-off fingertip from the 6-µm array, showing pulling up of a mesa of In solder onto the bottom of the finger.
Figure 11: Bottom-view (Au side) SEM of a typical finger whose tip broke off and remained in the solder as in Fig. 8.
be seen plowed up over the fingertips to the right. On the bottom of the fingers, around their break-off points to the left, can be seen the lighter and wider thin Au film. The Au is wider because of the undercut experienced by the MoCr during wet-etch patterning. Fig. 9 shows a closer view of another finger from the same array in which the In appears to have been either wicked up onto the finger during soldering or stretched up during chip removal. In either case it demonstrates good bonding. All of the fingertips that pulled out of the 6-µm array were analyzed for In, Au, and MoCr by x-ray (EDX) in the SEM. A 10-nm Au overcoat to avoid charging compromised Au analysis. Fig. 10 shows a typical pulled-out fingertip. The wide, flat surface to the far left is the unwetted Au film. Moving to the right, the cauliflower-textured band is In (4100 counts of the Lα1 peak) and Au (5500 counts of Mα1,2). The region further to the right, extending to the tip and narrower across the finger, is 600 counts of Mo-Lα1, 500 Au, 350 In,
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Published in Proc. 48th Electronic Components and Technology Conf.; Seattle, Washington (May, 1998); ©1998 IEEE
and 50 Cr-Kα1. All 9 pull-outs contained similar amounts of In, showing that good solder wetting was obtained in all cases. Thus, the 9 fingers pulled out because the In fractured and not because the In failed to wet these fingers. Fig. 11 shows a typical broken-off fingertip from the 6-µm array. The cauliflower region again analyzes as In-Au. The chip pads also showed no bridging of solder between pads on either array, so the resistances quoted above represent the whole daisy chain and do not involve shorts. Evaluation and Prospects The 100% soldering yield for the above arrays is promising, and further testing is underway to see how it scales for higher pincounts. Harder solders and other fluxless soldering techniques and finger metals are also being investigated. Some refractory, elastic metals are plasma etchable, and these would allow anisotropic etching that would prevent finger narrowing, thus making them less subject to the lateral deflection seen on the 6-µm pitch and probably extending the pitch capability to 3 µm. Shorter fingers could be used to increase stiffness, decrease pitch in the finger direction, and decrease series resistance, provided that chip-substrate coplanarity was sufficient so that less than 35 µm of lift and compliance was needed. Lift scales as L2/h (see Fig. 1 and ref. 2). Resistance can also be lowered by increasing the Au thickness. Because Au is much softer than MoCr, it cannot be deposited highly tensile, but on the other hand it does not seem to reduce MoCr curling very much either. Current- carrying capacity can be increased further for the high-power connections to a chip by distributing the load among many fingers around the chip, thus also reducing series-resistance losses within the chip. The fine pitch also leaves room for ground lines between every signal line for reduced crosstalk. These and/or underlying ground planes could be structured for impedance matching all the way up to the finger lift-off point, and grounded fingers could even be extended to the chip if desired. The very small chip pad area compared to conventional pads also reduces parasitic capacitance. Because of the very high compliance and elasticity of the microsprings compared to contacts used in other flip-chip technologies, they should greatly improve shock resistance and reduce thermal-fatigue failure on thermally mismatched substrates such as glass or ceramic MCMs or GaAs-based devices used for optical interconnects or laser print bars5. The transparency of glass substrates provides the advantages of simplifying alignment optics and allowing joint inspection after soldering. After full electrical testing and burn-in of an MCM, individual faulty chips could be melted off and replaced using a heated vacuum chuck on a micromanipulator without disturbing neighboring chips, because of the high thermal resistance along the fingers from the solder joints to the module substrate. This rework capability would likely represent a considerable cost savings over full KGD testing before MCM assembly. All of this could be done with the chips held only by the soldered fingers. Finally, encapsulation cans could be applied as shown in Fig. 5 to provide ruggedness, protection from contamination, and heat-sinking through fins on the can.
Conclusions We have made a preliminary demonstration of a flip-chip packaging technology that has much finer pitch and higher mechanical compliance than existing technologies. This should allow direct connection of high-density peripheral chip pads to thermally mismatched substrates without the use of fan-ins to area arrays, underfill stiffeners, or intermediate carriers. The high elasticity of the microsprings should also avoid thermal-fatigue failure when coupled with a hard solder. Fine pitch and microlithographic fabrication will allow leadout designs giving good impedance match, low crosstalk, and low parasitic inductance and capacitance. Inherent ease of rework may avoid the need for KDG testing.
Acknowledgments The authors are grateful to David Horine for enlightening discussions about packaging technology and comments on the manuscript, Bill Mosby for indium depositions, and the waferline crew for expert processing.
References 1. Lau, J. H., ed., Flip-Chip Technologies, McGraw-Hill (New York, 1996). 2. Smith, D. L., and A. S. Alimonda, “A New Flip-Chip Technology for High-Density Packaging”, Proc 46th Electronic Components and Technology Conf. (Orlando, Florida, May 1996), pp. 1069-1073. 3. Smith, D. L., and A. S. Alimonda, “Photolithographically Patterned Spring Contact”, U. S. Patent #5,613,861 (1997). [Other patents pending.] 4. Beale, J., and R. F. Pease, “Limits of High-Density, LowForce Pressure Contacts”, IEEE Trans-CPMT-A, Vol. 17, No. 2 (1994), pp. 257-262. 5. Chua, C. L., R. L. Thornton, and D. W. Treat, “Planar Laterally Oxidized Vertical-Cavity Lasers for LowThreshold High-Density Top-Surface-Emitting Arrays”, IEEE Photon. Technol. Lett., Vol. 9, No. 8 (1997), pp. 1060-1062.
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