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IEICE TRANS. ELECTRON., VOL.E89–C, NO.7 JULY 2006
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INVITED PAPER
Special Section on Heterostructure Microelectronics with TWHM2005
Future of Heterostructure Microelectronics and Roles of Materials Research for Its Progress Hideki HASEGAWA†a) , Fellow, Seiya KASAI† , Taketomo SATO† , and Tamotsu HASHIZUME† , Members
SUMMARY With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nanospace systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale. key words: heterostructure, III-V semiconductors, nanotechnology, high speed devices, sensors, smart chips
1.
Introduction
As a natural extension of the revolutionary progress of the internet and wireless technologies in the last century, we have for this century a concept of the “ubiquitous network society” where not only human beings but also various nohuman existences over the globe are going to be incorporated in various networks of networks. As another trends, we have also tremendous progresses of the nanotechnology and biotechnology. These will certainly add new features to ubiquitous networks Reflecting the above trends, new “off-roadmap” trends are rapidly emerging for device research. They include use of quantum phenomena, use of new materials such as groupIII nitrides, magnetic semiconductors, ZnO, organic semiconductors, carbon nanotubes (CNTs) etc., realization of new functions such as chemical and biological sensors and actuators, use of new system architectures [1] and formation of new wireless networks with smart chips. These trends seem to be opening up new horizon for electronics based on III-V nanostructures. The purpose of this paper is to discuss future challenges of III-V heterostructure microelectronics and related materials research in view of application for the coming ubiquitous network society. Recent activities by authors’ Manuscript received November 11, 2005. The authors are with Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo-shi, 0608628 Japan. a) E-mail: [email protected] DOI: 10.1093/ietele/e89–c.7.874 †
group at Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, are introduced as examples of efforts toward such a direction. 2.
Progress of III-V Nanotechnology
2.1 Semiconductor Nanotechnologies Traditionally, III-V electronic and photonic devices have been fabricated by the “top-down” approach similar to the Si VLSI technology, applying various film deposition and etching processes onto III-V multi-layer MBE/MOVPE wafers with the use of a suitable lithography. This approach is simple, straightforward and industrially proven for mass production. However, as the feature sizes of devices are continuously reduced deep into the nanometer region, many challenging problems emerge. On the other hand, recent explosive interests in the “nanotechnology” seem to be offering new possibilities including “bottom-up” approaches where arrays of desired nanostructures evolve from the bottom in a self-organized fashion. We believe that future new IIIV heterostructure electronics will be constructed on III-V nanostructures arrays and networks formed by a novel nanotechnology. Formation of nanostructures such as quantum wires (QWRs) and quantum dots (QDs) is the heart of the nanotechnology. Major approaches for III-V materials include; (1) direct top-down fabrication by EB lithography and etching, (2) use of imprint lithography in (1), (3) selective depletion of 2DEG by Schottky split gates, (4) selective MBE or MOVPE growth of QWRs and QDs on patterned or masked substrates, (5) self-assembled formation of QDs by Stranski-Krastanow (S-K) mode, (6) direct nanostructure formation by CVD processes, electrochemical processes and various molecular reactions, and (7) direct fabrication of nanostructures by scanned probe-induced atom manipulation and surface reaction. Each approach has its own advantages and disadvantages, depending on applications. Major critical factors to be considered include size, density, controllability of position and size, uniformity, surface smoothness, species and density of structural and electronic defects and cost and turnaround time. 2.2 Selective Epitaxial Growth of Nanostructures One of the most promising methods for future high density
c 2006 The Institute of Electronics, Information and Communication Engineers Copyright
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Fig. 1
Fig. 2 strate.
Basic principle of selective MBE growth of QWRs.
Fig. 3 Examples of nanostructure grown by selective MBE or MOVPE. (a) and (b) QD-QWR coupled structures, (c) Kagome lattice structure and (d) an array of AlGaAs nanotubes.
Basic principle of selective MOVPE growth on a masked sub-
integration of nanometer scale transport devices is the above approach (4) of selective epitaxial growth possessing position and size controllability. It combines the “top-down” and “bottom-up” approaches, as explained below. The basic principle of the selective MBE approach developed by the authors’ group [2] is shown in Fig. 1. Patterns consisting of mesa stripes with suitable orientations and side facets are formed by EB lithography and etching on (001) and (111)B GaAs, (001)InP and (0001) GaN substrates. After cleaning and removal of surface oxide, ridge structures are grown by MBE on mesa-stripes. Use of atomic hydrogen (H∗ ) for pre-growth oxide removal and for ridge growth has been found extremely useful. Then, by growing a triplelayered structure on the ridge structures by MBE, embedded nanowires with an arrow-headed or flat-top wire crosssection are formed in a self organized way due to built-in selective growth mechanism. In the case of the MOVPE version of the selective growth [3], a masked substrate is used rather than the patterned substrate, as shown in Fig. 2. Apart from this, formation of nanostructures proceeds in a similar
Fig. 4 (a) An InP-based hexagonal QWR network grown by selective MBE and (b) III-V nanostructure density vs. Si CMOS device density.
fashion. As compared with other approaches, the above methods have the following advantages; (i) sizes are smaller than lithography sizes, (ii) nanostructure boundaries are crystal facets and independent of lithography fluctuations (iii) position and size can be controlled, and (iv) nanostructures are defined by defect-free high quality heterointerfaces with steep and high potential barriers. An additional advantage of the MBE approach is that it is compatible with UHV-based processing steps and characterization techniques. In spite of apparent simplicity of the growth method, the actual growth process on non-planar substrates is complicated due to simultaneous involvement of various highindex facets and related kinetic processes. A detailed study
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has shown the importance of the facet boundary planes (FBPs) [4] in determining the position and size of nanostructures. A computer program [5] based on Einstein-Nernst equation has been successfully developed, and the size of the QWR can now be kinetically controlled down to sub10 nm region. Examples of GaAs-based and InP-based high density nanostructures grown by the MBE- and MOVPE-based selective growth methods are given in Figs. 3(a)–(d). They include arrays of QD-QWR coupled structures, and Kagome lattice structure [6] and an array of AlGaAs nanotubes [7]. An example of a hexagonal QWR network [8] is shown in Fig. 4(a) and this is for hexagonal BDD quantum LSIs explained later. Hexagon densities achieved by our selective MBE method are compared in Fig. 4(b) with reported Si CMOS transistor densities in Intel processors [9]. 3.
Future Challenges of III-V Hetero-Structure Devices and Key Material Related Issues
3.1 Communication Devices GaAs-based and InP-based compound semiconductors have very well established application areas in the communication devices similarly to their photonic counterpart. A recent “roadmap” for communication devices [10] is shown in Fig. 5. Here, abbreviations have the following meanings: ISM: industry, science, and medical, DCS: defense communications system, PCS: personal communications service, DECT: digital enhanced cordless telecommunications, LMDS: local multipoint distribution services, Contraband detection: examine cargo for illegal substances. Performances of these communication devices will further improve and their practical exploitations will further proceed. Another recent trend is the rapid progress of AlGaN/GaN heterostructure FETs (HFETs) in high power applications. The major near term application is devices for the base stations of next generation wireless communication. One figure of merit for devices for such an application is the product of the breakdown voltage and the cut-off frequency [11]. As shown in Fig. 6, GaN-based devices have the number in the range of several kV-GHz, very much surpassing those of Si LD MOSFETs, GaAs HFETs and InP
HFETs. However, surface-related problems such as the large gate leakage and the instability called current collapse seem to remain still unsolved. In this connection, we have proposed the thin surface barrier (TSB) model [12], [13] shown in Fig. 7 for gate leakage where unintentional deep donors such as those related to nitrogen vacancies as well as oxygen shallow donors [14] reduce the width of the Schottky barrier and provides leakage path by the thermionic field emission transport mechanism. Recently, the existence of lateral tunneling was found and this seems to be related to the current collapse [15]. On the other hand, the high frequency capability of GaN-based FETs is obviously an important issue. Values of the cut-off frequency, fT , reported in the literature [16]–[22] are compared in Fig. 8 for GaAs-based, InP-based and GaNbased HFETs as a function of the gate length, LG . It is seen that fT of GaN-based HFETs tends to saturate just around LG = 100 nm. One possible explanation for this anomaly is due to intrinsic effective gate length widening arising from carrier transport reflecting characteristic energy band structures of nitrides as recently indicated by simulation [23]. An alternative explanation is effective gate length widening due to lateral tunneling injection at the gate edge due to strong Fermi level pinning by surface states [15]. Clarification of this issue seems to be important for future progress of nitride HFETs. Yet another issue of a longer term nature related to the communication device is how to fill the so-called “THz gap”
Fig. 6
Fig. 5
Roadmap for communication devices.
Figure of merit of breakdown voltage times cut-off frequency.
Fig. 7
Thin surface barrier (TSB) model.
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Fig. 10 Power density trend of Si CMOS chips in comparison with the quantum limit. Fig. 8 Comparison of cut-off frequency of GaAs-based, InP-based and GaN-based HFETs as a function of gate length.
between drift plasma wave and electromagnetic space harmonics. 3.2 High Speed Digital Devices
Fig. 9
THz gap in communication devices.
as shown in Fig. 9 [24]. From the photonic device side, quantum cascade lasers have recently been successfully developed [25]. However, continuous operation at room temperature seems to be still difficult. On the other hand, from the electron device side, extrapolation of the data in Fig. 8 seems to indicate that operation in THz region by traditional HFETs is also difficult. From such a view point, recent work using a RTD is an interesting one [26]. Furthermore, it may be a time to shift from transit time devices to traveling-wave type devices, as the vacuum tubes moved to the traveling wave amplifiers. Intensive research was carried out on solid state traveling waves in the seventies of the last century when the semiconductor technology was poor. But, such research faded out long time ago. More recently, detection of THz waves by surface plasma wave in non-drift 2DEG of GaAs HFETs was demonstrated [27], [28]. Recently, authors’ group has also shown theoretically that interdigital gate HFETs can show large negative conductance at THz frequencies [29], [30] due to interaction
Back in eighties of the last century, there was big competition between Si devices and III-V devices for “future high speed devices” where the Si CMOS device has turned out to be the winner. However, the same issue seems to be coming back again. Namely, even in the main stream device technology, III-V quantum devices are mentioned in the appendix [31] of the roadmap as devices beyond the scaling limit of the Si CMOS technology. It is particularly interesting that the workers at Intel corporation are seriously investigating the InSb-based quantum well FETs as a possible candidate [32]. The issue here is the power consumption of the chip as shown in Fig. 10 for Intel processors [33]. The power density has remained remarkably constant until recently as a natural consequence of the scaling law of Si MOSFETs. However, it sharply increases towards future due to new factors such gate leakage currents by tunneling etc which are not in the scaling law. This is the reason for recent vigorous research efforts toward high-k dielectrics for which we calculated the power density from the road map [34] as shown in Fig. 10. Reduction of power density is significantly large, but not quite large enough. We can expect reduction shown by a dashed line by using the InSb QW transistors. However, the InAlSb/InSb system is still rather an exotic system and there seem to lots of surface/interface-related issues. It seems worthwhile to investigate InP-based HEMT for such applications because it which has provided the highest cut-off frequency as seen in Fig. 8. In any case, structures for high-density integration will be a challenging problem. 3.3 Sensors Reflecting the recent off-roadmap device research trends explained in the introduction, research on sensors is rapidly expanding, covering a large variety of material selection depending on which property is to be sensed. This includes
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Fig. 11
Various structures for sensing devices.
Fig. 13
Key issues for sensing mechanism.
Fig. 12 Structure and time transient characteristics of a Pt hydrogen gas sensor formed on InP.
the use of various III-V materials including nitrides with chemically stable surfaces. Here, unique features are; 1) superb electron transport properties with high surface sensitivity. 2) wide varieties of materials and material compositions, 3) availability of various heterostructures with different band line-ups, 4) advanced nanotechnology for forming nanostructures, and 5) on-chip integration with various electron devices for sense signal processing and communication. Most of the sensors reported have configurations of traditional semiconductor devices shown in Fig. 11 where changes of surface or interface potential by the property to be sensed are detected by corresponding changes in IV characteristics. Some of reported examples include 1) gas sensors using Pt and Pd on GaAs, InP, GaN and AlGaAN/GaN, 2) emerging liquid and biochemical sensors on GaAs, AlGaAs/GaAs, GaN and AlGaN [35]–[37]. As an example, a Pt hydrogen gas sensor on InP developed by authors’ group [38] is shown in Fig. 12. The sensing mechanism has been found to be interface dipole formation by atomic hydrogen produced by catalytic action of Pt. Recently, a dramatic increase of sensitivity was obtained in a Pd AlGaN/GaN hydrogen sensor [39] by reduction of leakage current on the novel surface control based of the TSB model shown in Fig. 7. Liquid sensors using AlGaN/GaN systems have also been successfully developed. The key issue for future progress is the understanding and control of surfaces and interfaces which are the key sensing parts. An example is shown in Fig. 13 [40] for an interface between semiconductor and organic molecule. Hybridization between semiconductor surface states and HOMO (highest occupied molecular orbital)-LUMO (lowest unoccupied molecular orbital) energy levels is believed to cause a dipole shift. However, exact nature and properties of the surface states in most of the III-V materials are not well-known in atomic scale.
Fig. 14 An image of a ubiquitous meme-media network incorporating IQ chips.
3.4 Smart Chips Recent revolution of internet and wireless technology has opened up possibilities of new types of wireless semiconductor chips which one might call “smart chips.” The simplest one is the RFID (radio frequency identification) chip or IC tag. A huge market is anticipated for such chips by replacing bar codes as well as by producing new type of applications. The smallest chip is now well below 1 mm2 [41]. An obvious next step is to put more functions onto the chip than a simple function of identification. Toward this aim, various efforts are now being made including with the smart dust [42] and the Si “mote” for sensor networks [43]. Authors’ group is also developing at Hokkaido University what we call intelligent quantum (IQ) chip [44]. As shown in Fig. 14, an IQ chip is a III-V semiconductor chip where nanometer scale processors and memories are integrated on a chip with capabilities of wireless communication, wireless power supply and various sensing functions.
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Fig. 16
Fig. 15
Basic concept of the hexagonal BDD quantum circuit.
Power consumption requirement for smart chips.
It is an attempt to realize tiny “knowledge vehicles” to be embedded anywhere in the society, as schematically shown in Fig. 14, or even within living species. One problem for realization of smart chips is power consumption as shown in Fig. 15. It indicates that the total power consumption of the chip including logic, memory, communication and sensors should well below 10 mW. Thus, from the trend shown in Fig. 10, use of Si CMOS technology is not a good choice. On the other hand, the energydelay time product of a quantum device, can, in principle, be reduced down to the Planck’s constant, h. Thus, use of quantum devices should lead to large reduction of power density as shown by a dashed horizontal line for the case of 1010 devices/cm2 operating at 10 GHz clock frequency. If the clock rate is smaller, power density will be further reduced. This is the reason why we try to develop ultra-low power quantum LSIs as explained in the next section. 3.5 Ultra-Low Power Quantum LSIs A recent progress of the semiconductor nanotechnology, has shown that quantum devices such as single electron transistors (SETs) operating at room temperature can be fabricated [45], solving a “traditional problem” of quantum devices. However, there is another problem which makes their large scale integration extremely difficult. Namely, quantum devices have poor current driving capability and poor threshold control due to low-current quantum transport which is extremely structure- and charge-sensitive. Thus, they are totally unsuitable to the conventional “logic gate architecture.” To solve above problem, authors’ group has recently proposed a novel hexagonal binary-decision diagram (BDD) quantum circuit approach [46]–[48] shown in Fig. 16. Here, path switching node devices based on quantum transport are formed on III-V hexagonal nanowire networks realize arbitrary combinational logic functions. Feasibility of the approach has already been demonstrated by using the node devices shown in Fig. 17(a) controlled by nanometer scale Schottky wrap gates (WPGs) shown in Fig. 17(b). Basic node devices and various small-scale circuits including a 2bit adder circuit shown in Fig. 17(c) [49] were fabricated. For higher density integration and larger scale circuits, we
Fig. 17 (a) BDD node devices, (b) Schottky WPG structures and (c) SEM image of a BDD 2bit adder.
will use the network grown by selective MBE as already explained. Such quantum LSIs will become brains of our IQ chips and brains of other nano-space systems. The key processing issue for quantum LSIs is the control of surfaces and interfaces of nanostructures in atomic scale. Removal of surface states in III-V materials is a well-known difficult problem. In order to overcome this problem, authors’ group has been making intensive efforts to understand and control surface states on (001)-oriented GaAs, InP and GaN, using various techniques including UHV STM/STS, contactless C-V, PL and XPS techniques. We recently have found that use of the Si ICL structure [50] shown Fig. 18(a) under an appropriate surface condi-
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become brains of smart chips and other nano-space systems. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale. Acknowledgments The work reported here is supported by the 21st Century COE Project at Hokkaido University on “MemeMedia Technology Approach to the R&D of NextGeneration Information Technologies (Project Leader Professor Y. Tanaka)” from MEXT, Japan. The authors would also like to express their thanks to Professors T. Fukui, J. Motohisa and E. Sano at RCIQE, Hokkaido University, for their useful discussion and for providing materials to be included here. References Fig. 18 (a) Concept of Si-ICL passivation, (b) structure of GaAs QWR and (c) effect of Si ICL on photoluminescence from aGaAs QWRs.
tion reduces surface state density dramatically, as shown by the photoluminescence data on a GaAs QWR sample in Figs. 18(b) and (c) [51]. Finally, another important application of low-power quantum LSI is the so-called quantum computer with unprecedented computational power derived from the massive parallelism involved in the basic principle of the quantum mechanics. In the above BDD circuit, quantum devices are used as dissipative switches where quantum coherence is maintained just within the active part of the device. On the other hand, quantum coherence should be maintained over the entire circuit operation for quantum computing [52]. Thus, increase of the coherence time is one of the most important issues. In order to realize a quantum computer in a solid-state semiconductor form, efforts such as utilizing nuclear spins in Si [53], utilizing spin states in coupled III-V QDs [54] and many others are going. Although the state of the art is still very much far away from its practical exploitation, it is the ultimate goal of the semiconductor nanotechnology, and thus, the long term research should be supported and continued. 4.
Conclusion
We discussed in this paper, the future of the heterostructure microelectronics from the view point of nanoelectronics. With advent of the ubiquitous network era and progress of III-V nanotechnology, III-V nanoelectronics has great future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V nanoelectronics will be formed on nanostructure networks formed by combining top-down and bottom-up approaches. In addition to communication devices, high speed digital LSIs, various sensors and various smart-chips are main application areas. Ultra-low power quantum LSIs may
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A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor applications,” IEEE Trans. Nanotech., vol.4, pp.153–158, 2005. P.P. Gelsigner, Tech. Dig. of 2001 ISSCC, IEEE Press, Piscataway, NJ, pp.22–25, 2001. International Technology Roadmap for Semi-conductors: http:// public.itrs.net/ S.M. Luber, K. Adlkofer, U. Rant, A. Ulman, A. Golzhauser, M. Grunze, D. Schuh, M. Tanaka, M. Tornow, and G. Abstreiter, “Liquid phase sensors based on chemically functionalized GaAs/AlGaAs heterostructures,” Physica E, vol.21, pp.1111–1115, 2004. A. Stutzmann, G. Steinhoff, M. Eickhoff, O. Ambacher, C.E. Nebel, J. Schalwig, R. Neuberger, and G. Muller, “GaN-based heterostructures for sensor applications,” Diam. Relat. Mater., vol.11, pp.886– 891, 2002. G. Steinhoff, M. Hermann, W.J. Schaff, L.F. Eastman, M. Stutzmann, and M. Eickhoff, “pH response of GaN surfaces and its application for pH-sensitive field-effect transistors,” Appl. Phys. Lett., vol.83, pp.177–179, 2003. T. Kimura, H. Hasegawa, T. Sato, and T. Hashizume, “Sensing mechanism of InP hydrogen sensors using Pt Schottky diodes formed by electrochemical process,” 2005 Int. Conf. Solid-State Devices and Materials (SSDM), Kobe, Japan, Extended Abstract, pp.218–219, Sept. 2005. K. Matsuo, T. Kimura, H. Hasegawa, and T. Hashizume, “Hydrogen response of Pd Schottky diodes formed on AlGaN/GaN heterostructure,” 2005 International Symposium on Surface Science and Nanotechnology (ISSS-4), Saitama, Japan, We-A24, Nov. 2005. A. Vilan and D. Cahen, “How organic molecules can control electronic devices,” Trends Biotechnology, vol.20, pp.22–29, 2002. M. Usami and M. Ohki, “The µ-chip: An ultra-small 2.45 GHz RFID chip for ubiquitous recognition application,” IEICE Trans. Electron., vol.E86-C, no.4, pp.521–528, 2003. See web site, http://www-bsac.eecs.berkeley.edu/archive/users/warneke-brett/SmartDust/ Intel web site, http://www.intel.co.jp/research/exploratory/wireless sensors.htm IQ chip in 21st Century COE project of Hokkaido Univ.: http://www.rciqe.hokudai.ac.jp M. Saitoh, T. Murakami, and T. Hiramoto, “Large Coulomb blockade oscillations at room temperature in ultra-narrow wire channel MOSFETs formed by slight oxidation process,” IEEE Trans. Nanotech., vol.2, pp.241–245, 2003. H. Hasegawa and S. Kasai, “Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires,” Physica E, vol.11, pp.149– 154, 2001. S. Kasai and H. Hasegawa, “A single electron binary-decisiondiagram quantum logic circuit based on Schottky wrap gate control of a GaAs nanowire hexagon,” IEEE Electron Device Lett., vol.23, pp.446–448, 2002. H. Hasegawa, S. Kasai, and T. Sato, “Hexagonal binary decision diagram quantum circuit approach for ultra-low power III-V quantum LSIs,” IEICE Trans. Electron., vol.E87-C, no.11, pp.1757–1768, 2004. S. Kasai, M. Yumoto, and H. Hasegawa, “Fabrication of GaAs-based integrated half and full adders by novel hexagonal BDD quantum circuit approach,” Solid State Electron., vol.47, pp.199–204, 2003. H. Hasegawa, “MBE growth and applications of silicon interface control layers,” Thin Solid Films, vol.367, pp.58–67, 2000. N. Shiozaki, T. Sato, and H. Hasegawa, “Effects of surface states and Si-interlayer based surface passivation on GaAs quantum wires grown by selective molecular beam epitaxy,” J. Vac. Sci. Technol. B, vol.23, pp.1714–1721, 2005. D. Lossand and D.P. DiVincenzo, “Quantum computation with quantum dots,” Phys. Rev. A, vol.57, pp.120–126, 1998. B.E. Kane, “A silicon-based nuclear spin quantum computer,” Na-
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ture, vol.393, pp.133–137, 1998. [54] T.H. Oosterkamp, T. Fujisawa, W.G. van der Wiel, K. Ishibashi, R.V. Hijman, S. Tarucha, and L.P. Kouwenhoven, “Microwave spectroscopy on a quantum-dot molecule,” Nature, vol.395, pp.873–876, 1998.
Hideki Hasegawa was born in Tokyo in June 22, 1941. He received B.E., M.E. and Ph.D. degrees in electronic engineering from University of Tokyo, Japan, in 1964, 1966 and 1970, respectively. He became Lecturer, Associate Professor and Professor in the Department of Electrical Engineering, Hokkaido University in 1970, 1971 and 1980, respectively. Later, he served as a Professor in Graduate School of Electronics, and that in Graduate School of Information Science and Technology, Hokkaido University. In 1991, he founded a Research Center for Interface Quantum Electronics (RCIQE) in Hokkaido University, and served as Director for 1991–2001. In 2001, the Center was reorganized as the Center as Research Center for Integrated Quantum Electronics (RCIQE), and he served as Director for 2001–2005. Since April, 2005, he has become a Professor Emeritus of Hokkaido University, and has been serving as a COE (Center of Excellence) Visiting Professor at RCIQE. His research interests include molecular beam epitaxial growth, characterization and processing of III-V compound semiconductor quantum nanostructures, and their applications to quantum devices and quantum LSIs. He has authored or co-authored more than 450 publications in major technical journals. He received the Journal Paper Award from the Japan Society of Applied Physics in 1982, the Max-Planck Research Award from Max-Planck Society and Alexander Humbolt Foundation, Germany, in 1991, Michael Lunn Award from International Conference on Indium Phosphide and Related Materials (IPRM) in 2003, respectively. He is a member of the Institute of Electrical and Electronics Engineers (IEEE), Japan Society of Applied Physics (JSAP) and other academic societies.
Seiya Kasai was born in Hokkaido on April, 1969. He received B.E., M.E. and Ph.D. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1992, 1994 and 1997, respectively. He joined Optoelectronics and High Frequency Device Research Laboratories, NEC, Japan, in 1997. In 1999, he moved to Graduate School of Electronics and Information Engineering, Hokkaido University, as a Research Associate and he has been an Associate Professor since 2001. From 2004, he has been an Associate Professor in Graduate School of Information Science and Technology and Research Center for Integrated Quantum Electronics (RCIQE). His current research interests include quantum nano-devices and their integrations and high-speed devices. He is a member of IEICE and the Japan Society of Applied Physics (JSAP).
Taketomo Sato was born in Tokyo in June, 1973. He received B.E. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1996. Then, he received M.S. and Ph.D. degrees in Electronics and Information Engineering from Hokkaido University, Japan, in 1998 and 2001, respectively. In 2001, he joined Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, as a postdoctoral researcher, and in the same year, moved to Graduate School of Electronics and Information Engineering, Hokkaido University, as a Research Associate. Since 2004, he has been an Associate Professor of RCIQE, Hokkaido University. His current research interests include fabrication of III-V nanostructures using selective MBE growth techniques. He has received a Presentation Encouragement Award of Japan Society of Applied Physics in 2000. He is a member of the Japan Society of Applied Physics (JSAP).
Tamotsu Hashizume was born in Hokkaido in June, 1956. He received B.E. and Ph.D. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1981 and 1991, respectively. He became Research Associate of Kushiro National College of Technology in 1981. Then he moved to the Department of Electrical Engineering, Hokkaido Polytechnic College, as Lecturer, in 1987. In 1994, he moved to the Graduate School of Electronics and Information Engineering, Hokkaido University, as Associate Professor. Since 2004, he has been a Professor of Research Center for Integrated Quantum Electronics, Hokkaido University. His research interests included surface passivation and device processing technologies for III-V compound semiconductors. Currently, his major activity expanded into characterization and control of surfaces and interfaces of GaN and related materials and their application to electronic devices. He has authored or co-authored over 100 papers in scientific and technical journals. He is a member of the Japan Society of Applied Physics and the Surface Science Society of Japan.
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INVITED PAPER
Special Section on Heterostructure Microelectronics with TWHM2005
Future of Heterostructure Microelectronics and Roles of Materials Research for Its Progress Hideki HASEGAWA†a) , Fellow, Seiya KASAI† , Taketomo SATO† , and Tamotsu HASHIZUME† , Members
SUMMARY With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nanospace systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale. key words: heterostructure, III-V semiconductors, nanotechnology, high speed devices, sensors, smart chips
1.
Introduction
As a natural extension of the revolutionary progress of the internet and wireless technologies in the last century, we have for this century a concept of the “ubiquitous network society” where not only human beings but also various nohuman existences over the globe are going to be incorporated in various networks of networks. As another trends, we have also tremendous progresses of the nanotechnology and biotechnology. These will certainly add new features to ubiquitous networks Reflecting the above trends, new “off-roadmap” trends are rapidly emerging for device research. They include use of quantum phenomena, use of new materials such as groupIII nitrides, magnetic semiconductors, ZnO, organic semiconductors, carbon nanotubes (CNTs) etc., realization of new functions such as chemical and biological sensors and actuators, use of new system architectures [1] and formation of new wireless networks with smart chips. These trends seem to be opening up new horizon for electronics based on III-V nanostructures. The purpose of this paper is to discuss future challenges of III-V heterostructure microelectronics and related materials research in view of application for the coming ubiquitous network society. Recent activities by authors’ Manuscript received November 11, 2005. The authors are with Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo-shi, 0608628 Japan. a) E-mail: [email protected] DOI: 10.1093/ietele/e89–c.7.874 †
group at Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, are introduced as examples of efforts toward such a direction. 2.
Progress of III-V Nanotechnology
2.1 Semiconductor Nanotechnologies Traditionally, III-V electronic and photonic devices have been fabricated by the “top-down” approach similar to the Si VLSI technology, applying various film deposition and etching processes onto III-V multi-layer MBE/MOVPE wafers with the use of a suitable lithography. This approach is simple, straightforward and industrially proven for mass production. However, as the feature sizes of devices are continuously reduced deep into the nanometer region, many challenging problems emerge. On the other hand, recent explosive interests in the “nanotechnology” seem to be offering new possibilities including “bottom-up” approaches where arrays of desired nanostructures evolve from the bottom in a self-organized fashion. We believe that future new IIIV heterostructure electronics will be constructed on III-V nanostructures arrays and networks formed by a novel nanotechnology. Formation of nanostructures such as quantum wires (QWRs) and quantum dots (QDs) is the heart of the nanotechnology. Major approaches for III-V materials include; (1) direct top-down fabrication by EB lithography and etching, (2) use of imprint lithography in (1), (3) selective depletion of 2DEG by Schottky split gates, (4) selective MBE or MOVPE growth of QWRs and QDs on patterned or masked substrates, (5) self-assembled formation of QDs by Stranski-Krastanow (S-K) mode, (6) direct nanostructure formation by CVD processes, electrochemical processes and various molecular reactions, and (7) direct fabrication of nanostructures by scanned probe-induced atom manipulation and surface reaction. Each approach has its own advantages and disadvantages, depending on applications. Major critical factors to be considered include size, density, controllability of position and size, uniformity, surface smoothness, species and density of structural and electronic defects and cost and turnaround time. 2.2 Selective Epitaxial Growth of Nanostructures One of the most promising methods for future high density
c 2006 The Institute of Electronics, Information and Communication Engineers Copyright
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Fig. 1
Fig. 2 strate.
Basic principle of selective MBE growth of QWRs.
Fig. 3 Examples of nanostructure grown by selective MBE or MOVPE. (a) and (b) QD-QWR coupled structures, (c) Kagome lattice structure and (d) an array of AlGaAs nanotubes.
Basic principle of selective MOVPE growth on a masked sub-
integration of nanometer scale transport devices is the above approach (4) of selective epitaxial growth possessing position and size controllability. It combines the “top-down” and “bottom-up” approaches, as explained below. The basic principle of the selective MBE approach developed by the authors’ group [2] is shown in Fig. 1. Patterns consisting of mesa stripes with suitable orientations and side facets are formed by EB lithography and etching on (001) and (111)B GaAs, (001)InP and (0001) GaN substrates. After cleaning and removal of surface oxide, ridge structures are grown by MBE on mesa-stripes. Use of atomic hydrogen (H∗ ) for pre-growth oxide removal and for ridge growth has been found extremely useful. Then, by growing a triplelayered structure on the ridge structures by MBE, embedded nanowires with an arrow-headed or flat-top wire crosssection are formed in a self organized way due to built-in selective growth mechanism. In the case of the MOVPE version of the selective growth [3], a masked substrate is used rather than the patterned substrate, as shown in Fig. 2. Apart from this, formation of nanostructures proceeds in a similar
Fig. 4 (a) An InP-based hexagonal QWR network grown by selective MBE and (b) III-V nanostructure density vs. Si CMOS device density.
fashion. As compared with other approaches, the above methods have the following advantages; (i) sizes are smaller than lithography sizes, (ii) nanostructure boundaries are crystal facets and independent of lithography fluctuations (iii) position and size can be controlled, and (iv) nanostructures are defined by defect-free high quality heterointerfaces with steep and high potential barriers. An additional advantage of the MBE approach is that it is compatible with UHV-based processing steps and characterization techniques. In spite of apparent simplicity of the growth method, the actual growth process on non-planar substrates is complicated due to simultaneous involvement of various highindex facets and related kinetic processes. A detailed study
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has shown the importance of the facet boundary planes (FBPs) [4] in determining the position and size of nanostructures. A computer program [5] based on Einstein-Nernst equation has been successfully developed, and the size of the QWR can now be kinetically controlled down to sub10 nm region. Examples of GaAs-based and InP-based high density nanostructures grown by the MBE- and MOVPE-based selective growth methods are given in Figs. 3(a)–(d). They include arrays of QD-QWR coupled structures, and Kagome lattice structure [6] and an array of AlGaAs nanotubes [7]. An example of a hexagonal QWR network [8] is shown in Fig. 4(a) and this is for hexagonal BDD quantum LSIs explained later. Hexagon densities achieved by our selective MBE method are compared in Fig. 4(b) with reported Si CMOS transistor densities in Intel processors [9]. 3.
Future Challenges of III-V Hetero-Structure Devices and Key Material Related Issues
3.1 Communication Devices GaAs-based and InP-based compound semiconductors have very well established application areas in the communication devices similarly to their photonic counterpart. A recent “roadmap” for communication devices [10] is shown in Fig. 5. Here, abbreviations have the following meanings: ISM: industry, science, and medical, DCS: defense communications system, PCS: personal communications service, DECT: digital enhanced cordless telecommunications, LMDS: local multipoint distribution services, Contraband detection: examine cargo for illegal substances. Performances of these communication devices will further improve and their practical exploitations will further proceed. Another recent trend is the rapid progress of AlGaN/GaN heterostructure FETs (HFETs) in high power applications. The major near term application is devices for the base stations of next generation wireless communication. One figure of merit for devices for such an application is the product of the breakdown voltage and the cut-off frequency [11]. As shown in Fig. 6, GaN-based devices have the number in the range of several kV-GHz, very much surpassing those of Si LD MOSFETs, GaAs HFETs and InP
HFETs. However, surface-related problems such as the large gate leakage and the instability called current collapse seem to remain still unsolved. In this connection, we have proposed the thin surface barrier (TSB) model [12], [13] shown in Fig. 7 for gate leakage where unintentional deep donors such as those related to nitrogen vacancies as well as oxygen shallow donors [14] reduce the width of the Schottky barrier and provides leakage path by the thermionic field emission transport mechanism. Recently, the existence of lateral tunneling was found and this seems to be related to the current collapse [15]. On the other hand, the high frequency capability of GaN-based FETs is obviously an important issue. Values of the cut-off frequency, fT , reported in the literature [16]–[22] are compared in Fig. 8 for GaAs-based, InP-based and GaNbased HFETs as a function of the gate length, LG . It is seen that fT of GaN-based HFETs tends to saturate just around LG = 100 nm. One possible explanation for this anomaly is due to intrinsic effective gate length widening arising from carrier transport reflecting characteristic energy band structures of nitrides as recently indicated by simulation [23]. An alternative explanation is effective gate length widening due to lateral tunneling injection at the gate edge due to strong Fermi level pinning by surface states [15]. Clarification of this issue seems to be important for future progress of nitride HFETs. Yet another issue of a longer term nature related to the communication device is how to fill the so-called “THz gap”
Fig. 6
Fig. 5
Roadmap for communication devices.
Figure of merit of breakdown voltage times cut-off frequency.
Fig. 7
Thin surface barrier (TSB) model.
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Fig. 10 Power density trend of Si CMOS chips in comparison with the quantum limit. Fig. 8 Comparison of cut-off frequency of GaAs-based, InP-based and GaN-based HFETs as a function of gate length.
between drift plasma wave and electromagnetic space harmonics. 3.2 High Speed Digital Devices
Fig. 9
THz gap in communication devices.
as shown in Fig. 9 [24]. From the photonic device side, quantum cascade lasers have recently been successfully developed [25]. However, continuous operation at room temperature seems to be still difficult. On the other hand, from the electron device side, extrapolation of the data in Fig. 8 seems to indicate that operation in THz region by traditional HFETs is also difficult. From such a view point, recent work using a RTD is an interesting one [26]. Furthermore, it may be a time to shift from transit time devices to traveling-wave type devices, as the vacuum tubes moved to the traveling wave amplifiers. Intensive research was carried out on solid state traveling waves in the seventies of the last century when the semiconductor technology was poor. But, such research faded out long time ago. More recently, detection of THz waves by surface plasma wave in non-drift 2DEG of GaAs HFETs was demonstrated [27], [28]. Recently, authors’ group has also shown theoretically that interdigital gate HFETs can show large negative conductance at THz frequencies [29], [30] due to interaction
Back in eighties of the last century, there was big competition between Si devices and III-V devices for “future high speed devices” where the Si CMOS device has turned out to be the winner. However, the same issue seems to be coming back again. Namely, even in the main stream device technology, III-V quantum devices are mentioned in the appendix [31] of the roadmap as devices beyond the scaling limit of the Si CMOS technology. It is particularly interesting that the workers at Intel corporation are seriously investigating the InSb-based quantum well FETs as a possible candidate [32]. The issue here is the power consumption of the chip as shown in Fig. 10 for Intel processors [33]. The power density has remained remarkably constant until recently as a natural consequence of the scaling law of Si MOSFETs. However, it sharply increases towards future due to new factors such gate leakage currents by tunneling etc which are not in the scaling law. This is the reason for recent vigorous research efforts toward high-k dielectrics for which we calculated the power density from the road map [34] as shown in Fig. 10. Reduction of power density is significantly large, but not quite large enough. We can expect reduction shown by a dashed line by using the InSb QW transistors. However, the InAlSb/InSb system is still rather an exotic system and there seem to lots of surface/interface-related issues. It seems worthwhile to investigate InP-based HEMT for such applications because it which has provided the highest cut-off frequency as seen in Fig. 8. In any case, structures for high-density integration will be a challenging problem. 3.3 Sensors Reflecting the recent off-roadmap device research trends explained in the introduction, research on sensors is rapidly expanding, covering a large variety of material selection depending on which property is to be sensed. This includes
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Fig. 11
Various structures for sensing devices.
Fig. 13
Key issues for sensing mechanism.
Fig. 12 Structure and time transient characteristics of a Pt hydrogen gas sensor formed on InP.
the use of various III-V materials including nitrides with chemically stable surfaces. Here, unique features are; 1) superb electron transport properties with high surface sensitivity. 2) wide varieties of materials and material compositions, 3) availability of various heterostructures with different band line-ups, 4) advanced nanotechnology for forming nanostructures, and 5) on-chip integration with various electron devices for sense signal processing and communication. Most of the sensors reported have configurations of traditional semiconductor devices shown in Fig. 11 where changes of surface or interface potential by the property to be sensed are detected by corresponding changes in IV characteristics. Some of reported examples include 1) gas sensors using Pt and Pd on GaAs, InP, GaN and AlGaAN/GaN, 2) emerging liquid and biochemical sensors on GaAs, AlGaAs/GaAs, GaN and AlGaN [35]–[37]. As an example, a Pt hydrogen gas sensor on InP developed by authors’ group [38] is shown in Fig. 12. The sensing mechanism has been found to be interface dipole formation by atomic hydrogen produced by catalytic action of Pt. Recently, a dramatic increase of sensitivity was obtained in a Pd AlGaN/GaN hydrogen sensor [39] by reduction of leakage current on the novel surface control based of the TSB model shown in Fig. 7. Liquid sensors using AlGaN/GaN systems have also been successfully developed. The key issue for future progress is the understanding and control of surfaces and interfaces which are the key sensing parts. An example is shown in Fig. 13 [40] for an interface between semiconductor and organic molecule. Hybridization between semiconductor surface states and HOMO (highest occupied molecular orbital)-LUMO (lowest unoccupied molecular orbital) energy levels is believed to cause a dipole shift. However, exact nature and properties of the surface states in most of the III-V materials are not well-known in atomic scale.
Fig. 14 An image of a ubiquitous meme-media network incorporating IQ chips.
3.4 Smart Chips Recent revolution of internet and wireless technology has opened up possibilities of new types of wireless semiconductor chips which one might call “smart chips.” The simplest one is the RFID (radio frequency identification) chip or IC tag. A huge market is anticipated for such chips by replacing bar codes as well as by producing new type of applications. The smallest chip is now well below 1 mm2 [41]. An obvious next step is to put more functions onto the chip than a simple function of identification. Toward this aim, various efforts are now being made including with the smart dust [42] and the Si “mote” for sensor networks [43]. Authors’ group is also developing at Hokkaido University what we call intelligent quantum (IQ) chip [44]. As shown in Fig. 14, an IQ chip is a III-V semiconductor chip where nanometer scale processors and memories are integrated on a chip with capabilities of wireless communication, wireless power supply and various sensing functions.
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Fig. 16
Fig. 15
Basic concept of the hexagonal BDD quantum circuit.
Power consumption requirement for smart chips.
It is an attempt to realize tiny “knowledge vehicles” to be embedded anywhere in the society, as schematically shown in Fig. 14, or even within living species. One problem for realization of smart chips is power consumption as shown in Fig. 15. It indicates that the total power consumption of the chip including logic, memory, communication and sensors should well below 10 mW. Thus, from the trend shown in Fig. 10, use of Si CMOS technology is not a good choice. On the other hand, the energydelay time product of a quantum device, can, in principle, be reduced down to the Planck’s constant, h. Thus, use of quantum devices should lead to large reduction of power density as shown by a dashed horizontal line for the case of 1010 devices/cm2 operating at 10 GHz clock frequency. If the clock rate is smaller, power density will be further reduced. This is the reason why we try to develop ultra-low power quantum LSIs as explained in the next section. 3.5 Ultra-Low Power Quantum LSIs A recent progress of the semiconductor nanotechnology, has shown that quantum devices such as single electron transistors (SETs) operating at room temperature can be fabricated [45], solving a “traditional problem” of quantum devices. However, there is another problem which makes their large scale integration extremely difficult. Namely, quantum devices have poor current driving capability and poor threshold control due to low-current quantum transport which is extremely structure- and charge-sensitive. Thus, they are totally unsuitable to the conventional “logic gate architecture.” To solve above problem, authors’ group has recently proposed a novel hexagonal binary-decision diagram (BDD) quantum circuit approach [46]–[48] shown in Fig. 16. Here, path switching node devices based on quantum transport are formed on III-V hexagonal nanowire networks realize arbitrary combinational logic functions. Feasibility of the approach has already been demonstrated by using the node devices shown in Fig. 17(a) controlled by nanometer scale Schottky wrap gates (WPGs) shown in Fig. 17(b). Basic node devices and various small-scale circuits including a 2bit adder circuit shown in Fig. 17(c) [49] were fabricated. For higher density integration and larger scale circuits, we
Fig. 17 (a) BDD node devices, (b) Schottky WPG structures and (c) SEM image of a BDD 2bit adder.
will use the network grown by selective MBE as already explained. Such quantum LSIs will become brains of our IQ chips and brains of other nano-space systems. The key processing issue for quantum LSIs is the control of surfaces and interfaces of nanostructures in atomic scale. Removal of surface states in III-V materials is a well-known difficult problem. In order to overcome this problem, authors’ group has been making intensive efforts to understand and control surface states on (001)-oriented GaAs, InP and GaN, using various techniques including UHV STM/STS, contactless C-V, PL and XPS techniques. We recently have found that use of the Si ICL structure [50] shown Fig. 18(a) under an appropriate surface condi-
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become brains of smart chips and other nano-space systems. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale. Acknowledgments The work reported here is supported by the 21st Century COE Project at Hokkaido University on “MemeMedia Technology Approach to the R&D of NextGeneration Information Technologies (Project Leader Professor Y. Tanaka)” from MEXT, Japan. The authors would also like to express their thanks to Professors T. Fukui, J. Motohisa and E. Sano at RCIQE, Hokkaido University, for their useful discussion and for providing materials to be included here. References Fig. 18 (a) Concept of Si-ICL passivation, (b) structure of GaAs QWR and (c) effect of Si ICL on photoluminescence from aGaAs QWRs.
tion reduces surface state density dramatically, as shown by the photoluminescence data on a GaAs QWR sample in Figs. 18(b) and (c) [51]. Finally, another important application of low-power quantum LSI is the so-called quantum computer with unprecedented computational power derived from the massive parallelism involved in the basic principle of the quantum mechanics. In the above BDD circuit, quantum devices are used as dissipative switches where quantum coherence is maintained just within the active part of the device. On the other hand, quantum coherence should be maintained over the entire circuit operation for quantum computing [52]. Thus, increase of the coherence time is one of the most important issues. In order to realize a quantum computer in a solid-state semiconductor form, efforts such as utilizing nuclear spins in Si [53], utilizing spin states in coupled III-V QDs [54] and many others are going. Although the state of the art is still very much far away from its practical exploitation, it is the ultimate goal of the semiconductor nanotechnology, and thus, the long term research should be supported and continued. 4.
Conclusion
We discussed in this paper, the future of the heterostructure microelectronics from the view point of nanoelectronics. With advent of the ubiquitous network era and progress of III-V nanotechnology, III-V nanoelectronics has great future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V nanoelectronics will be formed on nanostructure networks formed by combining top-down and bottom-up approaches. In addition to communication devices, high speed digital LSIs, various sensors and various smart-chips are main application areas. Ultra-low power quantum LSIs may
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Hideki Hasegawa was born in Tokyo in June 22, 1941. He received B.E., M.E. and Ph.D. degrees in electronic engineering from University of Tokyo, Japan, in 1964, 1966 and 1970, respectively. He became Lecturer, Associate Professor and Professor in the Department of Electrical Engineering, Hokkaido University in 1970, 1971 and 1980, respectively. Later, he served as a Professor in Graduate School of Electronics, and that in Graduate School of Information Science and Technology, Hokkaido University. In 1991, he founded a Research Center for Interface Quantum Electronics (RCIQE) in Hokkaido University, and served as Director for 1991–2001. In 2001, the Center was reorganized as the Center as Research Center for Integrated Quantum Electronics (RCIQE), and he served as Director for 2001–2005. Since April, 2005, he has become a Professor Emeritus of Hokkaido University, and has been serving as a COE (Center of Excellence) Visiting Professor at RCIQE. His research interests include molecular beam epitaxial growth, characterization and processing of III-V compound semiconductor quantum nanostructures, and their applications to quantum devices and quantum LSIs. He has authored or co-authored more than 450 publications in major technical journals. He received the Journal Paper Award from the Japan Society of Applied Physics in 1982, the Max-Planck Research Award from Max-Planck Society and Alexander Humbolt Foundation, Germany, in 1991, Michael Lunn Award from International Conference on Indium Phosphide and Related Materials (IPRM) in 2003, respectively. He is a member of the Institute of Electrical and Electronics Engineers (IEEE), Japan Society of Applied Physics (JSAP) and other academic societies.
Seiya Kasai was born in Hokkaido on April, 1969. He received B.E., M.E. and Ph.D. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1992, 1994 and 1997, respectively. He joined Optoelectronics and High Frequency Device Research Laboratories, NEC, Japan, in 1997. In 1999, he moved to Graduate School of Electronics and Information Engineering, Hokkaido University, as a Research Associate and he has been an Associate Professor since 2001. From 2004, he has been an Associate Professor in Graduate School of Information Science and Technology and Research Center for Integrated Quantum Electronics (RCIQE). His current research interests include quantum nano-devices and their integrations and high-speed devices. He is a member of IEICE and the Japan Society of Applied Physics (JSAP).
Taketomo Sato was born in Tokyo in June, 1973. He received B.E. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1996. Then, he received M.S. and Ph.D. degrees in Electronics and Information Engineering from Hokkaido University, Japan, in 1998 and 2001, respectively. In 2001, he joined Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, as a postdoctoral researcher, and in the same year, moved to Graduate School of Electronics and Information Engineering, Hokkaido University, as a Research Associate. Since 2004, he has been an Associate Professor of RCIQE, Hokkaido University. His current research interests include fabrication of III-V nanostructures using selective MBE growth techniques. He has received a Presentation Encouragement Award of Japan Society of Applied Physics in 2000. He is a member of the Japan Society of Applied Physics (JSAP).
Tamotsu Hashizume was born in Hokkaido in June, 1956. He received B.E. and Ph.D. degrees in electrical engineering from Hokkaido University, Hokkaido, Japan, in 1981 and 1991, respectively. He became Research Associate of Kushiro National College of Technology in 1981. Then he moved to the Department of Electrical Engineering, Hokkaido Polytechnic College, as Lecturer, in 1987. In 1994, he moved to the Graduate School of Electronics and Information Engineering, Hokkaido University, as Associate Professor. Since 2004, he has been a Professor of Research Center for Integrated Quantum Electronics, Hokkaido University. His research interests included surface passivation and device processing technologies for III-V compound semiconductors. Currently, his major activity expanded into characterization and control of surfaces and interfaces of GaN and related materials and their application to electronic devices. He has authored or co-authored over 100 papers in scientific and technical journals. He is a member of the Japan Society of Applied Physics and the Surface Science Society of Japan.
