Graphene-MoS2 Hybrid Technology for Large-Scale Two ...
Supporting information
Graphene-MoS2 Hybrid Technology for Large-Scale TwoDimensional Electronics ⊥
Lili Yu1*, Yi-Hsien Lee2, Xi Ling1, Elton J.G. Santos3, , Yong Cheol Shin4, Yuxuan Lin1, Madan Dubey5, Efthimios Kaxiras3,6, Jing Kong1, Han Wang1*, and Tomás Palacios1* 1
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 77
Massachusetts Avenue, Cambridge, MA 02139, USA. 2
Materials Science and Engineering, National Tsing-Hua University, Hsinchu, 30013, Taiwan
School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA
3 4
Department of Materials Science and Engineering, Massachusetts Institute of Technology, 77 Massachusetts
Avenue, Cambridge, MA 02139, USA. 5
United States Army Research Laboratory, 2800 Powder Mill Road, Adelphi, Maryland 20783-1197, United
States 6
Department of Physics, Harvard University, Cambridge, MA 02138, USA
⊥
Present address: Department of Chemical Engineering, Stanford University, Stanford, California
94305, United States, SLAC National Accelerator Laboratory, SUNCAT Center for Interface Science and Catalysis, Menlo Park, California 94025, United States
Corresponding author E-mail: [email protected], [email protected], [email protected]
1
CVD growth of MoS2
Figure S1. (a) Schematic setup for CVD growth of single layer MoS2. (b) Optical micrograph of as-grown CVD MoS2 at different locations. (c) AFM image and height profile of isolated triangle of MoS2 from right image of Figure S1 (b). Large-area single layer MoS2 was grown on 300 nm SiO2/Si substrate for large-scale electronics. The growth of MoS2 monolayers was initiated with the seeding of PTAS on substrate surfaces. A high solubility of PTAS in deionized (DI) water enables a uniform distribution of the seeds on the hydrophilic substrate surfaces. Uniform but small PTAS are precipitated on the surfaces after drying the water. The treated substrates are mounted up-side down in a growth furnace, the schematic set-up of which is shown in Figure S1. 2
The MoO3 powders (0.03g) and S powders (0.01g) were placed in different crucibles. The optimized distance of MoO3 and S crucible is 18 cm. During growth, the furnace was heated to the growth temperature of 650˚C and Ar gas flow passed through the furnace at a flow rate of 10sccm. The sulfur vapor is carried by the Ar gas flow and the MoO3 powders were evaporated and reduced by the S vapor to form MO3-x vapor. The MO3-x arrives at the substrate surface and reacts with the S vapor to form MoS2. With the seeding of PTAS, the synthesis of MoS2 favors layer growth and forms a continuous single layer MoS2 of size a few cm with a limited furnace size. (Figure 1(a) in main text). There is a discontinuous area full of isolated triangles because of reduced reactants for a geometry of crucible. The triangular shape of MoS2 monolayers is a direct consequence of the crystal structure of MoS2. The domain size of this sample is 20 µm on average (right of Figure S1b); a representative AFM is shown in Figure 1c. The thickness of CVD MoS2 monolayers is ~ 8 Å, consistent with values of MoS2 monolayer reported elsewhere.
3
CVD growth of single layer graphene
Figure S2. (a) Optical micrograph and (b) Raman spectroscopy of CVD-grown singlelayer graphene from the position indicated by the white circle in (a). The graphene sample was prepared by low-pressure chemical vapor deposition (LPCVD) process, following the established Cu-foil based graphene synthesis process. A 36 µm-thick Cu foil was used as a catalyst substrate that was located inside the growth chamber (quartz tube), with flowing CH4 and H2. Graphene was synthesized at 1035 °C with the pressure maintained at 1.70 Torr. For further analysis, graphene was transferred onto a 300 nm-thick SiO2 thermally grown heavily p-doped Si substrate as well as the pre-fabricated MoS2 sample, by taking advantage of a supporting layer. First, the graphene on a reverse side of the Cu foil was removed using O2/He plasma. Subsequently, PMMA (495 Microchem A4) as a supporting layer was spun on a graphene/Cu stack and then this stack was brought onto a Cu etchant (CE-100, TRANSENE). After etching Cu for one hour, the resulting PMMA/graphene stack was thoroughly rinsed with DI water. Further treatments to clean the graphene surface followed. Finally, this PMMA/graphene stack floating on a DI water bath was transferred onto a SiO2/Si and MoS2/ SiO2/Si substrate. To reduce trapping of water molecules between graphene and substrates, Piranha cleaning was carried out on the substrate in advance in the case of SiO2. The PMMA/graphene stack transferred on a SiO2/Si substrate was then dipped in acetone solution to selectively remove the PMMA. As a result, an intact and remarkably conformal graphene sample on the SiO2/Si and MoS2/ SiO2/Si substrate was obtained. In a specific area, as shown in Fig. S2(a), a small crack 4
(dashed circle) was found and the surface of graphene was notably clean with negligible PMMA residue. The quality of this graphene was characterized with Raman spectroscopy using a laser with the wavelength of 532 nm. The Raman spectra of graphene/ SiO2/Si (dashed red line in Figure S2b) showed evidence that this graphene was a single layer from the intensity ratio of the 2D band to the G band (2D/G) which was as high as ~8. Besides, as an indication of the defectiveness of graphene, the intensity ratio of the D band to the G band (D/G) was considered because the D-band generally appearing at 1345 cm-1 is susceptible to point defects in graphene created by impurities or by the interaction with dangling bonds of the substrate. The Raman spectra obtained in 10 locations in the sample showed not only negligible D band intensity by itself, as shown in Fig. S2 (b), but D/G lower than 0.1 on average. This provided a baseline of the quality of graphene to be used in the fabrication of the MoS2 transistor and circuits. The Raman spectra of graphene/ MoS2/ SiO2/Si is shown as the black line in Figure S2 (b). The strong background comes from the photoluminescence from MoS2 underneath. The position and intensity ratio of G and 2D in graphene persist in the graphene/ MoS2/ SiO2/Si structure, demonstrating the high quality of graphene.
5
Alignment accuracy of fabrication process A) Alignment accuracy The alignment accuracy is limited by the lithography step. If the alignment accuracy is Δ and resolution is γ for the lithography, we need Δ for the part of graphene on top of MoS2 (avoid cutting through MoS2) and we need γ for the width of the cut. Thus the alignment accuracy (or the difference between gate length and channel length) is Δ+γ. This cutting process is compatible with flexible electronics process where alignment margin is usually large. There is no leakage from the graphene edge in our devices after etch step and several nanometer gap is enough to isolate two graphene sheet. Thus this cut step won’t introduce large leakage current. B) E-Beam lithography alternates E-Beam lithography has been used just to ensure process cleanness and convenient design during lab stage. Since the whole process is CMOS fabrication compatible, we can use conventional photolithography processes instead as demonstrated by our group in the past[1]. We have added the discussion about the graphene cut process and alternative lithography technologies in the supporting information.
6
Top gate performance of MoS2-G FET.
Figure S3. Top gate performance of the MoS2–G FET: (a) log-scale current density; (b) transconductance/channel-width as a function of the top gate voltage Vtg with different source drain voltage Vd.
7
Temperature dependence of MoS2-Ti and MoS2-G FETs.
Figure S4. (a) Transconductance as a function of the back gate overdrive (Vbg-Vt). (b) Threshold voltage Vt as a function of temperature (T) of the MoS2–G FET.
Figure S5. Transconductance as a function of the back gate voltage Vbg at various temperatures in the control system MoS2 –Ti FET.
8
Calculation of n and Rs In a Schottky diode, when there is a series resistance 𝑅𝑠 , the current is expressed by 𝐼d = 𝐼s [exp(𝑞(𝑉d − 𝐼d 𝑅s )/𝑛𝜅𝐵 𝑇) − 1]
giving
𝑉d = 𝐼d 𝑅s +
𝑛 𝑘𝐵 𝑇 𝐼d 𝑑𝑉d 𝑛 𝑘𝐵 𝑇 1 𝑙𝑛 � + 1� ⟹ = 𝑅s + 𝑞 𝐼s 𝑑𝐼d 𝑞 𝐼d
6x105
dVd /dId (Ω)
5x105
4x105
3x105
2x105 0.0
4.0x105 8.0x105 1.2x106 1.6x106 2.0x106
1 / Id Figure S6. Plot of 𝑑𝑉d ⁄𝑑𝐼d as a function of 1⁄𝑑𝐼d for the MoS2-Ti FET with Vbg = 40V. In the plot of 𝑑𝑉d ⁄𝑑𝐼d as a function of 1⁄𝑑𝐼d the intercept is 𝑅s and the slope is
𝑛𝑘𝐵 𝑇⁄𝑞 . By using this method, n and Rs for each back gate voltage are calculated.
Figure S6 is an example of the fitting with Vbg = 40 V which gives Rs= 212 kΩ and n =
13.4.
9
Density functional theory (DFT) Calculation of the Graphene – MoS2 Interface
Figure S7. Side view of the charge difference between the combined system G/MoS2 and the sum of the isolated G and MoS2. (a) Plane-averaged electron density difference Δρ⊥ (10-3 e-/Å3) along the direction perpendicular to the interface z (Å). The horizontal solid lines indicate the position of the carbon atoms for G, and Mo and S for MoS2. (b) Isosurfaces (at ± 0.004 e-3/Å3) corresponding to the Δρ⊥ of the interface. The blue and red colors indicate electron accumulation and depletion, respectively. Figure S7 shows the charge difference Δρ⊥, plane-averaged perpendicular to the interface (Fig. S7 (a)), and the respective isosurfaces (Fig. S7 (b)) of the charge redistribution. The blue regions represent accumulation, and the red regions represent the depletion of electrons in the combined system relative to the two isolated components. In the calculation we have frozen the atomic positions of the respective layers as obtained in the combined situation. The polarization of the charge redistribution is beneficial to charge injection at the interface at low bias.
10
Figure S8: Calculated Schottky barrier height (SBH) 𝜑𝐵 (in meV) as a function of the bias voltage Vbg (in V) at different doping levels. The horizontal red line at 400 meV shows the value of the SBH expected from the energy difference between the work function of graphene (4.5 eV) and the electron affinity of MoS2 (~4.1 eV). The red dots show the experimental results obtained as described in the main text.
11
Graphene-MoS2 Hybrid Technology for Large-Scale TwoDimensional Electronics ⊥
Lili Yu1*, Yi-Hsien Lee2, Xi Ling1, Elton J.G. Santos3, , Yong Cheol Shin4, Yuxuan Lin1, Madan Dubey5, Efthimios Kaxiras3,6, Jing Kong1, Han Wang1*, and Tomás Palacios1* 1
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 77
Massachusetts Avenue, Cambridge, MA 02139, USA. 2
Materials Science and Engineering, National Tsing-Hua University, Hsinchu, 30013, Taiwan
School of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA
3 4
Department of Materials Science and Engineering, Massachusetts Institute of Technology, 77 Massachusetts
Avenue, Cambridge, MA 02139, USA. 5
United States Army Research Laboratory, 2800 Powder Mill Road, Adelphi, Maryland 20783-1197, United
States 6
Department of Physics, Harvard University, Cambridge, MA 02138, USA
⊥
Present address: Department of Chemical Engineering, Stanford University, Stanford, California
94305, United States, SLAC National Accelerator Laboratory, SUNCAT Center for Interface Science and Catalysis, Menlo Park, California 94025, United States
Corresponding author E-mail: [email protected], [email protected], [email protected]
1
CVD growth of MoS2
Figure S1. (a) Schematic setup for CVD growth of single layer MoS2. (b) Optical micrograph of as-grown CVD MoS2 at different locations. (c) AFM image and height profile of isolated triangle of MoS2 from right image of Figure S1 (b). Large-area single layer MoS2 was grown on 300 nm SiO2/Si substrate for large-scale electronics. The growth of MoS2 monolayers was initiated with the seeding of PTAS on substrate surfaces. A high solubility of PTAS in deionized (DI) water enables a uniform distribution of the seeds on the hydrophilic substrate surfaces. Uniform but small PTAS are precipitated on the surfaces after drying the water. The treated substrates are mounted up-side down in a growth furnace, the schematic set-up of which is shown in Figure S1. 2
The MoO3 powders (0.03g) and S powders (0.01g) were placed in different crucibles. The optimized distance of MoO3 and S crucible is 18 cm. During growth, the furnace was heated to the growth temperature of 650˚C and Ar gas flow passed through the furnace at a flow rate of 10sccm. The sulfur vapor is carried by the Ar gas flow and the MoO3 powders were evaporated and reduced by the S vapor to form MO3-x vapor. The MO3-x arrives at the substrate surface and reacts with the S vapor to form MoS2. With the seeding of PTAS, the synthesis of MoS2 favors layer growth and forms a continuous single layer MoS2 of size a few cm with a limited furnace size. (Figure 1(a) in main text). There is a discontinuous area full of isolated triangles because of reduced reactants for a geometry of crucible. The triangular shape of MoS2 monolayers is a direct consequence of the crystal structure of MoS2. The domain size of this sample is 20 µm on average (right of Figure S1b); a representative AFM is shown in Figure 1c. The thickness of CVD MoS2 monolayers is ~ 8 Å, consistent with values of MoS2 monolayer reported elsewhere.
3
CVD growth of single layer graphene
Figure S2. (a) Optical micrograph and (b) Raman spectroscopy of CVD-grown singlelayer graphene from the position indicated by the white circle in (a). The graphene sample was prepared by low-pressure chemical vapor deposition (LPCVD) process, following the established Cu-foil based graphene synthesis process. A 36 µm-thick Cu foil was used as a catalyst substrate that was located inside the growth chamber (quartz tube), with flowing CH4 and H2. Graphene was synthesized at 1035 °C with the pressure maintained at 1.70 Torr. For further analysis, graphene was transferred onto a 300 nm-thick SiO2 thermally grown heavily p-doped Si substrate as well as the pre-fabricated MoS2 sample, by taking advantage of a supporting layer. First, the graphene on a reverse side of the Cu foil was removed using O2/He plasma. Subsequently, PMMA (495 Microchem A4) as a supporting layer was spun on a graphene/Cu stack and then this stack was brought onto a Cu etchant (CE-100, TRANSENE). After etching Cu for one hour, the resulting PMMA/graphene stack was thoroughly rinsed with DI water. Further treatments to clean the graphene surface followed. Finally, this PMMA/graphene stack floating on a DI water bath was transferred onto a SiO2/Si and MoS2/ SiO2/Si substrate. To reduce trapping of water molecules between graphene and substrates, Piranha cleaning was carried out on the substrate in advance in the case of SiO2. The PMMA/graphene stack transferred on a SiO2/Si substrate was then dipped in acetone solution to selectively remove the PMMA. As a result, an intact and remarkably conformal graphene sample on the SiO2/Si and MoS2/ SiO2/Si substrate was obtained. In a specific area, as shown in Fig. S2(a), a small crack 4
(dashed circle) was found and the surface of graphene was notably clean with negligible PMMA residue. The quality of this graphene was characterized with Raman spectroscopy using a laser with the wavelength of 532 nm. The Raman spectra of graphene/ SiO2/Si (dashed red line in Figure S2b) showed evidence that this graphene was a single layer from the intensity ratio of the 2D band to the G band (2D/G) which was as high as ~8. Besides, as an indication of the defectiveness of graphene, the intensity ratio of the D band to the G band (D/G) was considered because the D-band generally appearing at 1345 cm-1 is susceptible to point defects in graphene created by impurities or by the interaction with dangling bonds of the substrate. The Raman spectra obtained in 10 locations in the sample showed not only negligible D band intensity by itself, as shown in Fig. S2 (b), but D/G lower than 0.1 on average. This provided a baseline of the quality of graphene to be used in the fabrication of the MoS2 transistor and circuits. The Raman spectra of graphene/ MoS2/ SiO2/Si is shown as the black line in Figure S2 (b). The strong background comes from the photoluminescence from MoS2 underneath. The position and intensity ratio of G and 2D in graphene persist in the graphene/ MoS2/ SiO2/Si structure, demonstrating the high quality of graphene.
5
Alignment accuracy of fabrication process A) Alignment accuracy The alignment accuracy is limited by the lithography step. If the alignment accuracy is Δ and resolution is γ for the lithography, we need Δ for the part of graphene on top of MoS2 (avoid cutting through MoS2) and we need γ for the width of the cut. Thus the alignment accuracy (or the difference between gate length and channel length) is Δ+γ. This cutting process is compatible with flexible electronics process where alignment margin is usually large. There is no leakage from the graphene edge in our devices after etch step and several nanometer gap is enough to isolate two graphene sheet. Thus this cut step won’t introduce large leakage current. B) E-Beam lithography alternates E-Beam lithography has been used just to ensure process cleanness and convenient design during lab stage. Since the whole process is CMOS fabrication compatible, we can use conventional photolithography processes instead as demonstrated by our group in the past[1]. We have added the discussion about the graphene cut process and alternative lithography technologies in the supporting information.
6
Top gate performance of MoS2-G FET.
Figure S3. Top gate performance of the MoS2–G FET: (a) log-scale current density; (b) transconductance/channel-width as a function of the top gate voltage Vtg with different source drain voltage Vd.
7
Temperature dependence of MoS2-Ti and MoS2-G FETs.
Figure S4. (a) Transconductance as a function of the back gate overdrive (Vbg-Vt). (b) Threshold voltage Vt as a function of temperature (T) of the MoS2–G FET.
Figure S5. Transconductance as a function of the back gate voltage Vbg at various temperatures in the control system MoS2 –Ti FET.
8
Calculation of n and Rs In a Schottky diode, when there is a series resistance 𝑅𝑠 , the current is expressed by 𝐼d = 𝐼s [exp(𝑞(𝑉d − 𝐼d 𝑅s )/𝑛𝜅𝐵 𝑇) − 1]
giving
𝑉d = 𝐼d 𝑅s +
𝑛 𝑘𝐵 𝑇 𝐼d 𝑑𝑉d 𝑛 𝑘𝐵 𝑇 1 𝑙𝑛 � + 1� ⟹ = 𝑅s + 𝑞 𝐼s 𝑑𝐼d 𝑞 𝐼d
6x105
dVd /dId (Ω)
5x105
4x105
3x105
2x105 0.0
4.0x105 8.0x105 1.2x106 1.6x106 2.0x106
1 / Id Figure S6. Plot of 𝑑𝑉d ⁄𝑑𝐼d as a function of 1⁄𝑑𝐼d for the MoS2-Ti FET with Vbg = 40V. In the plot of 𝑑𝑉d ⁄𝑑𝐼d as a function of 1⁄𝑑𝐼d the intercept is 𝑅s and the slope is
𝑛𝑘𝐵 𝑇⁄𝑞 . By using this method, n and Rs for each back gate voltage are calculated.
Figure S6 is an example of the fitting with Vbg = 40 V which gives Rs= 212 kΩ and n =
13.4.
9
Density functional theory (DFT) Calculation of the Graphene – MoS2 Interface
Figure S7. Side view of the charge difference between the combined system G/MoS2 and the sum of the isolated G and MoS2. (a) Plane-averaged electron density difference Δρ⊥ (10-3 e-/Å3) along the direction perpendicular to the interface z (Å). The horizontal solid lines indicate the position of the carbon atoms for G, and Mo and S for MoS2. (b) Isosurfaces (at ± 0.004 e-3/Å3) corresponding to the Δρ⊥ of the interface. The blue and red colors indicate electron accumulation and depletion, respectively. Figure S7 shows the charge difference Δρ⊥, plane-averaged perpendicular to the interface (Fig. S7 (a)), and the respective isosurfaces (Fig. S7 (b)) of the charge redistribution. The blue regions represent accumulation, and the red regions represent the depletion of electrons in the combined system relative to the two isolated components. In the calculation we have frozen the atomic positions of the respective layers as obtained in the combined situation. The polarization of the charge redistribution is beneficial to charge injection at the interface at low bias.
10
Figure S8: Calculated Schottky barrier height (SBH) 𝜑𝐵 (in meV) as a function of the bias voltage Vbg (in V) at different doping levels. The horizontal red line at 400 meV shows the value of the SBH expected from the energy difference between the work function of graphene (4.5 eV) and the electron affinity of MoS2 (~4.1 eV). The red dots show the experimental results obtained as described in the main text.
11
