High slew rate, low voltage BiCMOS and bipolar operational amplifier ...
743
High slew rate, low voltage BiCMOS and bipolar operational amplifier architectures with rail to rail common mode input voltage swing Jaime Ramirez-Angulo Department of Electrical and Computer Engineering New Mexico State University Box 30001Dept. 3-0, Las Cruces, NM 88003-0001 Tel. (505)-646-4406, FAX: (505)-646-1435, [email protected] Abstract. Class AB differential amplifiers using composite BiCMOS and bipolar transistors are introduced. Their utilization for the implementation of low voltage (+-1.65V) operational amplifiers with high slew rate and rail to rail common mode input voltage range is discussed.
I. INTRODUCTION High performance analog circuits are required in mixed mode VLSI systems that operate with single 3.3V supplies. One of the fundamental building blocks of analog circuits is the operational amplifier which for high speed voltage follower (buffer) applications has commonly the requirement to operate with a rail to rail common mode input voltage range, high slew rate and low static power consumption. In this communication we discuss the application of composite BiCMOS and composite bipolar transistors to implement operational amplifiers that operate with a single 3.3V supply and that have rail to rail common mode input voltage swing, high slew rate and bandwidth almost independent of the common mode input voltage.
II. BiCMOS AND BIPOLAR CLASS AB DIFFERENTIAL PAIRS Composite CMOS transistors (Fig. la) have been shown to be equivalent to a single MOS transistor with increased threshold voltage and reduced transconductance gain [l]. They have been used to implement the floating voltage sources required in class AB differential amplifiers. Composite CMOS transistors have several disadvantages [2][3]. The main one is that they have increased operating voltage requirements and for this reason, they are not compatible with low voltage supply VLSI systems. Composite BiCMOS and bipolar transistors were introduced by the author (Figs. l b and IC) recently [2]; these composite devices do not have the high voltage biasing requirements of composite CMOS transistors. Composite BiCMOS transistors
were shown to be equivalent to a regular MOS transistor of either polarity. Composite bipolar transistors were shown to be equivalent to a regular bipolar transistor of either polarity. Composite BiCMOS transistors can be used to implement class AB differential pairs for linear OTA applications [3],[5]. Composite bipolar transistor were used to implement linear programmable current mirrors with very wide gain adjustment range [4]. The basic scheme of a class AB differential pair with MOS transistors is shown in Fig. 2a. It requires two floating DC voltage sources (VMT). Its implementation using BiCMOS composite transistors is shown in Fig. 2b. In this implementation both the MOS transistor and the sources are substituted by composite BiCMOS transistors. Fig. 3a shows the basic scheme of a class AB differential pair with bipolar transistors, Fig. 3b shows its implementation using composite bipolar transistors. Fig. 4 shows the transfer characteristics of the differential pair currents (Il,I2) as a function of the differential input voltage (Vd). Fig. 4a corresponds to the composite BiCMOS version of Fig. 3a and Fig. 4b to the composite bipolar version of Fig. 3b. It can be seen that in both cases currents I1,12 are not limited by the differential as it is the case for a conventional pair bias currents (IBIAS) differential amplifier. In fact, it can be seen that I1,12 take values in the milliampere range with quiescent currents of only 100 uA. Class AB differential amplifiers can be used to implement high slew rate op amps without high static power consumption. An important feature of circuits of Figs. 2 and 3 is that currents I1 and I2 are available simultaneously at the top and bottom of the circuit. 'Ihis gives added design flexibility and simplifies the topology of the op amp circuit discussed in section 111.
III. HIGH SLEW RATE, LOW VOLTAGE RAILRAIL OP-AMP Low voltage op-amp architectures with rail to rail common-
744
mode input voltage range commonly use complementary differential input stages and folding techniques with DC currents sources (denoted Ibiasf in Fig. 5 ) to steer the differential pair currents to the op amp output node as shown in the circuit of Fig. 5 [6]. The maximum output current of this circuit is limited both by the bias currents of the differential pairs (Ibias) and the DC current sources of the folding circuitry (Ibiasf). The slew rate for a structure of this type has a value SR=Ibias/Cl where C1 is the load capacitance (Ibias=Ibiasf is assumed). For low supply voltages the transconductance gain of the op amp (and its bandwidth) is subject to at least a factor two variation with change in the common mode input voltage. This feature is not desirable since it does not allow optimal compensation of the op amp. Direct substitution of the differential pairs in Fig. 5 with class AB differential pairs using composite CMOS transistors overcomes the limitation on the output current due to the Ibias but not that due the folding circuitry. Another disadvantage is that composite CMOS transistors increase the supply voltage requirements of the circuit and decrease the effective transconductance (and the bandwidth) of the op amp [3]. Class AB differential amplifiers using composite bipolar or BiCMOS transistors can be used to implement high slew rate opamps with low voltage supply requirements. Fig. 6 shows the scheme of an op amp using complementary class AB differential pairs with composite BiCMOS transistors. Transistors Ml-M4 and Ql-Q4 constitute one of the differential pairs denoted DPI; MlP-M4P and QlP-Q4P constitute the complementary differential pair denoted DPII. The availability of the differential pair currents simultaneously on top and bottom of the circuit allows to avoid folding circuitry (and the corresponding output current limitation) since the currents I1,E of both differential pairs can be sensed on the same nodes (on the bottom of the circuit at Q5P and Q6P) using bipolar current mirrors Q5,Q5P and Q6,Q6P. A standard three mirror differencing scheme is used to obtain the op amp output current.
Operation of the circuit: For moderate or large positive common mode input voltages DPII is active while transistors in DPI are in cutoff. For moderate or large negative common mode input voltages transistors in DPI are active while transistors in DPII are in cutoff. For zero or small (positive or negative) common mode input voltages all transistors in DPI and DPII are in a transition from cutoff to saturated (active) mode. The transconductance gain (and bandwidth) of the op amp remains approximately constant over most of the common mode input voltage range (see simulations in section IV). This is achieved if for zero common mode input voltage the transistors in DPI and DPII have static currents which are approximately one half of the nominal bias currents. For +-1.65V operation this is achieved by sizing MOS transistors .in DPI and DPII to have a
quiescent VGS-VT of approximately 0.15V for the nominal bias current Ibias. The operating voltage requirements of transistors Q5P and Q6P do not preclude the operation of the circuit with rail to rail common mode swing since for large negative common mode signals only transistors in DPI are active and in spite of the voltage requirement (-0.6V) of Q5P and Q6P there is enough voltage to operate M1 and M4 in saturated mode. The operating voltage requirements of the input mirror transistors Q5P and Q6P can be reduced form 0.7V to 0.2V using low input voltage mirror structures recently introduced by the author [8].
IV. SIMULATION RESULTS The op amp of Fig. 6 was simulated using level two model parameters of the 2um BiCMOS low noise analog process of MOSIS [9]. Width over length ratios W/L=500/2 (in um) were used for all (P-channel) transistors. Bottom and DC biasing current sources were implemented with bipolar and MOS transistors respectively. Supply voltages of +-1.65V, bias currents Ibias=lOOuA and a load capacitance C b l O p F were used for the simulations. This corresponds to a slew rate SR=10 V / s in a conventional op amp. Fig. 7 shows a the static characteristic Vout vs Vin for the op amp connected in voltage follower configuration. It can be seen the op amp has a rail to rail common mode voltage range. Fig. 8a shows the transient response of the voltage follower to a 2Vp-p pulse, Fig. 8b shows the transient load capacitance current. The slew rate is approximately 12OV/us which is a factor 12 higher than for the conventional op amp structure with the same static current. A peak load capacitance transient current of approximately 2mA can be observed. This is a factor 20 larger than the static current. A SPICE simulation of the frequency response of the voltage follower for values of common mode input voltage (Vin) from -1.25 to 1.25V (in 0.2% steps) was done (it is not shown for the sake of space). It could be observed that the bandwidth (-3OMHz) remained approximately constant with changes in the common mode input voltage. This allows to optimize the compensation of the op amp and to obtain maximum bandwidth. Noise spectral density according to simulations is 25nV/dHz Breadboard prototypes of the circuit of Fig. 6 using BiCMOS arrays fabricated through MOSIS [7] have been built and tested to verify functionality (not the slew rate) of the circuit. A breadboard implementation of a bipolar version of the same circuit (all P-channel transistors replaced by PNP transistors) was also built and tested using CA3096 transistor arrays. In both circuits functionality could be verified. Both the BiCMOS circuit of Fig. 6 and the bipolar version are currently in fabrication using the low noise analog BiCMOS p'ocess of MOSIS.Experimenta1 results of the integrated version of the circuit will be discussed in a journal version of this paper.
745
V. CONCLUSIONS
Novel BiCMOS and bipolar op-amp structures using complementary class AB differential input stages have been proposed and verified. They operate with +-1.65V supplies and have slew rates which are at least a factor 10 times higher than conventional structures with comparable static power dissipation.
[7]
[8]
"Low Voltage Current mirrors for Built-in Current
Sensors," Jaime Ramirez-Angulo, 1994 IEEE International Symposium on Circuits and Systems,
REFERENCES "A versatile CMOS linear transconductor/square law function circuit," Seevinck, E. AND Waseenar, R.F.JEEE J. Solidatate Circuits, vol. SC-22, No.3, pp. 366-377, 1987.
"Use of MOSIS custom designed CMOS and BiCMOS transistor Arrays for teaching VLSI courses", J. Ramirez-Angulo and J. Beasley, 37th Midwest Symposium on Circuits and Systems, Detroir, MI, August 16-18 1993
London May 29-June 2, 1994. [9]
Low-Noise Analog Process Information, MOSIS, USC, Information Sciences Institute, Marina del Rey, CA.
Fig. 2
Class AB differential amplifier with composite BiCMOS transistors (a) Basic scheme @) Substitution of MOS transistors and batteries with composite BiCMOS transistors.
Fig. 3
Class AB differential amplifier with bipolar transistors (a) Basic scheme (b) Substitution of Bipolar trahktors and batten& with mnposite bipolar transistors
"Applications of Composite BICMOS Transistors," J. Ramirez-Angulo, M. Deyong and W.J. Adams, Electronics Letters, Vol. 27, No. 24, pp. 2236-2238, Nov. 1991. "A low-voltage vertical BiCMOS OTA", J. Ramirez-Angulo, IEEproceedings Part G, Vol. 139, NO. 4, August 1992, pp. 553-556 Wide gm Adjustment Range, Highly Linear OTA with Linear Programmable Current Mirrors,"J. Ramirez-Angulo and I. Grau, Proceedings of 1992IEEE Internutwnal Conference on Circuits and Systems, pp. 1372-1375, San Diego CA, May 10-13 1992. "A second generation Linear low-voltage BiCMOS OTA," J. Ramirez-Angulo and K. H. Treece, 1993 IEEE International Symposium on Circuits and Systems, pp. 1172-1175, May 3-6 1993, Chicago, 11. "Low Voltage Operational amplifier with rail-rail input and output ranges," J.H. Huising and D. Linebarger, IEEE Journal of Solid State Circuits, vol. SC-20, pp. 1144-1150,Dec. 1985.
Fig. 1 (a) Composite CMOS transistor @) Composite BiCMOS transistor (c) Composite bipolar transistor
746
Fig. 5 I
Low Voltage CMOS op amp with rail to rail common mode input voltage range
I
0.0v -.
.
-1.ov
1
I' __
-1ov .
-2W 0
Fig. 4
Transfer characteristics of class AB differential amplifiers (a) Composite BiCMOS version of Fig. 2 @) Composite bipolar version of Fig. 3
v(m
Fig. 7
-15V
-l.W
4.W
0.W
Q.N
1.W
1.N
2.W
I
vln
Simulated DC voltage transfer characteristic of op amp of Fig. 5 in voltage follower configuration
I46P
-1.5V 0
--o
Fig. 6
Low voltage BiCMOS op-amp with rail to rail common mode input voltage range
2.0mA
t
"(20)
Fig. 8
.
"(1)
t
(a) Transient response of voltage follower to an input pulse (b) Load capacitance current
High slew rate, low voltage BiCMOS and bipolar operational amplifier architectures with rail to rail common mode input voltage swing Jaime Ramirez-Angulo Department of Electrical and Computer Engineering New Mexico State University Box 30001Dept. 3-0, Las Cruces, NM 88003-0001 Tel. (505)-646-4406, FAX: (505)-646-1435, [email protected] Abstract. Class AB differential amplifiers using composite BiCMOS and bipolar transistors are introduced. Their utilization for the implementation of low voltage (+-1.65V) operational amplifiers with high slew rate and rail to rail common mode input voltage range is discussed.
I. INTRODUCTION High performance analog circuits are required in mixed mode VLSI systems that operate with single 3.3V supplies. One of the fundamental building blocks of analog circuits is the operational amplifier which for high speed voltage follower (buffer) applications has commonly the requirement to operate with a rail to rail common mode input voltage range, high slew rate and low static power consumption. In this communication we discuss the application of composite BiCMOS and composite bipolar transistors to implement operational amplifiers that operate with a single 3.3V supply and that have rail to rail common mode input voltage swing, high slew rate and bandwidth almost independent of the common mode input voltage.
II. BiCMOS AND BIPOLAR CLASS AB DIFFERENTIAL PAIRS Composite CMOS transistors (Fig. la) have been shown to be equivalent to a single MOS transistor with increased threshold voltage and reduced transconductance gain [l]. They have been used to implement the floating voltage sources required in class AB differential amplifiers. Composite CMOS transistors have several disadvantages [2][3]. The main one is that they have increased operating voltage requirements and for this reason, they are not compatible with low voltage supply VLSI systems. Composite BiCMOS and bipolar transistors were introduced by the author (Figs. l b and IC) recently [2]; these composite devices do not have the high voltage biasing requirements of composite CMOS transistors. Composite BiCMOS transistors
were shown to be equivalent to a regular MOS transistor of either polarity. Composite bipolar transistors were shown to be equivalent to a regular bipolar transistor of either polarity. Composite BiCMOS transistors can be used to implement class AB differential pairs for linear OTA applications [3],[5]. Composite bipolar transistor were used to implement linear programmable current mirrors with very wide gain adjustment range [4]. The basic scheme of a class AB differential pair with MOS transistors is shown in Fig. 2a. It requires two floating DC voltage sources (VMT). Its implementation using BiCMOS composite transistors is shown in Fig. 2b. In this implementation both the MOS transistor and the sources are substituted by composite BiCMOS transistors. Fig. 3a shows the basic scheme of a class AB differential pair with bipolar transistors, Fig. 3b shows its implementation using composite bipolar transistors. Fig. 4 shows the transfer characteristics of the differential pair currents (Il,I2) as a function of the differential input voltage (Vd). Fig. 4a corresponds to the composite BiCMOS version of Fig. 3a and Fig. 4b to the composite bipolar version of Fig. 3b. It can be seen that in both cases currents I1,12 are not limited by the differential as it is the case for a conventional pair bias currents (IBIAS) differential amplifier. In fact, it can be seen that I1,12 take values in the milliampere range with quiescent currents of only 100 uA. Class AB differential amplifiers can be used to implement high slew rate op amps without high static power consumption. An important feature of circuits of Figs. 2 and 3 is that currents I1 and I2 are available simultaneously at the top and bottom of the circuit. 'Ihis gives added design flexibility and simplifies the topology of the op amp circuit discussed in section 111.
III. HIGH SLEW RATE, LOW VOLTAGE RAILRAIL OP-AMP Low voltage op-amp architectures with rail to rail common-
744
mode input voltage range commonly use complementary differential input stages and folding techniques with DC currents sources (denoted Ibiasf in Fig. 5 ) to steer the differential pair currents to the op amp output node as shown in the circuit of Fig. 5 [6]. The maximum output current of this circuit is limited both by the bias currents of the differential pairs (Ibias) and the DC current sources of the folding circuitry (Ibiasf). The slew rate for a structure of this type has a value SR=Ibias/Cl where C1 is the load capacitance (Ibias=Ibiasf is assumed). For low supply voltages the transconductance gain of the op amp (and its bandwidth) is subject to at least a factor two variation with change in the common mode input voltage. This feature is not desirable since it does not allow optimal compensation of the op amp. Direct substitution of the differential pairs in Fig. 5 with class AB differential pairs using composite CMOS transistors overcomes the limitation on the output current due to the Ibias but not that due the folding circuitry. Another disadvantage is that composite CMOS transistors increase the supply voltage requirements of the circuit and decrease the effective transconductance (and the bandwidth) of the op amp [3]. Class AB differential amplifiers using composite bipolar or BiCMOS transistors can be used to implement high slew rate opamps with low voltage supply requirements. Fig. 6 shows the scheme of an op amp using complementary class AB differential pairs with composite BiCMOS transistors. Transistors Ml-M4 and Ql-Q4 constitute one of the differential pairs denoted DPI; MlP-M4P and QlP-Q4P constitute the complementary differential pair denoted DPII. The availability of the differential pair currents simultaneously on top and bottom of the circuit allows to avoid folding circuitry (and the corresponding output current limitation) since the currents I1,E of both differential pairs can be sensed on the same nodes (on the bottom of the circuit at Q5P and Q6P) using bipolar current mirrors Q5,Q5P and Q6,Q6P. A standard three mirror differencing scheme is used to obtain the op amp output current.
Operation of the circuit: For moderate or large positive common mode input voltages DPII is active while transistors in DPI are in cutoff. For moderate or large negative common mode input voltages transistors in DPI are active while transistors in DPII are in cutoff. For zero or small (positive or negative) common mode input voltages all transistors in DPI and DPII are in a transition from cutoff to saturated (active) mode. The transconductance gain (and bandwidth) of the op amp remains approximately constant over most of the common mode input voltage range (see simulations in section IV). This is achieved if for zero common mode input voltage the transistors in DPI and DPII have static currents which are approximately one half of the nominal bias currents. For +-1.65V operation this is achieved by sizing MOS transistors .in DPI and DPII to have a
quiescent VGS-VT of approximately 0.15V for the nominal bias current Ibias. The operating voltage requirements of transistors Q5P and Q6P do not preclude the operation of the circuit with rail to rail common mode swing since for large negative common mode signals only transistors in DPI are active and in spite of the voltage requirement (-0.6V) of Q5P and Q6P there is enough voltage to operate M1 and M4 in saturated mode. The operating voltage requirements of the input mirror transistors Q5P and Q6P can be reduced form 0.7V to 0.2V using low input voltage mirror structures recently introduced by the author [8].
IV. SIMULATION RESULTS The op amp of Fig. 6 was simulated using level two model parameters of the 2um BiCMOS low noise analog process of MOSIS [9]. Width over length ratios W/L=500/2 (in um) were used for all (P-channel) transistors. Bottom and DC biasing current sources were implemented with bipolar and MOS transistors respectively. Supply voltages of +-1.65V, bias currents Ibias=lOOuA and a load capacitance C b l O p F were used for the simulations. This corresponds to a slew rate SR=10 V / s in a conventional op amp. Fig. 7 shows a the static characteristic Vout vs Vin for the op amp connected in voltage follower configuration. It can be seen the op amp has a rail to rail common mode voltage range. Fig. 8a shows the transient response of the voltage follower to a 2Vp-p pulse, Fig. 8b shows the transient load capacitance current. The slew rate is approximately 12OV/us which is a factor 12 higher than for the conventional op amp structure with the same static current. A peak load capacitance transient current of approximately 2mA can be observed. This is a factor 20 larger than the static current. A SPICE simulation of the frequency response of the voltage follower for values of common mode input voltage (Vin) from -1.25 to 1.25V (in 0.2% steps) was done (it is not shown for the sake of space). It could be observed that the bandwidth (-3OMHz) remained approximately constant with changes in the common mode input voltage. This allows to optimize the compensation of the op amp and to obtain maximum bandwidth. Noise spectral density according to simulations is 25nV/dHz Breadboard prototypes of the circuit of Fig. 6 using BiCMOS arrays fabricated through MOSIS [7] have been built and tested to verify functionality (not the slew rate) of the circuit. A breadboard implementation of a bipolar version of the same circuit (all P-channel transistors replaced by PNP transistors) was also built and tested using CA3096 transistor arrays. In both circuits functionality could be verified. Both the BiCMOS circuit of Fig. 6 and the bipolar version are currently in fabrication using the low noise analog BiCMOS p'ocess of MOSIS.Experimenta1 results of the integrated version of the circuit will be discussed in a journal version of this paper.
745
V. CONCLUSIONS
Novel BiCMOS and bipolar op-amp structures using complementary class AB differential input stages have been proposed and verified. They operate with +-1.65V supplies and have slew rates which are at least a factor 10 times higher than conventional structures with comparable static power dissipation.
[7]
[8]
"Low Voltage Current mirrors for Built-in Current
Sensors," Jaime Ramirez-Angulo, 1994 IEEE International Symposium on Circuits and Systems,
REFERENCES "A versatile CMOS linear transconductor/square law function circuit," Seevinck, E. AND Waseenar, R.F.JEEE J. Solidatate Circuits, vol. SC-22, No.3, pp. 366-377, 1987.
"Use of MOSIS custom designed CMOS and BiCMOS transistor Arrays for teaching VLSI courses", J. Ramirez-Angulo and J. Beasley, 37th Midwest Symposium on Circuits and Systems, Detroir, MI, August 16-18 1993
London May 29-June 2, 1994. [9]
Low-Noise Analog Process Information, MOSIS, USC, Information Sciences Institute, Marina del Rey, CA.
Fig. 2
Class AB differential amplifier with composite BiCMOS transistors (a) Basic scheme @) Substitution of MOS transistors and batteries with composite BiCMOS transistors.
Fig. 3
Class AB differential amplifier with bipolar transistors (a) Basic scheme (b) Substitution of Bipolar trahktors and batten& with mnposite bipolar transistors
"Applications of Composite BICMOS Transistors," J. Ramirez-Angulo, M. Deyong and W.J. Adams, Electronics Letters, Vol. 27, No. 24, pp. 2236-2238, Nov. 1991. "A low-voltage vertical BiCMOS OTA", J. Ramirez-Angulo, IEEproceedings Part G, Vol. 139, NO. 4, August 1992, pp. 553-556 Wide gm Adjustment Range, Highly Linear OTA with Linear Programmable Current Mirrors,"J. Ramirez-Angulo and I. Grau, Proceedings of 1992IEEE Internutwnal Conference on Circuits and Systems, pp. 1372-1375, San Diego CA, May 10-13 1992. "A second generation Linear low-voltage BiCMOS OTA," J. Ramirez-Angulo and K. H. Treece, 1993 IEEE International Symposium on Circuits and Systems, pp. 1172-1175, May 3-6 1993, Chicago, 11. "Low Voltage Operational amplifier with rail-rail input and output ranges," J.H. Huising and D. Linebarger, IEEE Journal of Solid State Circuits, vol. SC-20, pp. 1144-1150,Dec. 1985.
Fig. 1 (a) Composite CMOS transistor @) Composite BiCMOS transistor (c) Composite bipolar transistor
746
Fig. 5 I
Low Voltage CMOS op amp with rail to rail common mode input voltage range
I
0.0v -.
.
-1.ov
1
I' __
-1ov .
-2W 0
Fig. 4
Transfer characteristics of class AB differential amplifiers (a) Composite BiCMOS version of Fig. 2 @) Composite bipolar version of Fig. 3
v(m
Fig. 7
-15V
-l.W
4.W
0.W
Q.N
1.W
1.N
2.W
I
vln
Simulated DC voltage transfer characteristic of op amp of Fig. 5 in voltage follower configuration
I46P
-1.5V 0
--o
Fig. 6
Low voltage BiCMOS op-amp with rail to rail common mode input voltage range
2.0mA
t
"(20)
Fig. 8
.
"(1)
t
(a) Transient response of voltage follower to an input pulse (b) Load capacitance current
