Low-Voltage Low-Power Low-Noise Amplifier for ... - Semantic Scholar
Low-Voltage Low-Power Low-Noise Amplifier for Wireless Sensor Networks Derek Ho and Shahriar Mirabbasi Department of Electrical and Computer Engineering University of British Columbia, Vancouver, Canada {dho, shahriar}@ece.ubc.ca Abstract—This work presents a methodology for designing CMOS low-voltage low-power low-noise amplifiers (LNAs) based on the inductively degenerated common-source topology. To demonstrate the application of the proposed method, two LNAs operating at 900MHz and 2.4GHz are designed and simulated using a 90nm CMOS process. The 900MHz (2.4GHz) design has noise figure of less than 5.5dB (5dB) over the entire band of interest, a power gain of 12dB (13dB), input 1dB compression point of -20dBm (-18dBm), input-referred thirdorder intercept point of -10dBm (-9dBm), and consumes 1.6mW (2.8mW) from a 0.45V (0.5V) supply. Both LNAs are matched to 50Ω input and output impedances. The LNAs are designed for operation in the industrial, scientific, and medical (ISM) band and are intended for systems using the IEEE 802.15.4 (Zigbee) low-power standard.
I.
INTRODUCTION
Supply Power (mW)
Average Power Consumption (mW)
Wireless sensor networks have seen significant growth recently in applications such as health monitoring, factory automation, and security surveillance. A wireless sensor node is typically battery operated and demands a long battery life, which imposes stringent power requirements on the sensor node circuitry [1].
Figure 1. Energy-scavenging mechanisms and power consumption for networks with different sizes [1].
This research is funded by Natural Science and Engineering Research Council of Canada (NSERC). CAD tools are provided by Canadian Microelectronics Corporation (CMC) Microsystems.
An emerging class of self-sufficient wireless sensor nodes, such as the PicoRadio [2], is designed to scavenge energy from the environment. Sensor nodes are currently small enough to harness energy from vibration, heat, and the sun (see Fig. 1). These forms of energy usually provide only a limited voltage, necessitating circuits capable of operating from a low supply voltage [3]. For example, the output voltage of a single solar cell is 0.5V. Although low-voltage receivers with microwatt power consumption have been previously reported [4], these circuits have a high noise figure (NF) and low operating frequency. This work presents a methodology for the rapid and intuitive design of a low-voltage LNA given the power budget. Based on the design methodology, two LNAs operating at 900MHz and 2.4GHz are designed and simulated using 90nm CMOS technology to meet the specifications of IEEE 802.15.4 (Zigbee) as it is becoming a popular choice for implementing wireless sensor networks [5]. Zigbee requires a minimum input 1dB compression point (P1dB) of -20dBm and a minimum input-referred thirdorder intercept point (IIP3) of -10dBm [6]. Since Zigbee is intended for short-range applications, such as sensor networks, its NF specification is rather relaxed and the NF for the entire receiver can be as large as 19dB. This paper is organized as follows: Section II describes the inductively degenerated LNA circuit topology. Section III details a methodology used to rapidly choose circuit component values. Section IV shows simulation results of two LNAs and compares them with recently proposed lowpower circuits, and finally Section V concludes the paper. II.
CIRCUIT TOPOLOGY
There are various circuit topologies for LNAs. Each topology has its own strengths and weaknesses. For example, although the cascode topology provides high gain and good input-output isolation, a two-transistor stack is not optimal for operation at low supply voltages. On the other hand, achieving a high gain with a multi-stage topology can violate the power budget. Among single-stage amplifiers,
the common-gate topology provides good linearity and stability, but its NF is generally inferior to that of the common-source (CS) topology [7]. One LNA topology that is becoming increasingly popular is the inductively degenerated CS structure. This topology, shown in Fig. 2, allows for maximizing gain under a low power budget. For this LNA, the input and output are matched to 50Ω. Input matching is accomplished with a matching network. In this work, a T-match network, consisting of Lm, Cm, and Lg. The source-degenerated inductance Ls facilitates the input matching by modifying the real part of the input impedance. Rd is used to modify the real part of the output impedance to 50Ω. Ld is used to tune out the load capacitance and undesirable parasitic capacitances of the transistor at the center frequency fc to improve the gain.
VDD
Ld Lm Cm
Lg
Step 2: Calculate the drain current ID from the target power consumption (excluding biasing circuits) PDC and target supply voltage VDD, namely ID = PDC / VDD. W can then be readily calculated from the current density chosen in step 1 (assuming the use of minimum gate length L). Step 3: Determine the gate-to-source bias voltage VGS to give the ID calculated in step 2. ID can be plotted verses different values of VGS using a circuit simulator. From this plot, VGS can be chosen. If VGS takes on the value greater than VDD, either increase VDD, which increases power, or revisit step 1 to select another sub-optimal current density. Steps 1 through 3 are iterated until a good tradeoff between power and performance is found. Step 4: Obtain the gate-source capacitance Cgs and device transconductance gm at the operating point using a circuit simulator.
Rd
RFin
appear to be constant across various technology nodes and different foundries [9].
RFout Ls
Step 5: Design Lg and Ls by finding the estimate of the input impedance Zin, given by (1) through the use of the smallsignal model in Fig. 3. υRF and Rs model the antenna. For the purpose of this estimation, body effect and channel-length modulation are assumed to be small. Fig. 3 does not include Lm and Cm as they are added in the final step.
Figure 2. The inductively degenerated CS LNA with an input T-match.
Z in =
III.
DESIGN METHODOLOGY
A number of LNA design optimization techniques are well established such as classical noise matching (CNM), simultaneous noise and input matching (SNIM), powerconstrained simultaneous noise and input matching (PCSNIM), and power-constrained noise optimization (PCNO). A good overview of these techniques is presented in [8]. These techniques are rigorous, but often too complex for hand calculations. This section presents a methodology for the rapid and intuitive design of an inductively degenerated CS LNA given the power and supply voltage constraints. We assume that a circuit simulator is available. Step 1: Determine the current density that approximately minimizes NF and maximizes the unity power gain frequency fMAX of the device. The current density is given by ID/(W/L) where ID is the drain current and W and L are the width and the length of the device, respectively. Typically, L is chosen to be the minimum length of the technology, and therefore the current density can be expressed as ID/W. Minimum NF and maximum fMAX of a MOSFET occur when the current density of the device is 0.15mA/µm and 0.2mA/µm, respectively. The minimum NF and maximum fMAX as a function of ID/W are relatively flat in the proximity of their optimal points. Interestingly, these current densities
g L 1 + jω ( L s + L g ) + m s jωC gs C gs
(1)
Figure 3. Small-signal model for calculating input impedance.
Ls is determined by equating the real part of the input impedance to Rs, as in (2). ℜe{Z in } =
g m Ls = Rs = 50Ω C gs
(2)
Once Ls is found, Lg is obtained by setting the imaginary part of Zin to zero as in (3), yielding (4). ℑm{Z in } =
1
ωC gs
+ ω ( Ls + L g ) = 0
(3)
Lg =
1
ω 2 C gs
− Ls
(4)
Step 6: Choose Rd and Ld so that the output impedance Zout, given by (5). Z out = {[1 + ( g m + g mb ) jωLs ]ro + jωLs } || ( Rd + jωLd )
(5)
Zout is the complex conjugate of the load impedance. It is derived from the small-signal model of Fig. 4, with gmVgs, ro, and gmbVbs modeling the amplifying current component, output resistance, and body effect of the transistor, respectively. The values for gm, gmb, and ro are obtained using a circuit simulator.
around 280mV, about 60mV lower than the standard threshold voltage. IV.
SIMULATION RESULTS
Both LNAs are simulated in a 90nm CMOS process using SpectreRF with the BSIM3v3 device model. For more accurate results, the inductors are modeled by the 9-element model depicted in Fig. 5. L is the inductance, and C and R are the shunt capacitance and series resistance used to model wire parasitics. COX1 and COX2 model the capacitance between the metal used for the inductor and the substrate. Their values may not necessarily be the same in cases where there is a slight asymmetry in the spiral layout. RSUB and CSUB model the parasitics of the substrate.
Figure 4. Small-signal model for output impedance calculation.
Due to the gate-drain parasitic capacitance Cgd, which couples the input to the output, when tuning the output, the input becomes out of tune. The input and output impedances cannot be simultaneously matched to 50Ω, necessitating the inclusion of a matching network to provide additional degrees of freedom for matching. Two LNAs based on the above methodology are designed. The schematics and component values of the LNAs are depicted respectively in Fig. 2 and Table 1. TABLE 1 SUMMARY OF COMPONENT VALUES
VDD (V) ID (mA) W/L (µm) Ls (nH) Lg (nH) Ld (nH) Rd (Ω) Lm (nH) Cm (pF)
900MHz Band 0.45 3.5 100/0.1 (Not Required) 53 3 30 7.5 1.2
2.4GHz Band 0.5 5.6 100/0.1 0.4 15.6 3 30 3.6 1
The calculated value of Ls for the 900MHz LNA is negligible and hence is omitted. The 0.4nH Ls of the 2.4GHz LNA can be implemented using a bond wire. The 53nH Lg can be implemented off-chip. To further reduce supply voltage, a low-threshold voltage transistor can be used if the option is available. For the purpose of demonstration, we have used a low-VT transistor in the 900MHz design. According to simulations of the inductively degenerated CS structure, the low-VT transistor has a threshold voltage
Figure 5. 9-element model of a spiral inductor.
The two LNAs are designed to give bandwidths that cover the 902-928 MHz and 2.4-2.483 GHz ISM bands, which are also used for Zigbee. The 900MHz and 2.4GHz circuits are biased respectively with 3.5mA and 5.6mA, yielding a set of performance specifications depicted in Fig. 6. Their values at the centre frequency are summarized in Table 2. TABLE 2 SUMMARY OF PERFORMANCE
VDD (V) Power (mW) S21 (dB) S12 (dB) S11, S22 (dB) NF (dB) Kf Input P1dB (dBm) IIP3 (dBm)
900MHz Band 0.45 1.6 12 -32 -19, -15 4.9 5 -20 -10
2.4GHz Band 0.5 2.8 13 -28 -18, -19 4.9 2.8 -18 -9
Both circuits satisfy the linearity and noise requirements of Zigbee. The NF of the 900MHz and 2.4GHz LNAs are respectively 5.5dB and 5dB over the entire band of interest, which leaves plenty of noise budget for the mixer and the rest of the receive chain. The stability factor Kf is above unity for both designs, indicating unconditional stability of the circuits [10]. A comparison with recently published lowpower LNAs is presented in Table 3.
14
11
12 S21 (dB)
S21 (dB)
13
9
V.
10
7
8 6
5 0.5
0.7
0.9 1.1 Frequency (GHz)
2
1.3
2.2
2.4 2.6 2.8 Frequency (GHz)
(a)
3
(b) 0
0
S11, S22 (dB)
S11, S22 (dB)
-5 -5 -10 -15
S11
0.5
0.7
1.1
-20 -25 S11 S22
1.3
2
2.2
Frequency (GHz)
2.6
2.8
3
REFERENCES
(d)
9
9
8
8
7
7 NF (dB)
NF (dB)
2.4
Frequency (GHz)
(c)
6 5
[1]
6 5
4
4
3
3
2
[2]
2 0.5
0.7
0.9
1.1
1.3
2
2.2
Frequency (GHz)
2.4
2.6
2.8
3
Frequency (GHz)
(e)
(f)
14
5
12
4.5
Stability Factor
Stability Factor
ACKNOWLEDGMENT The authors would like to thank Mr. Karim Allidina for his technical advice and insightful comments on the paper.
-15
-35 0.9
An approach for designing low-voltage low-power inductively degenerated CS LNAs is presented. This approach is particularly useful for wireless sensor network applications. Based on the proposed methodology, two LNAs are designed to meet the specification of the Zigbee standard. Simulation results show that good linearity, gain, and stability are simultaneously achieved by a singletransistor amplifier.
-10
-30
S22
-20
10 8 6 4
[3]
4
[4]
3.5 3 2.5
0.5
0.7
0.9
1.1
1.3
2
2.2
Frequency (GHz)
2.4
2.6
2.8
3
Frequency (GHz)
(g)
[5]
(h)
Figure 6. Performance of proposed LNAs with 900MHz and 2.4GHz designs on the left and right, respectively. (a) and (b): gain; (c) and (d): input and output reflection; (e) and (f): noise figure; (g) and (h): stability factor.
[6]
[7]
TABLE 3 COMPARISON WITH RECENT LOW-POWER LNAS Reference
This work
[11]*,**
[12]*
[13]*
[6]*
Process
90n CMOS
0.18µ CMOS
0.18µ CMOS
90n CMOS
0.18µ CMOS
VDD (V)
0.5
1
1
1.2
1.8
Power (mW)
2.8
0.26
3.2
9.7
6.5
S21 (dB)
13
13.6
16.4
13.3
7.1
NF (dB)
4.9
4.6
fc (GHz) 2.44 1 * Quoted numbers are measured results. ** Operates in the subthreshold region.
CONCLUSION
3.5
2.9
3
5.7
5.5
6
[8]
[9]
[10] [11]
[12] [13]
K. Iniewski, C. Siu, S. Kilambi, S. Khan, and P. Crowley, “Ultra-low power circuit and system design trade-offs for smart sensor network applications,” The 3rd Int. Conf. on Information and Communications Technology (ICICT), 2005. J.L. da Silva Jr., J. Shamberger, M. J. Ammer, C. Guo, S. Li, R. Shah, T. Tuan, M. Sheets, J. M. Rabaey, B. Nikolic, A. SangiovanniVincentelli, and P. Wright, “Design methodology for PicoRadio networks,” Proc. of Design, Automation and Test Conf. and Exhibition, 2001, pp. 314 – 323. S.S. Rajput and S.S. Jamuar, “Low voltage analog circuit design techniques,” IEEE Circuits and Systems Magazine, vol. 2, issue 1, 2002, pp. 24 – 42. A. Porret, T. Melly, D. Python, C.C. Enz, and E.A. Vittoz, “An ultralow power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver,” IEEE J. Solid-State Circuits, vol. 36, no. 3, Mar. 2001, pp. 452 – 466. T.H. Lin, W.J. Kaiser, and G.J. Pottie, “Integrated low-power communication system design for wireless sensor networks,” IEEE Comm. Magazine, vol. 42, issue 12, Dec. 2004, pp. 142 – 150. N.J. Oh, S.G. Lee., and J. Ko, “A CMOS 868/915 MHz direct conversion Zigbee single-chip radio,” IEEE Comm. Magazine, vol. 43, issue 12, Dec. 2005, pp. 100 – 109. W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. Pineda de Gyvez, D. J. Allstot, and E. Sanchez-Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,” IEEE Trans. on Circuits and Systems II, vol. 52, no. 12, Dec. 2005, pp. 875-879. T.K. Nguyen, C.H. Kim, G.J. Ihm, M.S. Yang, and S.G. Lee, “CMOS Low-noise amplifier design optimization techniques,” IEEE Trans. on Microwave Theory and Techniques, vol. 52, no. 5, May 2004. S.P. Voinigescu, T.O. Dickson, R. Beerkens, I. Khalid, and P. Westergaard, “A comparison of Si CMOS, SiGe BiCMOS, and InP HBT technologies for high-speed and millimeter-wave Ics,” Topical Meeting on Si Monolithic IC in RF Systems, Sep. 2004, pp. 111-114. J. Rollett, “Stability and power-gain invariants of linear twoports,” IRE Trans. on Circuit Theory, vol. 9, issue 1, Mar. 1962, pp. 29 – 32. B. G. Perumana, S. Chakraborty, C.-H. Lee, and J. Laskar, “A fully monolithic 260-µW, 1-GHz subthreshold low noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 6, Jun. 2005, pp. 428-430. Y.S. Wang and L.-H. Lu, “5.7GHz low-power variable-gain LNA in 0.18µm CMOS,” Electronics Letters, vol. 41, no. 2, Jan. 2005. D. Linten, S. Thijs, M. I. Natarajan, P. Wambacq, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Donnay, and S. Decoutere, “A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, Jul. 2005, , pp. 1434 – 1442.
I.
INTRODUCTION
Supply Power (mW)
Average Power Consumption (mW)
Wireless sensor networks have seen significant growth recently in applications such as health monitoring, factory automation, and security surveillance. A wireless sensor node is typically battery operated and demands a long battery life, which imposes stringent power requirements on the sensor node circuitry [1].
Figure 1. Energy-scavenging mechanisms and power consumption for networks with different sizes [1].
This research is funded by Natural Science and Engineering Research Council of Canada (NSERC). CAD tools are provided by Canadian Microelectronics Corporation (CMC) Microsystems.
An emerging class of self-sufficient wireless sensor nodes, such as the PicoRadio [2], is designed to scavenge energy from the environment. Sensor nodes are currently small enough to harness energy from vibration, heat, and the sun (see Fig. 1). These forms of energy usually provide only a limited voltage, necessitating circuits capable of operating from a low supply voltage [3]. For example, the output voltage of a single solar cell is 0.5V. Although low-voltage receivers with microwatt power consumption have been previously reported [4], these circuits have a high noise figure (NF) and low operating frequency. This work presents a methodology for the rapid and intuitive design of a low-voltage LNA given the power budget. Based on the design methodology, two LNAs operating at 900MHz and 2.4GHz are designed and simulated using 90nm CMOS technology to meet the specifications of IEEE 802.15.4 (Zigbee) as it is becoming a popular choice for implementing wireless sensor networks [5]. Zigbee requires a minimum input 1dB compression point (P1dB) of -20dBm and a minimum input-referred thirdorder intercept point (IIP3) of -10dBm [6]. Since Zigbee is intended for short-range applications, such as sensor networks, its NF specification is rather relaxed and the NF for the entire receiver can be as large as 19dB. This paper is organized as follows: Section II describes the inductively degenerated LNA circuit topology. Section III details a methodology used to rapidly choose circuit component values. Section IV shows simulation results of two LNAs and compares them with recently proposed lowpower circuits, and finally Section V concludes the paper. II.
CIRCUIT TOPOLOGY
There are various circuit topologies for LNAs. Each topology has its own strengths and weaknesses. For example, although the cascode topology provides high gain and good input-output isolation, a two-transistor stack is not optimal for operation at low supply voltages. On the other hand, achieving a high gain with a multi-stage topology can violate the power budget. Among single-stage amplifiers,
the common-gate topology provides good linearity and stability, but its NF is generally inferior to that of the common-source (CS) topology [7]. One LNA topology that is becoming increasingly popular is the inductively degenerated CS structure. This topology, shown in Fig. 2, allows for maximizing gain under a low power budget. For this LNA, the input and output are matched to 50Ω. Input matching is accomplished with a matching network. In this work, a T-match network, consisting of Lm, Cm, and Lg. The source-degenerated inductance Ls facilitates the input matching by modifying the real part of the input impedance. Rd is used to modify the real part of the output impedance to 50Ω. Ld is used to tune out the load capacitance and undesirable parasitic capacitances of the transistor at the center frequency fc to improve the gain.
VDD
Ld Lm Cm
Lg
Step 2: Calculate the drain current ID from the target power consumption (excluding biasing circuits) PDC and target supply voltage VDD, namely ID = PDC / VDD. W can then be readily calculated from the current density chosen in step 1 (assuming the use of minimum gate length L). Step 3: Determine the gate-to-source bias voltage VGS to give the ID calculated in step 2. ID can be plotted verses different values of VGS using a circuit simulator. From this plot, VGS can be chosen. If VGS takes on the value greater than VDD, either increase VDD, which increases power, or revisit step 1 to select another sub-optimal current density. Steps 1 through 3 are iterated until a good tradeoff between power and performance is found. Step 4: Obtain the gate-source capacitance Cgs and device transconductance gm at the operating point using a circuit simulator.
Rd
RFin
appear to be constant across various technology nodes and different foundries [9].
RFout Ls
Step 5: Design Lg and Ls by finding the estimate of the input impedance Zin, given by (1) through the use of the smallsignal model in Fig. 3. υRF and Rs model the antenna. For the purpose of this estimation, body effect and channel-length modulation are assumed to be small. Fig. 3 does not include Lm and Cm as they are added in the final step.
Figure 2. The inductively degenerated CS LNA with an input T-match.
Z in =
III.
DESIGN METHODOLOGY
A number of LNA design optimization techniques are well established such as classical noise matching (CNM), simultaneous noise and input matching (SNIM), powerconstrained simultaneous noise and input matching (PCSNIM), and power-constrained noise optimization (PCNO). A good overview of these techniques is presented in [8]. These techniques are rigorous, but often too complex for hand calculations. This section presents a methodology for the rapid and intuitive design of an inductively degenerated CS LNA given the power and supply voltage constraints. We assume that a circuit simulator is available. Step 1: Determine the current density that approximately minimizes NF and maximizes the unity power gain frequency fMAX of the device. The current density is given by ID/(W/L) where ID is the drain current and W and L are the width and the length of the device, respectively. Typically, L is chosen to be the minimum length of the technology, and therefore the current density can be expressed as ID/W. Minimum NF and maximum fMAX of a MOSFET occur when the current density of the device is 0.15mA/µm and 0.2mA/µm, respectively. The minimum NF and maximum fMAX as a function of ID/W are relatively flat in the proximity of their optimal points. Interestingly, these current densities
g L 1 + jω ( L s + L g ) + m s jωC gs C gs
(1)
Figure 3. Small-signal model for calculating input impedance.
Ls is determined by equating the real part of the input impedance to Rs, as in (2). ℜe{Z in } =
g m Ls = Rs = 50Ω C gs
(2)
Once Ls is found, Lg is obtained by setting the imaginary part of Zin to zero as in (3), yielding (4). ℑm{Z in } =
1
ωC gs
+ ω ( Ls + L g ) = 0
(3)
Lg =
1
ω 2 C gs
− Ls
(4)
Step 6: Choose Rd and Ld so that the output impedance Zout, given by (5). Z out = {[1 + ( g m + g mb ) jωLs ]ro + jωLs } || ( Rd + jωLd )
(5)
Zout is the complex conjugate of the load impedance. It is derived from the small-signal model of Fig. 4, with gmVgs, ro, and gmbVbs modeling the amplifying current component, output resistance, and body effect of the transistor, respectively. The values for gm, gmb, and ro are obtained using a circuit simulator.
around 280mV, about 60mV lower than the standard threshold voltage. IV.
SIMULATION RESULTS
Both LNAs are simulated in a 90nm CMOS process using SpectreRF with the BSIM3v3 device model. For more accurate results, the inductors are modeled by the 9-element model depicted in Fig. 5. L is the inductance, and C and R are the shunt capacitance and series resistance used to model wire parasitics. COX1 and COX2 model the capacitance between the metal used for the inductor and the substrate. Their values may not necessarily be the same in cases where there is a slight asymmetry in the spiral layout. RSUB and CSUB model the parasitics of the substrate.
Figure 4. Small-signal model for output impedance calculation.
Due to the gate-drain parasitic capacitance Cgd, which couples the input to the output, when tuning the output, the input becomes out of tune. The input and output impedances cannot be simultaneously matched to 50Ω, necessitating the inclusion of a matching network to provide additional degrees of freedom for matching. Two LNAs based on the above methodology are designed. The schematics and component values of the LNAs are depicted respectively in Fig. 2 and Table 1. TABLE 1 SUMMARY OF COMPONENT VALUES
VDD (V) ID (mA) W/L (µm) Ls (nH) Lg (nH) Ld (nH) Rd (Ω) Lm (nH) Cm (pF)
900MHz Band 0.45 3.5 100/0.1 (Not Required) 53 3 30 7.5 1.2
2.4GHz Band 0.5 5.6 100/0.1 0.4 15.6 3 30 3.6 1
The calculated value of Ls for the 900MHz LNA is negligible and hence is omitted. The 0.4nH Ls of the 2.4GHz LNA can be implemented using a bond wire. The 53nH Lg can be implemented off-chip. To further reduce supply voltage, a low-threshold voltage transistor can be used if the option is available. For the purpose of demonstration, we have used a low-VT transistor in the 900MHz design. According to simulations of the inductively degenerated CS structure, the low-VT transistor has a threshold voltage
Figure 5. 9-element model of a spiral inductor.
The two LNAs are designed to give bandwidths that cover the 902-928 MHz and 2.4-2.483 GHz ISM bands, which are also used for Zigbee. The 900MHz and 2.4GHz circuits are biased respectively with 3.5mA and 5.6mA, yielding a set of performance specifications depicted in Fig. 6. Their values at the centre frequency are summarized in Table 2. TABLE 2 SUMMARY OF PERFORMANCE
VDD (V) Power (mW) S21 (dB) S12 (dB) S11, S22 (dB) NF (dB) Kf Input P1dB (dBm) IIP3 (dBm)
900MHz Band 0.45 1.6 12 -32 -19, -15 4.9 5 -20 -10
2.4GHz Band 0.5 2.8 13 -28 -18, -19 4.9 2.8 -18 -9
Both circuits satisfy the linearity and noise requirements of Zigbee. The NF of the 900MHz and 2.4GHz LNAs are respectively 5.5dB and 5dB over the entire band of interest, which leaves plenty of noise budget for the mixer and the rest of the receive chain. The stability factor Kf is above unity for both designs, indicating unconditional stability of the circuits [10]. A comparison with recently published lowpower LNAs is presented in Table 3.
14
11
12 S21 (dB)
S21 (dB)
13
9
V.
10
7
8 6
5 0.5
0.7
0.9 1.1 Frequency (GHz)
2
1.3
2.2
2.4 2.6 2.8 Frequency (GHz)
(a)
3
(b) 0
0
S11, S22 (dB)
S11, S22 (dB)
-5 -5 -10 -15
S11
0.5
0.7
1.1
-20 -25 S11 S22
1.3
2
2.2
Frequency (GHz)
2.6
2.8
3
REFERENCES
(d)
9
9
8
8
7
7 NF (dB)
NF (dB)
2.4
Frequency (GHz)
(c)
6 5
[1]
6 5
4
4
3
3
2
[2]
2 0.5
0.7
0.9
1.1
1.3
2
2.2
Frequency (GHz)
2.4
2.6
2.8
3
Frequency (GHz)
(e)
(f)
14
5
12
4.5
Stability Factor
Stability Factor
ACKNOWLEDGMENT The authors would like to thank Mr. Karim Allidina for his technical advice and insightful comments on the paper.
-15
-35 0.9
An approach for designing low-voltage low-power inductively degenerated CS LNAs is presented. This approach is particularly useful for wireless sensor network applications. Based on the proposed methodology, two LNAs are designed to meet the specification of the Zigbee standard. Simulation results show that good linearity, gain, and stability are simultaneously achieved by a singletransistor amplifier.
-10
-30
S22
-20
10 8 6 4
[3]
4
[4]
3.5 3 2.5
0.5
0.7
0.9
1.1
1.3
2
2.2
Frequency (GHz)
2.4
2.6
2.8
3
Frequency (GHz)
(g)
[5]
(h)
Figure 6. Performance of proposed LNAs with 900MHz and 2.4GHz designs on the left and right, respectively. (a) and (b): gain; (c) and (d): input and output reflection; (e) and (f): noise figure; (g) and (h): stability factor.
[6]
[7]
TABLE 3 COMPARISON WITH RECENT LOW-POWER LNAS Reference
This work
[11]*,**
[12]*
[13]*
[6]*
Process
90n CMOS
0.18µ CMOS
0.18µ CMOS
90n CMOS
0.18µ CMOS
VDD (V)
0.5
1
1
1.2
1.8
Power (mW)
2.8
0.26
3.2
9.7
6.5
S21 (dB)
13
13.6
16.4
13.3
7.1
NF (dB)
4.9
4.6
fc (GHz) 2.44 1 * Quoted numbers are measured results. ** Operates in the subthreshold region.
CONCLUSION
3.5
2.9
3
5.7
5.5
6
[8]
[9]
[10] [11]
[12] [13]
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