Independent-gate and tied-gate FinFET SRAM Circuits: Design ...
Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability Sherif A. Tawfik, Zhiyu Liu, and Volkan Kursun Department of Electrical and Computer Engineering University of Wisconsin – Madison, Madison, Wisconsin 53706 - 1691 Abstract – Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today’s high performance microprocessors. Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. With the first independent-gate FinFET SRAM cell, one gate of each double-gate access and pull-up transistor is permanently disabled in order to enhance the data stability while achieving write-ability with minimum sized transistors. With the second independent-gate FinFET SRAM cell, the threshold voltages of the access transistors are dynamically adjusted during circuit operation in order to maximize the memory integration density without sacrificing the performance and stability. The read stability is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tiedgate FinFET SRAM cell with the same size transistors in a 32nm FinFET technology. Furthermore, with the IG-FinFET SRAM cells, the idle mode leakage power and the cell area are reduced by up to 36% and 11%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for comparable read stability in a 32nm FinFET technology. I. INTRODUCTION Scaling is the primary thrust behind the advancement of CMOS technology. The increased sub-threshold and gate-dielectric leakage currents have become the primary barriers against further CMOS technology scaling into the sub-45nm regime. The double-gate FinFET offers distinct advantages for simultaneously suppressing the sub-threshold and gate dielectric leakage currents as compared to the traditional single-gate MOSFETs. The two electrically coupled gates and the thin silicon body suppress the short-channel effects of a double-gate FinFET, thereby reducing the sub-threshold leakage current [1]. The suppressed short-channel effects and the enhanced gate control over the channel (lower sub-threshold swing) permit the use of a thicker gate oxide in a double-gate FinFET as compared to a conventional single-gate transistor. The gate oxide leakage current of a double-gate transistor is thereby significantly reduced. The thin body of a double-gate device is typically undoped or lightly doped. The carrier mobility is therefore enhanced and the device variations due to doping fluctuations are reduced in a double-gate MOSFET as compared to a single-gate bulk transistor. Successful fabrication of the tied-gate and the independent-gate FinFETs have been demonstrated [2]-[4]. The amount of embedded SRAM in modern micro-processors and systems-on-chips (SoCs) increases to meet the performance requirements in each new technology generation [5]. Lowering of supply and threshold voltages causes a significant degradation in SRAM cell data stability with the scaling of CMOS technology. Maintaining the data stability of SRAM cells is expected to become increasingly challenging as the device dimensions are scaled to the sub-45nm regime. In addition to the data stability issues, SRAM arrays are also an important source of leakage due to the enormous number of transistors and the low activity factor of the memory caches. The development of an SRAM cell that can provide higher data stability, enhanced integration density, and lower leakage power with the emerging FinFET technologies is highly desirable. Two six-transistor (6T) independent-gate FinFET SRAM cells with lower power consumption, higher integration density, and enhanced data stability are described in this paper. All of the six transistors of the independent-gate FinFET SRAM cells are sized minimum without sacrificing functionality and data stability. With the first independent-gate SRAM cell one gate of each access and pull-up FinFET is permanently disabled for enhanced read stability and write-ability. Alternatively, with the second independent-gate FinFET SRAM cell, the strength of the data access transistors is 978-1-4244-1847-3/07/$25.00 ©2007 IEEE
dynamically adjusted during circuit operation for better data stability. The read static noise margin is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied-gate FinFET SRAM cell with the same size transistors in a 32nm FinFET technology. Furthermore, the leakage power consumption of the two IG-FinFET SRAM cells is reduced by up to 36% as compared to a tied-gate FinFET SRAM cell that is sized for comparable static noise margin. The paper is organized as follows. The FinFET operation is described in Section II. The tied-gate and the independent-gate FinFET SRAM cells are presented in Section III. Data stability, power, delay, and area characteristics of the standard tied-gate and the independent-gate FinFET SRAM cells are compared in Section IV. Finally, conclusions are offered in Section V. II. FINFET DEVICE The physical and electrical characteristics of the FinFETs are presented in this section. The FinFETs used in this paper have a symmetrical structure, as shown in Fig. 1. The physical parameters used for MEDICI simulations in a 32nm FinFET technology are listed in Table I. VDD is 0.8 V. TABLE I. DEVICE PARAMETERS Parameter Value Channel length (L) 32 nm Effective channel length (Leff) 25.6 nm Fin thickness (tsi) 8 nm Fin height (Hfin) 32 nm Oxide thickness (tox) 1.6 nm Channel doping 1015 cm-3 Source / Drain doping 2 x 1020 cm-3 Gates work function (N-type FinFET) 4.5 eV Gates work function (P-type FinFET) 4.9 eV
Gate
Back Gate
tsi Source
Drain
Hfin
L
Drain Front Gate (b)
(a) Drain
Source
Front Gate
Insulator
Source tsi = 8nm
tox = 1.6nm
Back Gate Gate
25.6nm L = 32nm
Oxide Heavily doped Si Lightly doped Si
(c)
Fig. 1. FinFET structure. (a) 3D structure of a one-fin tied-gate FinFET. (b) 3D structure of a one-fin independent-gate FinFET. (c) Cross sectional top view of an independent-gate FinFET with a drawn channel length of 32nm.
The width of a FinFET is quantized due to the vertical gate structure. The fin height determines the minimum transistor width (Wmin). With the two gates of a single-fin FET tied together, Wmin is (1) Wmin = 2 × Hfin + tsi, where Hfin is the height of the fin and tsi is the thickness of the silicon body as shown in Fig. 1. Hfin is the dominant component of the transistor width since tsi is typically much smaller than Hfin. Since Hfin is fixed in a FinFET technology, multiple parallel fins are utilized to increase the width of a FinFET. The total physical transistor width (Wtotal) of a tied-gate FinFET with n parallel fins is IEEE ICM - December 2007
Wtotal = n × Wmin = n× (2 × Hfin + Tsi). (2) The two vertical gates of a FinFET can be separated by depositing oxide on top of the silicon fin, thereby forming an independent-gate FinFET as shown in Fig. 1b. An independent-gate FinFET (IG-FinFET) provides two different active modes of operation with significantly different current characteristics determined by the bias conditions of the two independent gates as shown in Fig. 2. In the Dual-Gate-Mode, the two gates are biased with the same signal. Alternatively, in the Single-Gate-Mode, one gate is biased with the input signal while the other gate is disabled (disabled gate: biased with VGND in an N-type FinFET and with VDD in a P-type FinFET). The two gates are strongly coupled in the Dual-Gate-Mode, thereby lowering the threshold voltage (Vth) as compared to the Single-Gate-Mode. The maximum drain current produced in the Dual-Gate-Mode is therefore 2.6 times higher as compared to the Single-Gate-Mode as shown in Fig. 2. The switched gate capacitance of the FinFET is also halved in the Single-Gate-Mode due to the disabled back gate. The unique Vth modulation aspect of IG-FinFETs through selective gate bias is exploited in this paper to enhance the SRAM data stability and integration density while lowering the static and dynamic power consumption with minimum sized transistors. 1.E-02
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Fig. 3. Two tied-gate FinFET SRAM cells. (a) SRAM-TG1: all six transistors are sized minimum. (b) SRAM-TG2: the pull-down transistors in the crosscoupled inverters have two fins. The size of each transistor is given as (number of fins × fin height)/channel length.
1.E-04 1.E-05 1.E-06 Vth = 0.25V
Vth = 0.4V
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0.2
0.4
0.6
0.8
VGS (V)
Fig. 2. Drain current characteristics of an N-type IG-FinFET. The drain-tosource voltage is 0.8V. T = 70 oC.
III. FinFET SRAM CELLS The design considerations for the reliable operation of the 6T FinFET SRAM circuits are provided in this section. The tied-gate FinFET SRAM cells are presented in Section III.A. The independent-gate FinFET (IG-FinFET) SRAM circuits are described in Section III.B. A. Standard TG-FinFET SRAM Cells The data stability of a memory circuit is most vulnerable to external noise during a read operation due to the intrinsic disturbance produced by the direct data-read-access mechanism of the standard 6T SRAM cells [10]. In order to maintain the read stability, the current conducting capability of the pull-down transistors must be higher as compared to the access transistors. Alternatively, for write ability, the current conducting capability of the access transistors must be stronger as compared to the pull-up transistors [5], [10]. Two tied-gate FinFET SRAM cells (SRAM-TG1 and SRAMTG2) with different sizes are considered in this paper, as shown in Fig. 3. All of the six transistors in SRAM-TG1 are sized minimum (one fin), as shown in Fig. 3a. A minimum sized SRAM cell is highly desirable for maximizing the memory integration density. For sufficient noise immunity and read stability, however, the pull-down transistors of the inverters in a tied-gate FinFET SRAM cell should have at least two fins, as illustrated in Fig. 3b. This enhancement in cell stability through transistor sizing, unfortunately, comes at a cost of significantly higher leakage power consumption and larger cell area. B. IG-FinFET SRAM Cells Two IG-FinFET 6T SRAM cells [5], [8], [11] are presented in this section. The idle mode leakage power consumption is reduced with the IG-FinFET SRAM cells while enhancing the data stability and the integration density as compared to the tied-gate FinFET SRAM circuits. All of the transistors in the two independent-gate SRAM cells have single fin (minimum width) as shown in Fig. 4.
With the first independent-gate FinFET SRAM cell (SRAM-IG1), the pull-down transistors in the cross-coupled inverters are tied-gate FinFETs. Alternatively, the pull-up transistors in the cross-coupled inverters and the access transistors are independent-gate FinFETs operating in the single-gate mode. The access transistors act as highVth devices. The disturbance caused by the direct-data-access mechanism during read operations is therefore suppressed without the need for increasing the sizes of the transistors within the crosscoupled inverters. The data stability is enhanced and the standby leakage power consumption is reduced while maintaining functionality (sufficient read SNM and write ability) with minimum sized transistors. With the second independent-gate FinFET SRAM cell (SRAMIG2) the transistors in the cross-coupled inverters are tied-gate FinFETs. Alternatively, the access transistors are independent-gate FinFETs. The unique Vth modulation aspect of IG-FinFETs through selective gate bias is exploited with the second IG-FinFET SRAM cell by dynamically tuning the read and write strength of the access transistors. SRAM-IG2 provides two separate data access mechanisms for the read and write operations. One gate of each access transistor is controlled by a read/write signal (RW). The second gate of each access transistor is controlled by a separate write signal (W), as shown in Fig. 4b. The operation of SRAM-IG2 is as follows. Both RW and W signals are maintained low in an un-accessed SRAM cell. During a read operation, RW signal transitions high while W is maintained low. Provided that Node1 stores “0”, BL is discharged through N3 and N1. Alternatively, provided that Node2 stores “0”, BLB is discharged through N4 and N2. The access transistors N3 and N4 act as high-Vth devices with weaker current conducting capability as compared to the tied-gate transistors N1 and N2 during a read operation with this technique. The current produced by the access transistors (with one gate disabled) is significantly reduced. The intrinsic data disturbance that occurs due to the direct-data-readaccess mechanism of the 6T SRAM cell topology is significantly suppressed with SRAM-IG2, thereby enhancing the read stability as compared to the standard tied-gate FinFET SRAM circuits. Alternatively, during a write operation, both RW and W transition high. The two access transistors N3 and N4 act as low-Vth devices conducting significantly higher current. The write speed of SRAMIG2 is, therefore, similar to the fastest standard tied-gate FinFET SRAM circuit shown in Fig. 3a. In order to write a “0” to Node1, the bitline (BL) and the complementary bitline (BLB) are discharged and charged, respectively. A “0” is forced into the IG-FinFET SRAM cell through N3. Alternatively, for writing a “0” to Node2, BL and BLB are charged and discharged, respectively. A “0” is forced onto Node2 through N4. IEEE ICM - December 2007
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(b) Fig. 4. The IG-FinFET SRAM cells. (a) SRAM-IG1. (b) SRAM-IG2. The size of each transistor is given as (number of fins × fin height)/channel length.
IV. SIMULATION RESULTS The read stability, leakage power, cell area, active mode power, and access delays of the two tied-gate FinFET SRAM cells (SRAMTG1 and SRAM-TG2) and the two independent-gate FinFET SRAM cells (SRAM-IG1 and SRAM-IG2) are compared in this section for a 32nm FinFET technology with MEDICI [9]. The transistor sizing of the SRAM cells are shown in Figs. 3 and 4. Active mode data are measured at 70°C. Leakage power consumption is measured at both 70°C and 27°C in order to evaluate the effectiveness of the independent-gate techniques for suppressing the leakage currents over the entire range of a typical memory temperature spectrum. A. Read Stability Static noise margin (SNM) is the metric used in this paper to characterize the read stability of the SRAM cells. The SNM is defined as the minimum DC noise voltage necessary to flip the state of an SRAM cell [6]. The read SNM of the four SRAM cells during a read operation are shown in Fig. 5. The disturbance induced at Node2 during a read operation is significantly suppressed by increasing the Vth of the access transistors with the two independent-gate techniques as compared to SRAM-TG1, despite the identical transistor sizing. Alternatively, with SRAM-TG2, the disturbance during read operations is reduced by increasing the size of the pull-down devices. The Node2 of SRAM-TG1, SRAM-TG2, SRAM-IG1, and SRAM-IG2 rises to 80mV, 32mV, 34mV, and 34mV, respectively, during a read operation. The read SNM of SRAM-IG1, SRAM-IG2, and SRAMTG2 is enhanced by 50%, 92%, and 64%, respectively, as compared to the SRAM-TG1. The SNM of SRAM-IG2 is enhanced by 17% as compared to SRAM-TG2. Note that the SNM of SRAM-IG2 is 28% higher as compared to SRAM-IG1 due to the more symmetric voltage transfer characteristics of the cross-coupled inverters with stronger pull-up devices in SRAM-IG2. SRAM-IG2 provides the highest data stability among the four SRAM circuits evaluated in this paper. 250
230mV 197mV
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200 150
70 oC
27 oC
15
10
5
0
N1
180mV 120mV
100
SRAM-TG1
SRAM-TG2
SRAM-IG1
SRAM-IG2
Fig. 6. The leakage power consumptions of the FinFET SRAM cells at 70°C and 27°C. C. Active Mode Power and Access Speed The junction and oxide capacitances of the access transistors attached to the bitlines are extracted for each FinFET SRAM cell. The length of the bitlines is estimated based on the cell layout height. A Π-type RC network that represents the bitline parasitics of a 256-bit SRAM column is attached to the FinFET SRAM circuits. The read delay is defined as the time required for developing a voltage difference of 200mV between BL and BLB. The normalized active mode power and delay of the four FinFET SRAM circuits are shown in Fig. 7. The four SRAM cells consume similar read and write power. SRAM-TG2 has the shortest read delay due to the stronger access and pull-down transistors as compared to SRAM-IG1 and SRAMIG2. The read delay of SRAM-IG1 and SRAM-IG2 is increased by 154% as compared to SRAM-TG2. SRAM-IG2 has the shortest write delay due to the strong access transistors during write operations and the lower internal node parasitic capacitances as compared to SRAM-TG2. The write delay is reduced by 12% with SRAM-IG2 as compared to SRAM-TG2. From an application point of view, SRAM-IG1 and SRAM-IG2 are the most attractive choices at the higher levels of caches for which the enhanced integration density and the lower leakage power consumption are the most important design criteria. Alternatively, for a speed-critical first level cache with a smaller amount of memory, the larger SRAM-TG2 cells can be more attractive due to the higher read speed with reasonable write speed and data stability. SRAM-TG1 is not a practical choice due to the unacceptably small read static noise margin. Note that SRAM-IG2 is not suitable for an interleaved memory architecture due to the unintentional read access to the inactive cells in a row during a write operation. Alternatively, SRAM-IG1 and SRAM-TG2 would successfully maintain the data stability with the popular interleaved cache architectures. 2.5 Normalized Delay and Power
W
B. Leakage Power Consumption The leakage power consumption of the SRAM cells at 70°C and 27°C are shown in Fig. 6. The leakage power of an SRAM cell is determined by the total effective transistor width that produces the leakage current. In SRAM-TG1, SRAM-IG1, and SRAM-IG2, all the transistors are sized minimum. SRAM-TG1, SRAM-IG1, and SRAM-IG2 therefore consume the lowest leakage power. Transistor sizing for enhanced data stability comes at a cost of significant additional leakage power with SRAM-TG2, as illustrated in Fig. 6. The leakage power consumed by SRAM-IG1 and SRAM-IG2 is reduced by 35% (36%) at 70°C (27°C) as compared to SRAM-TG2. Leakage Power Consumption (nW)
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1.5
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Read Power
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Fig. 7. The active mode power consumption and propagation delays of the SRAM circuits. For each SRAM circuit, the power and delay are normalized with respect to SRAM-TG1.
50 0 SRAM-TG1
SRAM-TG2
SRAM-IG1
SRAM-IG2
Fig. 5. The read SNM of the tied-gate and the independent-gate FinFET SRAM cells.
D. Process Variations The effect of process variations on the tied-gate and the independent-gate SRAM cells is evaluated in this section. 1500 IEEE ICM - December 2007
SRAM-IG1 / SRAM-IG2 Mean = 12.5 nW SD = 1.6 nW
Number of Samples
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Monte-Carlo simulations are run with Taurus-Medici using a PERL script. The channel length, the fin height, the fin thickness, and the gate oxide thickness are assumed to have independent Gaussian distributions with a 3σ variation of 10%. The distribution of the leakage power and the SNM for the tied-gate and the independentgate SRAM cells are shown in Figs. 8 and 9, respectively. The mean and the standard deviation (SD) of the leakage power are reduced by 35%, and 41%, respectively, with SRAM-IG1 and SRAM-IG2 as compared to SRAM-TG2. Furthermore, both SRAM-IG1 and SRAM-IG2 significantly enhance the mean SNM while suppressing the SNM standard deviation as compared to SRAM-TG1.
93.3% 300 WL
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100
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Fig. 8. Leakage power distributions of SRAM-TG2, SRAM-IG1, and SRAMIG2.
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Fig. 9. SNM distributions of the four FinFET SRAM cells.
E. SRAM Cell Area The thin-cell layouts of SRAM-TG1, SRAM-TG2, SRAM-IG1, and SRAM-IG are shown in Fig. 10. The pitch of the FinFET is assumed to be 6 times the fin thickness in the layouts. SRAM-TG1, SRAM-IG1, and SRAM-IG2 have the smallest area since all six transistors are sized minimum with only one fin. SRAM-TG2 has the largest area since the pull-down transistors in the cross-coupled inverters have two fins. The area of SRAM-TG2 is 12.5% larger than SRAM-IG1 and SRAM-IG2. V. CONCLUSIONS Two independent-gate FinFET SRAM cells are presented in this paper for simultaneously enhancing the read data stability and the memory integration density while reducing the standby mode power consumption. All of the six transistors of the IG-FinFET SRAM cells are sized minimum. The data access and the pull-up FinFETs are permanently operated in the Single-Gate-Mode with the first IGFinFET SRAM cell, thereby enhancing the static noise margin by up to 50% as compared to a tied-gate FinFET SRAM cell with the same size transistors. The threshold voltages of the access transistors are dynamically adjusted with the second IG-FinFET SRAM cell. Only one gate of each access transistor is enabled during a read operation for enhanced data stability. Alternatively, during a write operation both gates of each access transistor are enabled for achieving writeability. The read SNM is enhanced by 92% with the second IGFinFET as compared to a tied-gate FinFET SRAM cell with the same size transistors. Furthermore, the leakage power consumption of the two IG-FinFET SRAM cells is reduced by up to 36% as compared to a 6T tied-gate FinFET SRAM cell that is sized for comparable read static noise margin. The independent-gate FinFET techniques reduce the cell area by 11% as compared to a tied-gate FinFET SRAM circuit sized for comparable data stability.
W VGND
VDD
BLB
(d) Fig. 10. Layouts of the FinFET SRAM cells. (a) SRAM-TG1. (b) SRAMTG2. (c) SRAM-IG1. (d) SRAM-IG2. SRAM-TG1, SRAM-IG1, and SRAMIG2: 0.226 µm2. SRAM-TG2: 0.254 µm2. REFERENCES [1] E. Nowak et al., “Turning Silicon on Its Edge,” IEEE Circuits & Device Magazine, pp. 20-31, January/February 2004. [2] Meng-Hsueh Chiang et al., “Novel High-Density Low-Power Logic Circuit Techniques Using DG Devices,” IEEE Transactions on Electron Devices, Vol. 52, No. 10, pp. 2339–2342, October 2005 [3] Y. X. Liu et al., “4-Terminal FinFETs with High Threshold Voltage Controllability,” Proceedings of the IEEE Device Research Conference, Vol. 1, pp. 207–208, June 2004. [4] J. Kedzierski et al., “Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation,”Proceedings of the IEEE Electron Devices Meeting, pp. 247–250, December 2002. [5] V. Kursun, S. A. Tawfik, and Z. Liu, “Leakage-Aware Design of Nanometer SoC,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3231-3234, May 2007. [6] E. Seevinck, F. J. List, and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, October 1987. [7] M. Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” Proceedings of the IEEE Symposium on VLSI Circuits, pp. 288-291, June 2004. [8] B. Giraud et al., “A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3022-3025, May 2007. [9] Medici Device Simulator, Synopsys, Inc., 2006. [10] Z. Liu and V. Kursun, “High Read Stability and Low Leakage Cache Memory Cell,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2774-2777, May 2007. [11] O. Thomas, M. Reyboz, and M. Belleville, “Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS Technology,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2778-2781, May 2007.
IEEE ICM - December 2007
dynamically adjusted during circuit operation for better data stability. The read static noise margin is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied-gate FinFET SRAM cell with the same size transistors in a 32nm FinFET technology. Furthermore, the leakage power consumption of the two IG-FinFET SRAM cells is reduced by up to 36% as compared to a tied-gate FinFET SRAM cell that is sized for comparable static noise margin. The paper is organized as follows. The FinFET operation is described in Section II. The tied-gate and the independent-gate FinFET SRAM cells are presented in Section III. Data stability, power, delay, and area characteristics of the standard tied-gate and the independent-gate FinFET SRAM cells are compared in Section IV. Finally, conclusions are offered in Section V. II. FINFET DEVICE The physical and electrical characteristics of the FinFETs are presented in this section. The FinFETs used in this paper have a symmetrical structure, as shown in Fig. 1. The physical parameters used for MEDICI simulations in a 32nm FinFET technology are listed in Table I. VDD is 0.8 V. TABLE I. DEVICE PARAMETERS Parameter Value Channel length (L) 32 nm Effective channel length (Leff) 25.6 nm Fin thickness (tsi) 8 nm Fin height (Hfin) 32 nm Oxide thickness (tox) 1.6 nm Channel doping 1015 cm-3 Source / Drain doping 2 x 1020 cm-3 Gates work function (N-type FinFET) 4.5 eV Gates work function (P-type FinFET) 4.9 eV
Gate
Back Gate
tsi Source
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Hfin
L
Drain Front Gate (b)
(a) Drain
Source
Front Gate
Insulator
Source tsi = 8nm
tox = 1.6nm
Back Gate Gate
25.6nm L = 32nm
Oxide Heavily doped Si Lightly doped Si
(c)
Fig. 1. FinFET structure. (a) 3D structure of a one-fin tied-gate FinFET. (b) 3D structure of a one-fin independent-gate FinFET. (c) Cross sectional top view of an independent-gate FinFET with a drawn channel length of 32nm.
The width of a FinFET is quantized due to the vertical gate structure. The fin height determines the minimum transistor width (Wmin). With the two gates of a single-fin FET tied together, Wmin is (1) Wmin = 2 × Hfin + tsi, where Hfin is the height of the fin and tsi is the thickness of the silicon body as shown in Fig. 1. Hfin is the dominant component of the transistor width since tsi is typically much smaller than Hfin. Since Hfin is fixed in a FinFET technology, multiple parallel fins are utilized to increase the width of a FinFET. The total physical transistor width (Wtotal) of a tied-gate FinFET with n parallel fins is IEEE ICM - December 2007
Wtotal = n × Wmin = n× (2 × Hfin + Tsi). (2) The two vertical gates of a FinFET can be separated by depositing oxide on top of the silicon fin, thereby forming an independent-gate FinFET as shown in Fig. 1b. An independent-gate FinFET (IG-FinFET) provides two different active modes of operation with significantly different current characteristics determined by the bias conditions of the two independent gates as shown in Fig. 2. In the Dual-Gate-Mode, the two gates are biased with the same signal. Alternatively, in the Single-Gate-Mode, one gate is biased with the input signal while the other gate is disabled (disabled gate: biased with VGND in an N-type FinFET and with VDD in a P-type FinFET). The two gates are strongly coupled in the Dual-Gate-Mode, thereby lowering the threshold voltage (Vth) as compared to the Single-Gate-Mode. The maximum drain current produced in the Dual-Gate-Mode is therefore 2.6 times higher as compared to the Single-Gate-Mode as shown in Fig. 2. The switched gate capacitance of the FinFET is also halved in the Single-Gate-Mode due to the disabled back gate. The unique Vth modulation aspect of IG-FinFETs through selective gate bias is exploited in this paper to enhance the SRAM data stability and integration density while lowering the static and dynamic power consumption with minimum sized transistors. 1.E-02
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Fig. 3. Two tied-gate FinFET SRAM cells. (a) SRAM-TG1: all six transistors are sized minimum. (b) SRAM-TG2: the pull-down transistors in the crosscoupled inverters have two fins. The size of each transistor is given as (number of fins × fin height)/channel length.
1.E-04 1.E-05 1.E-06 Vth = 0.25V
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0.8
VGS (V)
Fig. 2. Drain current characteristics of an N-type IG-FinFET. The drain-tosource voltage is 0.8V. T = 70 oC.
III. FinFET SRAM CELLS The design considerations for the reliable operation of the 6T FinFET SRAM circuits are provided in this section. The tied-gate FinFET SRAM cells are presented in Section III.A. The independent-gate FinFET (IG-FinFET) SRAM circuits are described in Section III.B. A. Standard TG-FinFET SRAM Cells The data stability of a memory circuit is most vulnerable to external noise during a read operation due to the intrinsic disturbance produced by the direct data-read-access mechanism of the standard 6T SRAM cells [10]. In order to maintain the read stability, the current conducting capability of the pull-down transistors must be higher as compared to the access transistors. Alternatively, for write ability, the current conducting capability of the access transistors must be stronger as compared to the pull-up transistors [5], [10]. Two tied-gate FinFET SRAM cells (SRAM-TG1 and SRAMTG2) with different sizes are considered in this paper, as shown in Fig. 3. All of the six transistors in SRAM-TG1 are sized minimum (one fin), as shown in Fig. 3a. A minimum sized SRAM cell is highly desirable for maximizing the memory integration density. For sufficient noise immunity and read stability, however, the pull-down transistors of the inverters in a tied-gate FinFET SRAM cell should have at least two fins, as illustrated in Fig. 3b. This enhancement in cell stability through transistor sizing, unfortunately, comes at a cost of significantly higher leakage power consumption and larger cell area. B. IG-FinFET SRAM Cells Two IG-FinFET 6T SRAM cells [5], [8], [11] are presented in this section. The idle mode leakage power consumption is reduced with the IG-FinFET SRAM cells while enhancing the data stability and the integration density as compared to the tied-gate FinFET SRAM circuits. All of the transistors in the two independent-gate SRAM cells have single fin (minimum width) as shown in Fig. 4.
With the first independent-gate FinFET SRAM cell (SRAM-IG1), the pull-down transistors in the cross-coupled inverters are tied-gate FinFETs. Alternatively, the pull-up transistors in the cross-coupled inverters and the access transistors are independent-gate FinFETs operating in the single-gate mode. The access transistors act as highVth devices. The disturbance caused by the direct-data-access mechanism during read operations is therefore suppressed without the need for increasing the sizes of the transistors within the crosscoupled inverters. The data stability is enhanced and the standby leakage power consumption is reduced while maintaining functionality (sufficient read SNM and write ability) with minimum sized transistors. With the second independent-gate FinFET SRAM cell (SRAMIG2) the transistors in the cross-coupled inverters are tied-gate FinFETs. Alternatively, the access transistors are independent-gate FinFETs. The unique Vth modulation aspect of IG-FinFETs through selective gate bias is exploited with the second IG-FinFET SRAM cell by dynamically tuning the read and write strength of the access transistors. SRAM-IG2 provides two separate data access mechanisms for the read and write operations. One gate of each access transistor is controlled by a read/write signal (RW). The second gate of each access transistor is controlled by a separate write signal (W), as shown in Fig. 4b. The operation of SRAM-IG2 is as follows. Both RW and W signals are maintained low in an un-accessed SRAM cell. During a read operation, RW signal transitions high while W is maintained low. Provided that Node1 stores “0”, BL is discharged through N3 and N1. Alternatively, provided that Node2 stores “0”, BLB is discharged through N4 and N2. The access transistors N3 and N4 act as high-Vth devices with weaker current conducting capability as compared to the tied-gate transistors N1 and N2 during a read operation with this technique. The current produced by the access transistors (with one gate disabled) is significantly reduced. The intrinsic data disturbance that occurs due to the direct-data-readaccess mechanism of the 6T SRAM cell topology is significantly suppressed with SRAM-IG2, thereby enhancing the read stability as compared to the standard tied-gate FinFET SRAM circuits. Alternatively, during a write operation, both RW and W transition high. The two access transistors N3 and N4 act as low-Vth devices conducting significantly higher current. The write speed of SRAMIG2 is, therefore, similar to the fastest standard tied-gate FinFET SRAM circuit shown in Fig. 3a. In order to write a “0” to Node1, the bitline (BL) and the complementary bitline (BLB) are discharged and charged, respectively. A “0” is forced into the IG-FinFET SRAM cell through N3. Alternatively, for writing a “0” to Node2, BL and BLB are charged and discharged, respectively. A “0” is forced onto Node2 through N4. IEEE ICM - December 2007
VDD
VDD
P1
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BLB
(1x32)/32
(1x32)/32
P2
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Node2 (1x32)/32 N1
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(b) Fig. 4. The IG-FinFET SRAM cells. (a) SRAM-IG1. (b) SRAM-IG2. The size of each transistor is given as (number of fins × fin height)/channel length.
IV. SIMULATION RESULTS The read stability, leakage power, cell area, active mode power, and access delays of the two tied-gate FinFET SRAM cells (SRAMTG1 and SRAM-TG2) and the two independent-gate FinFET SRAM cells (SRAM-IG1 and SRAM-IG2) are compared in this section for a 32nm FinFET technology with MEDICI [9]. The transistor sizing of the SRAM cells are shown in Figs. 3 and 4. Active mode data are measured at 70°C. Leakage power consumption is measured at both 70°C and 27°C in order to evaluate the effectiveness of the independent-gate techniques for suppressing the leakage currents over the entire range of a typical memory temperature spectrum. A. Read Stability Static noise margin (SNM) is the metric used in this paper to characterize the read stability of the SRAM cells. The SNM is defined as the minimum DC noise voltage necessary to flip the state of an SRAM cell [6]. The read SNM of the four SRAM cells during a read operation are shown in Fig. 5. The disturbance induced at Node2 during a read operation is significantly suppressed by increasing the Vth of the access transistors with the two independent-gate techniques as compared to SRAM-TG1, despite the identical transistor sizing. Alternatively, with SRAM-TG2, the disturbance during read operations is reduced by increasing the size of the pull-down devices. The Node2 of SRAM-TG1, SRAM-TG2, SRAM-IG1, and SRAM-IG2 rises to 80mV, 32mV, 34mV, and 34mV, respectively, during a read operation. The read SNM of SRAM-IG1, SRAM-IG2, and SRAMTG2 is enhanced by 50%, 92%, and 64%, respectively, as compared to the SRAM-TG1. The SNM of SRAM-IG2 is enhanced by 17% as compared to SRAM-TG2. Note that the SNM of SRAM-IG2 is 28% higher as compared to SRAM-IG1 due to the more symmetric voltage transfer characteristics of the cross-coupled inverters with stronger pull-up devices in SRAM-IG2. SRAM-IG2 provides the highest data stability among the four SRAM circuits evaluated in this paper. 250
230mV 197mV
SNM (mV)
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180mV 120mV
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Fig. 6. The leakage power consumptions of the FinFET SRAM cells at 70°C and 27°C. C. Active Mode Power and Access Speed The junction and oxide capacitances of the access transistors attached to the bitlines are extracted for each FinFET SRAM cell. The length of the bitlines is estimated based on the cell layout height. A Π-type RC network that represents the bitline parasitics of a 256-bit SRAM column is attached to the FinFET SRAM circuits. The read delay is defined as the time required for developing a voltage difference of 200mV between BL and BLB. The normalized active mode power and delay of the four FinFET SRAM circuits are shown in Fig. 7. The four SRAM cells consume similar read and write power. SRAM-TG2 has the shortest read delay due to the stronger access and pull-down transistors as compared to SRAM-IG1 and SRAMIG2. The read delay of SRAM-IG1 and SRAM-IG2 is increased by 154% as compared to SRAM-TG2. SRAM-IG2 has the shortest write delay due to the strong access transistors during write operations and the lower internal node parasitic capacitances as compared to SRAM-TG2. The write delay is reduced by 12% with SRAM-IG2 as compared to SRAM-TG2. From an application point of view, SRAM-IG1 and SRAM-IG2 are the most attractive choices at the higher levels of caches for which the enhanced integration density and the lower leakage power consumption are the most important design criteria. Alternatively, for a speed-critical first level cache with a smaller amount of memory, the larger SRAM-TG2 cells can be more attractive due to the higher read speed with reasonable write speed and data stability. SRAM-TG1 is not a practical choice due to the unacceptably small read static noise margin. Note that SRAM-IG2 is not suitable for an interleaved memory architecture due to the unintentional read access to the inactive cells in a row during a write operation. Alternatively, SRAM-IG1 and SRAM-TG2 would successfully maintain the data stability with the popular interleaved cache architectures. 2.5 Normalized Delay and Power
W
B. Leakage Power Consumption The leakage power consumption of the SRAM cells at 70°C and 27°C are shown in Fig. 6. The leakage power of an SRAM cell is determined by the total effective transistor width that produces the leakage current. In SRAM-TG1, SRAM-IG1, and SRAM-IG2, all the transistors are sized minimum. SRAM-TG1, SRAM-IG1, and SRAM-IG2 therefore consume the lowest leakage power. Transistor sizing for enhanced data stability comes at a cost of significant additional leakage power with SRAM-TG2, as illustrated in Fig. 6. The leakage power consumed by SRAM-IG1 and SRAM-IG2 is reduced by 35% (36%) at 70°C (27°C) as compared to SRAM-TG2. Leakage Power Consumption (nW)
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Fig. 7. The active mode power consumption and propagation delays of the SRAM circuits. For each SRAM circuit, the power and delay are normalized with respect to SRAM-TG1.
50 0 SRAM-TG1
SRAM-TG2
SRAM-IG1
SRAM-IG2
Fig. 5. The read SNM of the tied-gate and the independent-gate FinFET SRAM cells.
D. Process Variations The effect of process variations on the tied-gate and the independent-gate SRAM cells is evaluated in this section. 1500 IEEE ICM - December 2007
SRAM-IG1 / SRAM-IG2 Mean = 12.5 nW SD = 1.6 nW
Number of Samples
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Monte-Carlo simulations are run with Taurus-Medici using a PERL script. The channel length, the fin height, the fin thickness, and the gate oxide thickness are assumed to have independent Gaussian distributions with a 3σ variation of 10%. The distribution of the leakage power and the SNM for the tied-gate and the independentgate SRAM cells are shown in Figs. 8 and 9, respectively. The mean and the standard deviation (SD) of the leakage power are reduced by 35%, and 41%, respectively, with SRAM-IG1 and SRAM-IG2 as compared to SRAM-TG2. Furthermore, both SRAM-IG1 and SRAM-IG2 significantly enhance the mean SNM while suppressing the SNM standard deviation as compared to SRAM-TG1.
93.3% 300 WL
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Fig. 8. Leakage power distributions of SRAM-TG2, SRAM-IG1, and SRAMIG2.
Number of Samples
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Fig. 9. SNM distributions of the four FinFET SRAM cells.
E. SRAM Cell Area The thin-cell layouts of SRAM-TG1, SRAM-TG2, SRAM-IG1, and SRAM-IG are shown in Fig. 10. The pitch of the FinFET is assumed to be 6 times the fin thickness in the layouts. SRAM-TG1, SRAM-IG1, and SRAM-IG2 have the smallest area since all six transistors are sized minimum with only one fin. SRAM-TG2 has the largest area since the pull-down transistors in the cross-coupled inverters have two fins. The area of SRAM-TG2 is 12.5% larger than SRAM-IG1 and SRAM-IG2. V. CONCLUSIONS Two independent-gate FinFET SRAM cells are presented in this paper for simultaneously enhancing the read data stability and the memory integration density while reducing the standby mode power consumption. All of the six transistors of the IG-FinFET SRAM cells are sized minimum. The data access and the pull-up FinFETs are permanently operated in the Single-Gate-Mode with the first IGFinFET SRAM cell, thereby enhancing the static noise margin by up to 50% as compared to a tied-gate FinFET SRAM cell with the same size transistors. The threshold voltages of the access transistors are dynamically adjusted with the second IG-FinFET SRAM cell. Only one gate of each access transistor is enabled during a read operation for enhanced data stability. Alternatively, during a write operation both gates of each access transistor are enabled for achieving writeability. The read SNM is enhanced by 92% with the second IGFinFET as compared to a tied-gate FinFET SRAM cell with the same size transistors. Furthermore, the leakage power consumption of the two IG-FinFET SRAM cells is reduced by up to 36% as compared to a 6T tied-gate FinFET SRAM cell that is sized for comparable read static noise margin. The independent-gate FinFET techniques reduce the cell area by 11% as compared to a tied-gate FinFET SRAM circuit sized for comparable data stability.
W VGND
VDD
BLB
(d) Fig. 10. Layouts of the FinFET SRAM cells. (a) SRAM-TG1. (b) SRAMTG2. (c) SRAM-IG1. (d) SRAM-IG2. SRAM-TG1, SRAM-IG1, and SRAMIG2: 0.226 µm2. SRAM-TG2: 0.254 µm2. REFERENCES [1] E. Nowak et al., “Turning Silicon on Its Edge,” IEEE Circuits & Device Magazine, pp. 20-31, January/February 2004. [2] Meng-Hsueh Chiang et al., “Novel High-Density Low-Power Logic Circuit Techniques Using DG Devices,” IEEE Transactions on Electron Devices, Vol. 52, No. 10, pp. 2339–2342, October 2005 [3] Y. X. Liu et al., “4-Terminal FinFETs with High Threshold Voltage Controllability,” Proceedings of the IEEE Device Research Conference, Vol. 1, pp. 207–208, June 2004. [4] J. Kedzierski et al., “Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation,”Proceedings of the IEEE Electron Devices Meeting, pp. 247–250, December 2002. [5] V. Kursun, S. A. Tawfik, and Z. Liu, “Leakage-Aware Design of Nanometer SoC,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3231-3234, May 2007. [6] E. Seevinck, F. J. List, and J. Lohstroh, “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, October 1987. [7] M. Yamaoka et al., “Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology,” Proceedings of the IEEE Symposium on VLSI Circuits, pp. 288-291, June 2004. [8] B. Giraud et al., “A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3022-3025, May 2007. [9] Medici Device Simulator, Synopsys, Inc., 2006. [10] Z. Liu and V. Kursun, “High Read Stability and Low Leakage Cache Memory Cell,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2774-2777, May 2007. [11] O. Thomas, M. Reyboz, and M. Belleville, “Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS Technology,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2778-2781, May 2007.
IEEE ICM - December 2007
