Robust FinFET SRAM design based on dynamic back-gate voltage ...
Microelectronics Reliability 54 (2014) 2604–2612
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Robust FinFET SRAM design based on dynamic back-gate voltage adjustment Behzad Ebrahimi a, Ali Afzali-Kusha a,⇑, Hamid Mahmoodi b a b
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran Department of Electrical and Computer Engineering, San Francisco State University, CA, USA
a r t i c l e
i n f o
Article history: Received 3 October 2013 Received in revised form 22 March 2014 Accepted 29 April 2014 Available online 24 May 2014 Keywords: SRAM Dynamic back-gate design FinFET Robust Low power
a b s t r a c t In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction To maximize the density, SRAM cells are realized using minimum sized transistors in each technology [1]. On the other hand, the shrinkage of the technology feature size to nano-scale regime has adversely impacted the SRAM yield due to uncertainty in the device parameters induced by process variations. In addition, in this regime, short channel effects more severely deteriorate the performance of the SRAM cells. To overcome these problems, new device structures may be invoked. Among them, double gate transistors have superior short channel characteristics and better immunity to process variations when compared to conventional bulk CMOS transistors. These originate from the use of a thin silicon film, lightly doped channel, and two gates for a better channel control [2]. Among double gate transistors, FinFET structure is one of the promising devices thanks to similarity of its fabrication process to that of the planar bulk CMOS [3]. Two gates of FinFET can be tied together or used independently. The independent use of gates offers dynamic or static performance tunability yielding a great
⇑ Corresponding author. Tel.: +98 21 8208 4920; fax: +98 21 8877 8690. E-mail address: [email protected] (A. Afzali-Kusha). http://dx.doi.org/10.1016/j.microrel.2014.04.015 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
flexibility for designers [4]. With a clever configuration, independent-gate structure may be used to merge series or parallel transistors in the logic reducing the number of transistors improving some of the characteristics (please see e.g., [5,6]). For example, in Ref. [5], the proposed gates with independent-gate implementations have lower input capacitance, number of Fins, and power consumption when compared to conventional tied-gate implementations while achieving about the same performance. In addition, recent advances in the manufacturing process permit the selective cut of the upper part of the gate allowing the implementation of both independent-gate and tied-gate double gate FinFETs on the same die [7]. This feature can also be utilized for the performance improvement of SRAM cells based on FinFETs. These improvements include both stability and static power improvement. In Ref. [8], the authors proposed connecting the back-gate of access transistors to the adjacent bit-cell storage nodes. Using this technique, the access transistor corresponding to the node storing ‘‘0’’ (‘‘1’’) becomes weak (strong) during the read (write) operation and the cell stability is increased using the built-in feedback [8]. In Ref. [9], a write wordline connected to the back-gate of pull-up transistors was used to weaken the transistors during the write operation, improving the write margin. In Ref. [10], an approach for finding the static back-gate voltages which maximize
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the yield has been proposed. The fixed back-gate voltages were obtained for read, write, and hold modes of SRAM operation. Finally, the use of back-gate voltage for the leakage reduction has been proposed in Ref. [11]. It should be noted that the successful fabrication of FinFET SRAM cells using both independent and tied-gate devices has been reported in Ref. [12]. In this work, we propose the use of back-gates of pull-up transistors to enhance the stability of a SRAM cell. The voltages of these back-gates are determined such that the read and write stabilities are maximized and the static power is minimized. We also propose a circuit for the dynamic biasing of the pull-up transistors. To minimize the area overhead, the circuit for generating the dynamic voltages is shared among all the cells in a column. The contributions of this paper are as follows: Proposing a new dynamic back-gate biasing for improving SRAM cell performance metrics in double gate FinFET technology. Presenting a comparative analysis of the read SNM, read current, write margin and standby power of the proposed design versus the schemes in Refs. [8,9], and demonstrating significant improvements in write margin and standby power while maintaining competitive read SNM and read current. Providing a comparative analysis of process variation sensitivity of the proposed scheme versus the recently proposed schemes, proving significantly enhanced write margin yield and a competitive and satisfactory read SNM yield enabling us to lower the minimum operating voltage. The rest of this paper is organized as follows. The FinFET structure is described in Section 2. In Section 3, the SRAM design considerations are reviewed. Section 4 discusses the existing dynamic back-gate voltage schemes while Section 5 describes the proposed dynamic back-gate voltage technique. The results are discussed in Section 6 while Section 7 concludes the paper.
Table 1 Device parameters used for simulations. Gate length, Lg (nm) Equivalent oxide thickness, toxe (Å) Body thickness, tsi (nm) Channel doping, Nbody (#/cm3) Fin height, Hfin (nm) Gate work function (eV)
22 11 15 1016 30 4.6
saturation for transport was used. The mobilities were calibrated using the experimental data given in Ref. [16]. The results of the I–V characteristics obtained from these simulations were in good agreement with the results reported in Ref. [9]. Also, it should be noted that, in (1 0 0) wafers, for typical channel orientation of (1 1 0), the difference between the electron and hole mobilities decreases compared to that of the conventional bulk case. Thus, the midgap work function of 4.6 eV for both nFET and pFET results in comparable strengths for both nFET and pFET. Using this work function for both n- and p-type transistors with equal sizes, the threshold voltage of about 0.4 V was obtained for both devices (results of device simulations). The strength ratio of pFET–nFET was also obtained to be about 0.75. One also should notice that the use of the high aspect ratio for the FinFETs makes using different work functions (along the sidewalls of the fins) for n- and p-type transistors difficult [9,17]. Consequently, in this work, similar to [9], we assumed single gate material for both nFET and pFET (It is imperative to mention that this assumption should not affect the comparative results presented in Section 6). For the SRAM cell characteristics, we performed mixed mode device/circuit simulations. It should be noted that in order to have a compact layout, we chose single fin devices. 3. SRAM design considerations In this section, we describe different operational modes of the conventional 6T SRAM cell shown in Fig. 2 along with the desired back-gate voltage of the transistors.
2. FinFET structure In FinFET devices, the gates on either side of the fin can be tied together or electrically isolated to allow an independent biasing scheme. This is achieved by removing the gate material in the region directly on top of the fin [7,13]. In the tied-gate operating mode (Fig. 1a), the two gates are biased together while in the independent-gate operating mode (Fig. 1b), they are biased independently. We use a 22 nm FinFET technology with device parameters similar to those used in Ref. [9]. The parameters are listed in Table 1. The terminal contact resistances, which were included in the simulations, were calculated based on the model presented in Ref. [14]. In this paper, the results were obtained using 2D Sentaurus Device Simulator [15] with the temperature T = 300 K. In the simulations, the density gradient model along with high field
3.1. Read state Consider the case that VL = ‘‘1’’ and VR = ‘‘0’’ (see Fig. 2). During the read operation, bitlines are precharged to Vdd and the wordline is set to Vdd. This operation raises VR to a value that is determined by the voltage division between NR and AR. This voltage is denoted by Vread. If Vread becomes greater than the trip point voltage of PL and NL (Vtrip), the value of the cell flips and a destructive read occurs. The stability in the read state is measured by the read static noise margin (SNM) [18]. To increase the read SNM, NR should be stronger than AR in order to decrease Vread. Also, the leakage current of PR which is in the OFF state may increase the Vread value decreasing the read
Fig. 1. Schematic structure of double gate FinFETs (a) tied-gate mode and (b) independent-gate mode.
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Read Write Hold
Fig. 2. A conventional 6T SRAM cell.
stability. To minimize the leakage, the absolute value of the threshold voltage of PR should be high. On the other hand, PL and AL should be stronger than NL to increase Vtrip. Based on this discussion, the desired back-gate voltages of the transistors from the read stability perspective are Vdd, 0, Vdd, 0, Vdd, and 0 for NR, AR, PR, PL, AL, and NL, respectively. It is worth noting that, in addition to Vtrip and Vread, the gain of the inverter transfer characteristics also impacts the read SNM (higher gains would result in higher read SNMs) [18]. Another parameter in the read state is the access time for which the read current is used as a metric [9]. The read current is the current of the access transistor (AR) whose source is at Vread. From this aspect, if NR and AR become strong and PR becomes weak, the read current increases decreasing the access time [10]. While this parameter is not included in our optimization in favor of the read stability, it will be included in our comparative study. 3.2. Write state While writing a ‘‘1’’ into the cell that stores ‘‘0’’ (Fig. 2), the voltage of BL is set to 0 and that of BR is set to Vdd, and the wordline is asserted. In this case, the node L is discharged through AL. If VL, which is determined by the voltage division between PL and AL, becomes lower than the trip point voltage of PR and NR, the write operation will be accomplished. The stability in the write state is measured by the write margin [19]. To increase the write margin, AL should be stronger than PL and Vtrip of PR–NR should be high. Hence, PR and AR should be stronger than NR. Also, the leakage current of NL which is in the OFF state may help the discharge of the node L increasing the write margin. To maximize the leakage, the threshold voltage of NL should be low. Thus, the desired back-gate voltages of the transistors from the write stability perspective are Vdd, Vdd, Vdd, 0, Vdd, and 0 for AL, PL, NL, PR, AR, and NR, respectively. 3.3. Hold state In most of the time, no read or write operation is performed placing the array cells in the hold mode where the bitlines are precharged to Vdd and the wordline is set to 0. In this mode, the most important parameter is the standby power [20]. In the case of Fig. 2, the transistors AR, PR, and NL are in the subthreshold regions of operation, and hence, their subthreshold currents contribute to the static power. In this state, to minimize the static power, the absolute value of the threshold voltage of these transistors should be high. Hence, the desired back-gate voltages of the transistors from the static power view are 0, Vdd, and 0 for AR, PR, and NL, respectively. The back-gate voltages of other transistors are not important. To summarize our discussion, in Table 2, the bitline voltages and the desired back-gate voltage for different transistors in the SRAM cell of Fig. 2 are listed. In this table, BPX, BNX and BAX are used to resemble the back-gate voltages of the pull-up (P),
BP0
BP1
BN0
BN1
BA0
BA1
BL0
BL1
Vdd 0 Vdd
0 Vdd NI
Vdd 0 NI
0 Vdd 0
0 Vdd 0
Vdd Vdd NI
Vdd Vdd Vdd
Vdd 0 Vdd
pull-down (N), and access (A) transistors, respectively, in the side storing the logic X which can be ‘‘0’’ or ‘‘1’’. Also, BLX denotes the bitline voltage near the node storing the logic X. NI stands for not important. 4. Existing dynamic back-gate voltage techniques The FinFET device has a superior short channel control compared to the planar bulk transistor. However, to have acceptable read and write stabilities in the SRAM cells implemented using these devices, the number of fins of the transistors should be increased (e.g., increasing the fin numbers of pull-down (access) for increasing read (write) stability [9]). Another approach for increasing the stabilities is to use the back-gate of transistors [8– 11]. Using the back-gate, one also can lower the static power. This approach has been invoked in Refs. [8,9] where the back-gate of the access transistors are connected to the adjacent bit-cell storage nodes as shown in Fig. 3. This scheme is referred to as ABG structure here. For the ABG SRAM cell, the read SNM increases compared to the structure which is only composed of tied-gate FinFETs, referred to as DG structure here. In the ABG cell, however, the read current degrades owing to the zero back-gate bias of the discharging access transistor. In the ABG cell, the desired back-gate voltages for the read stability and static power (see Table 2) are applied to the back-gates of all six transistors of the SRAM cell. It has been shown that the read SNMs of the ABG and DG SRAM cells may become equal if the work functions of the gates in the DG structure are increased compared to those in the ABG structure [9]. In this case, the write margin also improves in the ABG cell as compared to that of the DG structure especially at low Vdd’s due to the stronger access transistor [9]. For the area comparison, the layouts for the structures are shown in Fig. 4 where we used the design rules for the FinFET technology reported in Ref. [21]. Similar to [9], we assumed the SOI FinFET technology where n-well to p-well spacing rules can be avoided and the nFET and pFET drains can be directly connected. Compared to increasing the number of fins, the approach connecting the back-gate of access transistors to the adjacent bit-cell storage nodes has the advantage of not increasing the area [9,22]. This is also evident from Fig. 4b and c where there is no extra contact for the back-gate. More specifically, there is one contact for the back-gate of the access transistor and the gates of the pull-down and pull-up transistors.
Fig. 3. Schematics of a 6T SRAM cell where the back-gates of the access transistors are connected to the adjacent bit-cell storage nodes for providing the dynamic feedback (ABG).
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Fig. 4. Layout for 6T SRAM cells (a) DG, (b) ABG with tied-gate pull-up and (c) ABG with independent-gate pull-up.
The authors in Ref. [9] suggested connecting the back-gate of pull-up transistors to a Write Wordline (WWL). In this method, whose layout is shown in Fig. 4c, the area increases by about 12.5% compared to that of the ABG structure with tied-gate pullup due to the additional contact space required for WWL [22]. This line was assumed to route horizontally in a different metal layer than that of the WL [9]. The WWL has been suggested to be set to Vdd during the write state and 0 or an intermediate value during the read and hold states [9]. One of the problems with this approach, as implied from Table 2, is that same back-gate voltage bias is used for both BP0 and BP1 in read and hold states. Assuming NI can be 0, the desired back-gate voltages are Vdd for BP0 and 0 for BP1. Therefore, to have one fixed value for both pull-up transistors in both the operation modes, we should choose a compromising value. In Ref. [9], the authors suggested 0.48 V for a technology of 22 nm gate length when the supply voltage varied from 0.4 V to 1.2 V. Moreover, the approach in Ref. [9] sets the back-gate bias of both pull-up transistors to Vdd during the write mode irrespective of the data being written to the cell, whereas based on the results presented in Table 2, it is most optimal for write margin enhancement to set the back-gate of the pull-up on the node storing logic ‘‘0’’ (BP0) at zero bias and that of the pull-up on the node storing logic ‘‘1’’ (BP1) at Vdd. Additionally, the implementation of this approach requires some circuitry (which has some overhead) for the generation and distribution of the fixed voltage along with setting the WWL to Vdd during the write and 0.48 V during the read and hold states.
5. Proposed dynamic back-gate voltage technique In this work, we suggest a technique in which the back-gate voltages of the pull-up transistors are dynamically adjusted. The values of the voltages are set based on the desired values of each state. Table 2 suggests that, in the hold state, the back-gate voltage of the pull-up transistor whose drain stores logic ‘‘0’’ should be Vdd and the back-gate voltage of the other pull-up transistor is not important. Hence, in our design the back-gates are precharged to Vdd (as is done for the bitlines) to have the highest threshold
voltage for the pull-up transistors. In the write state, the pull-up transistor whose drain stores logic ‘‘1’’, should be weak, and hence, its back-gate voltage should be set to Vdd. In this case, the other pull-up transistor should be strong to have a high Vtrip, and hence, its back-gate voltage should be set to 0. The bias, however, turns on the OFF state pull-up with the back-gate during the write operation increasing the power consumption. First, note that, the use of the midgap work function metals for the gates yields high threshold voltage transistors with rather small ON current (high resistance). Second, turning on the pull-up helps the write operation reducing its required operation time. Thus, the time that we are required to apply this bias is reduced. Table 2 also suggests in the read state, the pull-up transistor whose drain stores logic ‘‘1’’ should have the back-gate voltage of 0. The back-gate voltage of the other pull-up transistor should be Vdd. These values are complement of the desired values for the write operation. Hence, we cannot fix the connection of the back-gates of the pull-up transistors to the corresponding storage nodes to avoid detrimental degradation of the write stability. Since the stored value is not known a priori, we need to choose a fixed value for the back-gate voltages of the pull-up transistors regardless of the stored value. In this work, we propose to set the value based on maximizing the read SNM. We also leave pull-down transistors in the tied-gate mode, because it is the favorable mode from read stability and static power perspective as shown in Table 2. Also, write margin sensitivity to pull-down threshold voltage is much smaller compared to those of access and pull-up transistors [19]. The back-gates of the access transistors are also connected to the adjacent storage nodes (similar to the other ABG structures). This is the favorable case from read stability and static power perspectives as shown in Table 2. To set the desired back-gate voltages of the pull-up transistors based on the operation state of the SRAM cell, we propose the circuit diagram for the SRAM array which is shown in Fig. 5. In the proposed scheme, the pull-up back-gate biases are data dependent and set based on the input data to be written to the cell using an added write driver circuitry as shown in Fig. 5. In this case, proper values of the bitlines and pull-up back-gate voltages should be set
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Fig. 6. Nominal write margin (CWLM) versus Vdd for different SRAM structures.
It should be noted that SRAM stability and performance could also be improved using other means such as 6T SRAM cells with two-fin pull-down or 8T cell structures. Our design, however, would outperform these structures. In the case of the former cell, using sizing to improve the read stability worsens the write stability and vice versa (see e.g., [9]). For example, the two-fin pull-down approach increasing the area by 16.6% [9] improves the read stability while deteriorates the write stability by about the same amount (see Fig. 6 in Ref. [9]), and hence, may not be a good choice for improving both of the read and write stabilities especially at lower supply voltages where the write stability is degraded more. In addition, it increases the power. On the other hand, increasing the number of transistors, as is the case for the latter cell structure, increases the area considerably. For example, the 8T SRAM cell has 30% more area compared to the former structure [28]. The area penalty of our design is about one third of that of the 8T SRAM cell. Fig. 5. The proposed array design for dynamically biasing the back-gate of pull-up transistors.
before the wordline is activated, while in the case of the conventional SRAM cell, the setting of the voltages are performed only for the bitlines. Since the interconnect used for the back-gate voltage has the same length (interconnect dominant capacitance [22]) as that of the bitline, the setting of the voltages should be performed at about the same time. Sharing the added circuitry among the cells of each column makes its area and power overhead negligible. The extra write driver typically induces a very small area penalty [23] (about 0.5% for an array of 128 cells per column [24]). The hold state biasing of the back-gates, which lowers the standby power as well, is performed by an extra precharge circuit, as shown in Fig. 5. As a rule of thumb, the area overhead of the extra precharge circuit should be much less than that of the write driver circuit [25]. An optimum pre-generated back-gate voltage bias (Vopt) for the read state is applied to the back-gate lines via a pair of nMOS switches (Fig. 5). These nMOS sizes are determined to achieve the required voltage swing on the back-gate lines from the precharged value of Vdd set during the hold state (initial state) to the optimum value (Vopt) required for the read operation, within the read cycle. Therefore, these nMOS switches are expected to occupy less area than that of the extra write driver due to the lower voltage swing required on the back-gate lines and the longer time available for this voltage swing to be completed. The optimum back-gate voltage bias (Vopt) can also be generated by a low Vdd voltage reference (e.g., [26,27]). As the voltage reference is shared for the whole chip, its area and power penalty is negligible [26,27]. It should be noted that the layout of the proposed SRAM cell remains similar to Fig. 4c. The difference is that the pull-up backgate lines are assumed to route vertically (on contrary to horizontally in the approach of [9]) in a different metal layer than that of the bitlines to eliminate the cross talk noise to the parallel bitlines.
6. Results and discussion In this part, we study the efficacy of the proposed scheme by comparing its performance with those of the DG structure, the ABG structure proposed in Ref. [8] where the independent-gate mode is used only for the access transistors, the ABG structure with back-gate voltage of 0 and Vdd for the pull-up transistors during the read/hold and write states, respectively [9], and the ABG structure with back-gate voltage of 0.48 V and Vdd for the pull-up transistors during the read/hold and write states, respectively [9]. In the case of the DG structure, to increase the read stability, we increase the gate work function to 4.75 eV. By increasing the gate work function further, the read stability decreases instead of increasing due to the severe subthreshold leakage current increase of the pMOS pull-up as discussed in Section 3. Next, we present the static characteristics of one SRAM cell in each structure with the corresponding backgate bias conditions. 6.1. Nominal study First, we consider the write stability metric (write margin) for which different definitions have been suggested in the literature [19]. In this work, we use the difference between Vdd and the minimum wordline voltage, namely, combined wordline margin (CWLM), that can cause a successful write operation as a metric [19]. It has been shown that this metric has a Gaussian distribution in the presence of process variations [19,29]. The write margin of different structures versus the supply voltage is depicted in Fig. 6. The results reveal that our proposed structure has the highest write margin among different structures even more than the ABG structure, in which the back-gate of the pull-up transistors are connected to Vdd. It should be noticed out the proposed structure has an acceptable write margin even for Vdd’s as low as 0.5 V
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while the area is compact due to using FinFETs with one fin. Additionally, to avoid the half-selected issue for the cells in the selected row, it has been suggested that the whole row is simultaneously written [30]. Using this approach, in this work, we assume 8 cells (one byte) in each row for each SRAM sub-block [31]. On the other hand, the half-selected cells in the same column as that of the cell being written have their wordlines deactivated. Hence, during the short time of the write operation, the storage node voltages of the half-selected cells do not change considerably yielding high halfselected cell stability. As discussed in Section 3.3, the static power is the most important metric in the hold state. In Fig. 7, we compare the static powers of the structures. The results demonstrate that the DG structure has about one order of magnitude higher static power than that of the ABG structure with tied-gate mode pull-up. This may be justified by noting that, due to the higher gate work function in the DG structure, the pull-up transistor has higher subthreshold leakage current. In the case of the independent-gate mode pull-up, if the back-gate voltages of the pull-up transistors are set to 0, the subthreshold leakage current will become unacceptably high. On the other hand, if the compromising value which considers the read stability and static power is used for the back-gates of the pullup transistors, the subthreshold leakage will increase considerably at high supply voltages. The results indicate that our proposed structure and ABG structure with tied-gate pull-up transistors have the least static power. The reason for the lower static power for these structures is that the back-gate voltage of the OFF state pull-up transistor is Vdd resulting in a higher absolute value for the threshold voltage. In Fig. 8, we have plotted the nominal (without considering process variation impacts) read SNM versus the supply voltage for all the structures. As evident from the figure, for the supply voltages larger than 0.6 V, the ABG structure [8] has a higher read SNM than that of the DG structure in spite of increasing the gate work function for the DG structure. Using the independent-gate mode operation for the pull-up transistors decreases the read SNM. This may be attributed to the smaller transconductance of independent-gate FinFET compared to that of the tied-gate one [4]. The smaller transconductance leads to a smaller gain for the inverter determining the transfer characteristic and consequently the read SNM becomes smaller [18]. If the back-gate of the pull-up transistors is connected to the ground, the read SNM decreases due to the increase in the subthreshold leakage current of the pull-up transistors, especially at higher supply voltages. The back-gate of the pullup transistors may be connected to an intermediate fixed voltage. As an example, this value was set to 0.48 V in Ref. [9]. In this case, however, the read SNM decreases due to the smaller transconductance of the independent-gate pull-up transistors and also decrease in the value of Vtrip owing to weak pull-up at lower supply voltages. In the case of our proposed design, the back-gate voltages for the read and hold states can be different. Using the proposed
circuit shown in Fig. 5, we can choose an optimum back-gate voltage based on the supply voltage for the read state. We used simulations to find the optimum values for the maximum read SNM by sweeping the back-gate voltage between 0 and Vdd for each supply voltage. The optimum values considering the read stability are listed in the inset of Fig. 8. Due to the process variations, the optimum value for a given Vdd may vary. To study the sensitivity of the read SNM to the optimum value, we changed the optimum values for all the supply voltages studied in this work by 20% and measured the read SNM. The results showed at most 2.5% change in the value of the SNM. Hence, the preciseness of the voltage generator is not of a critical concern. The results indicate that the read stability of our design is higher than those of the ABG structures with fixed pull-up back-gate voltages of 0 and 0.48 V for the supply voltages between 0.4 V and 0.9 V while lower than those of the DG and ABG structures for the supply voltages between 0.7 V and 0.9 V. The lower read stability may be attributed to the less transconductance of the independent-gate pull-up transistor with respect to the tied-gate one which causes better stability for the DG and ABG structures at high supply voltages. In addition, the read SNM of the proposed technique, similar to that of the ABG [8], is the highest for the supply voltages from 0.4 V to 0.6 V. The read currents for different structures are compared in Fig. 9. As is evident from the figure, the read currents of the ABG structures (including our proposed structure) are more than that of DG structure for lower Vdd’s. This may be attributed to the fact that the lower gate work function effect (lower threshold voltage) dominates the zero back-gate bias of the access transistor (higher threshold voltage) in the case of the ABG structures. At higher supply voltages, the read current of the ABG structure, in which the back-gates of the pull-up transistors are connected to ground, decreases because the subthreshold leakage of the OFF state pullup transistor increases. This raises the value of Vread (the source voltage of the access transistor) leading to a lower overdrive voltage for the (discharging) access transistor, and hence, a smaller read current. At the highest supply voltage (Vdd = 0.9 V), the read
Fig. 7. Nominal static power versus Vdd for different SRAM structures.
Fig. 9. Nominal read current versus Vdd for different SRAM structures.
Fig. 8. Nominal read SNM versus Vdd for different SRAM structures.
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currents of the ABG structures are lower than that of the DG structure because the zero back-gate bias dominates the lower gate work function. This implies that the use of the independent-gate structure only slightly lowers the read speed for the highest Vdd. It should be noted that the midgap work function values used in this work are more appropriate for low power applications. For example, the read current values are very close to those of a SRAM array fabricated using a 28 nm low power SOC process [32]. 6.2. Study of process variation effect Now, we study the impact of the process variation on the SRAM cell structures discussed in this work. In addition to channel length and silicon thickness variations due to the line-edge roughness, there are other sources of variations including random dopant fluctuations as well as work function, fin height, and oxide thickness variations. As the experimental results presented in e.g., [33,34] show, the random dopant fluctuation can be ignored due to the fact that the body is lightly doped. Also, the work function variation can be suppressed by using gate-last process where amorphous metal gate are deposited after the high-temperature annealing and activation process steps [35]. On the other hand, since the real values of fin height and oxide thickness are not determined by the lithography resolution, their variations should not be critical (please see e.g., [33]). The actual values of the channel length and silicon thickness are dictated by the lithography resolution and hence their variations are of key concern (see e.g., [9,10,33]). It should be mentioned that including other variation sources may be readily performed by extending the analysis given below. For this study, we assume that the channel length and silicon thickness have the variations such that the standard variations, namely, rtsi and rLg, respectively, are 7% Lg [9]. The variation of read SNM and CWLM may be very well modeled by a normal distribution [19,29]. Therefore, we assume that these metrics have Gaussian distributions which are functions of twelve random variables. Denoting the metric by y, we may write
y ¼ f ðx1 ; . . . ; x12 Þ;
ð1Þ
where x1,. . ., x12 are the Gaussian random variables with the averages of g1, . . ., g12 and standard deviations of r1,. . ., r12. These twelve random variables are channel lengths and silicon thicknesses of six transistors of the SRAM cell. Hence, we can use the following expression to find their statistical characteristics using bivarient Taylor Series as [36]:
ly ¼ f ðg1 ; . . . ; g12 Þ
ð2Þ
!2 12 X @f ¼ r2i @xi gi i¼1
ð3Þ
r
2 y
Here, we used the cell sigma, the yield figure of merit of the SRAM, which is defined as the minimum amount of variation needed to cause a read or write failure. The cell sigma is given by the mean (l) divided by the standard deviation (r) [9]. Nowadays, six-sigma (6r) yield or larger is required for large SRAM arrays [9]. In Fig. 10, we have plotted the read SNM and CWLM cell sigma yields versus the supply voltage obtained from simulations and using Eqs. (2) and (3). It should be noted that ly’s in Eq. (2) were approximated by their nominal values which were presented in Figs. 6 and 8. Also, since the variations of the read SNM and CWLM were linearly proportional to the variations of the random variables (xi) [19,29], the derivatives in (3), of/oxi, were easily found by using the metric values through the simulations at some values of xi near the nominal values (gi). As is evident from the figure, our proposed structure and the ABG structure with pull-up back-gate voltages equal to 0 have over six-sigma read yield for supply
Fig. 10. (a) Read SNM and (b) CWLM cell sigma yield versus the supply voltage for different SRAM cell structures.
voltages as low as 0.5 V. This is due to the high nominal read SNM and less sensitivity to device parameters especially at low supply voltages. As expected the write yield degrades considerably for low supply voltages. Among these structures, only our proposed structure has over six-sigma write yield down to Vdd equal to 0.55 V (0.15 V below the minimum of the other structures). For our structure, at Vdd = 0.5 V, the write margin cell sigma is slightly lower than six. To have six-sigma write yield, one may lower gate work function of the transistors to 4.57 eV to increase the writability. This work function tuning makes the access (as well as pull-down) nMOS stronger while making the pull-up pMOS weaker. These strength changes improves the write yield such that both the read and write cell sigma yields become above six. In this case, the read current increases by 56% while the static power also increases by 47% compared to the case of no work function tuning. The static power is still 23% lower than that of the structure (without work function tuning) when the supply voltage of 0.6 V is used. Therefore, if a proper work function tuning can be performed, one may use Vdd = 0.5 V to lower the static power (as well as the dynamic power due to a lower supply voltage). With similar work function tuning, we used the gate work function of 4.61 eV, 4.54 eV, 4.49 eV, and 4.61 eV for the DG, ABG, ABG with pull-up back-gate voltage of 0 during the read/hold states, and ABG with pull-up back-gate voltage of 0.48 V during the read/hold states, respectively. This resulted in the minimum operating voltage of 0.65, 0.65, 0.6, and 0.7 V, respectively. These numbers suggest that the proposed structure still could operate with the supply voltage which is 0.1 V lower than that of the other structures. Next, we consider the SNM cell sigma yield for the half-selected cells in the same column of the selected cell shown in Fig. 11. For the read operation (Fig. 11b), the yields for all the structures are very high. In the case of the write operation, while the half-selected disturb is the worst for our proposed structure, it is still higher than six. It should be noted that as the wordlines of half-selected cells are inactive, the storage node voltages of the half-selected cells do not have enough time for changing their values for threatening
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the supply voltage are plotted in Fig. 12. As is observed from the results the proposed structure consumes more dynamic energy compared to those of the other structures. This is due to the more voltage switchings of the lines connected to the back-gates of the pull-up transistors. Since the main contributor to the total power of SRAM is the static power [20,33], the larger dynamic energy for the proposed structure may not be considered as major shortcoming. It should be noticed that since our structure could operate at lower minimum supply voltages, the dynamic power may be lowered by lowering the supply voltage wherever the corresponding speed reduction can be tolerated. The supply voltage reduction also lowers the static power. 7. Conclusions
Fig. 11. Half-selected SNM cell sigma during (a) write and (b) read versus the supply voltage for different SRAM cell structures.
the reliability (SNM, which is a static parameter, is a pessimistic metric) (see e.g., [37]). 6.3. Dynamic energy consumption In this part, we study the energy consumptions of the structures per read and write operations. In the structures considered in this work, the main sources of the dynamic power consumption are the voltage changes of the long wordline, bitlines, and pull-up backgate lines. The increased static currents of the cells during the read and write operations (including those induced due to the application of the back-gate biases) can be neglected as the cells are in the hold state most of the time while the read and write times are very short. To perform this study, we assumed a SRAM block with 8 cells in each row [31] and 128 cells in each column [24] and the line capacitance was taken as 0.25 fF/lm to account for the dominant interconnect capacitance as well as the drain/gate contact capacitance [22]. Hence, we included the additional parasitic capacitances for the pull-up back-gate lines as well as the bitlines. The results for the energy consumptions of all the structures versus
We proposed a dynamic back-gate design for the pull-up transistors of SRAM cells to increase the cell stability during the read and write states while decreasing the static power during hold state. The optimization was performed by dynamically adjusting the voltages of the back-gates of the pull-up transistors in the cell. The voltages were determined in order to have maximum stability during the read and write states and minimum static power during the hold state. During the write operation, we used an extra write driver which sets the desired back-gate voltage of pull-up transistors to considerably increase the write margin. During the hold state, to decrease the static power, the back-gates were precharged to the supply voltage using an extra precharge circuit. The read stability degradation was prevented using proper back-gate voltages generated using nMOS switches. To reduce the area and power overheads, the added circuitry was shared for each column. Also, the proposed structure had the highest write margin among the structures considered in this work. The half-selected issue for the cells in the selected row has been avoided by writing the whole row simultaneously. The half-selected cells in the same column of the selected cell had high stability during read and write operations. Therefore, the proposed cell may be used for the applications where writing the whole row simultaneously is possible. For the cell with single fin FinFETs, the minimum operating voltage for six-sigma yield obtained to be about 0.55 V which was 0.15 V lower than that of a recently proposed structure. In addition, our structure had much less static power. The minimum operating voltage of the proposed structure could be lowered to 0.5 V by some work function tuning while the minimum operating voltage for all other structure was 0.6 V or higher using similar work function tunings. Acknowledgement The first two authors acknowledge the financial support by the Iranian National Science Foundation (INSF). References
Fig. 12. (a) Write energy for one byte (solid lines) and read energy (dotted lines) versus Vdd for different SRAM structures.
[1] Agarwal K, Nassif S. The impact of random device variation on SRAM cell stability in sub-90-nm CMOS technologies. IEEE Trans Very Large Scale Integr (VLSI) Syst 2008;16(1):86–97. [2] Neudeck GW. An overview of double-gate MOSFETs. Proc BGIM 2003:214–7. [3] Tang SH, et al. FinFET-a quasiplanar double-gate MOSFET. In: Proc ISSCC Dig. Techn. Papers; 2001. p. 118–9. [4] Datta A et al. Modeling and circuit synthesis for independently controlled double gate FinFET devices. IEEE Trans Comput-Aided Des Integr Circuits Syst 2007;26(11):1957–66. [5] Rostami M, Mohanram K. Dual-Vth independent-gate FinFETs for low power logic circuits. IEEE Trans Comput-Aided Des 2011;30(3):337–49. [6] Tawfik SA, Kursun V. Low-power and compact sequential circuits with independent-gate FinFETs. IEEE Trans Electron Dev 2008;55(1):60–70. [7] Liu YX et al. Cointegration of high-performance tied-gate three-terminal FinFETs and variable threshold-voltage independent-gate four-terminal
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[22] Kang M et al. Asymmetric independent-gate MOSFET SRAM for high stability. IEEE Trans Electron Dev 2011;58(9):2959–65. [23] Ney A et al. A design-for-diagnosis technique for SRAM write drivers. Proc Date 2008:1480–5. [24] Chang MF, Chen YC, Chen CF. A 0.45-V 300-MHz 10T flow through SRAM with expanded write/read stability and speed-area-wise array for sub-0.5-V chips. IEEE Trans Circuits Syst II, Exp Briefs 2010;57(12):980–5. [25] Cheng SP, Huang SY. A low-power SRAM for Viterbi decoder in wireless communication. IEEE Trans Consum Electron 2008;54(2):290–5. [26] Jing X et al. A 0.5 V nanoWatt CMOS voltage reference with two high PSRR outputs. Proc IEEE Int Symp Circuits Syst 2012:2837–40. [27] Annema A et al. A sub-1V bandgap voltage reference in 32 nm FinFET technology. Proc IEEE Int Solid-State Circuits Conf Dig Tech Pap 2009:332–3. [28] Chang L et al. Stable SRAM cell design for the 32 nm node and beyond. Symp.VLSI Technol Dig Tech Pap 2005:128–9. [29] Wang J, Calhoun BH. Minimum supply voltage and yield estimation for large SRAMs under parametric variations. IEEE Trans Very Large Scale Integr (VLSI) Syst 2011;19(11):2120–5. [30] Chun KC, Jain P, Lee JH, Kim CH. A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power ondie caches. IEEE J Solid-State Circuits 2011;46(6):1495–505. [31] Chang IJ, Kim J, Park SP, Roy K. A 32 kb 10T subthreshold SRAM array with bitinterleaving and differential read scheme in 90 nm CMOS. Proc IEEE Int SolidState Circuits Conf (ISSCC) Dig Tech Pap 2008:388–9. [32] Wang J et al. Non-Gaussian distribution of SRAM read current and design impact to low power memory using voltage acceleration method. Symp VLSI Technol (VLSIT) 2011:220–1. [33] Lu D, Niknejad A, Hu C, Lin C. Compact modeling in variations of finFET sram cells. Des Test Comput 2010;27(2):45–50. [34] Endo K et al. Variability analysis of TiN metal-gate FinFETs. IEEE Electron Dev Lett 2010;31(6):546–8. [35] Matsukawa T et al. Suppressing Vt and Gm variability of FinFETs using amorphous metal gates for 14 nm and beyond. Proc IEEE IEDM 2012:8.2.1–4. [36] A. Papoulis Probability, random variables and stochastic process. New York: McGraw-Hill; 2002. [37] Lee ZC, Ho KM, Kong ZH, Kim TT. NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells. Proc IEEE Int Soc Des Conf 2012:200–3.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Robust FinFET SRAM design based on dynamic back-gate voltage adjustment Behzad Ebrahimi a, Ali Afzali-Kusha a,⇑, Hamid Mahmoodi b a b
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran Department of Electrical and Computer Engineering, San Francisco State University, CA, USA
a r t i c l e
i n f o
Article history: Received 3 October 2013 Received in revised form 22 March 2014 Accepted 29 April 2014 Available online 24 May 2014 Keywords: SRAM Dynamic back-gate design FinFET Robust Low power
a b s t r a c t In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction To maximize the density, SRAM cells are realized using minimum sized transistors in each technology [1]. On the other hand, the shrinkage of the technology feature size to nano-scale regime has adversely impacted the SRAM yield due to uncertainty in the device parameters induced by process variations. In addition, in this regime, short channel effects more severely deteriorate the performance of the SRAM cells. To overcome these problems, new device structures may be invoked. Among them, double gate transistors have superior short channel characteristics and better immunity to process variations when compared to conventional bulk CMOS transistors. These originate from the use of a thin silicon film, lightly doped channel, and two gates for a better channel control [2]. Among double gate transistors, FinFET structure is one of the promising devices thanks to similarity of its fabrication process to that of the planar bulk CMOS [3]. Two gates of FinFET can be tied together or used independently. The independent use of gates offers dynamic or static performance tunability yielding a great
⇑ Corresponding author. Tel.: +98 21 8208 4920; fax: +98 21 8877 8690. E-mail address: [email protected] (A. Afzali-Kusha). http://dx.doi.org/10.1016/j.microrel.2014.04.015 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
flexibility for designers [4]. With a clever configuration, independent-gate structure may be used to merge series or parallel transistors in the logic reducing the number of transistors improving some of the characteristics (please see e.g., [5,6]). For example, in Ref. [5], the proposed gates with independent-gate implementations have lower input capacitance, number of Fins, and power consumption when compared to conventional tied-gate implementations while achieving about the same performance. In addition, recent advances in the manufacturing process permit the selective cut of the upper part of the gate allowing the implementation of both independent-gate and tied-gate double gate FinFETs on the same die [7]. This feature can also be utilized for the performance improvement of SRAM cells based on FinFETs. These improvements include both stability and static power improvement. In Ref. [8], the authors proposed connecting the back-gate of access transistors to the adjacent bit-cell storage nodes. Using this technique, the access transistor corresponding to the node storing ‘‘0’’ (‘‘1’’) becomes weak (strong) during the read (write) operation and the cell stability is increased using the built-in feedback [8]. In Ref. [9], a write wordline connected to the back-gate of pull-up transistors was used to weaken the transistors during the write operation, improving the write margin. In Ref. [10], an approach for finding the static back-gate voltages which maximize
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the yield has been proposed. The fixed back-gate voltages were obtained for read, write, and hold modes of SRAM operation. Finally, the use of back-gate voltage for the leakage reduction has been proposed in Ref. [11]. It should be noted that the successful fabrication of FinFET SRAM cells using both independent and tied-gate devices has been reported in Ref. [12]. In this work, we propose the use of back-gates of pull-up transistors to enhance the stability of a SRAM cell. The voltages of these back-gates are determined such that the read and write stabilities are maximized and the static power is minimized. We also propose a circuit for the dynamic biasing of the pull-up transistors. To minimize the area overhead, the circuit for generating the dynamic voltages is shared among all the cells in a column. The contributions of this paper are as follows: Proposing a new dynamic back-gate biasing for improving SRAM cell performance metrics in double gate FinFET technology. Presenting a comparative analysis of the read SNM, read current, write margin and standby power of the proposed design versus the schemes in Refs. [8,9], and demonstrating significant improvements in write margin and standby power while maintaining competitive read SNM and read current. Providing a comparative analysis of process variation sensitivity of the proposed scheme versus the recently proposed schemes, proving significantly enhanced write margin yield and a competitive and satisfactory read SNM yield enabling us to lower the minimum operating voltage. The rest of this paper is organized as follows. The FinFET structure is described in Section 2. In Section 3, the SRAM design considerations are reviewed. Section 4 discusses the existing dynamic back-gate voltage schemes while Section 5 describes the proposed dynamic back-gate voltage technique. The results are discussed in Section 6 while Section 7 concludes the paper.
Table 1 Device parameters used for simulations. Gate length, Lg (nm) Equivalent oxide thickness, toxe (Å) Body thickness, tsi (nm) Channel doping, Nbody (#/cm3) Fin height, Hfin (nm) Gate work function (eV)
22 11 15 1016 30 4.6
saturation for transport was used. The mobilities were calibrated using the experimental data given in Ref. [16]. The results of the I–V characteristics obtained from these simulations were in good agreement with the results reported in Ref. [9]. Also, it should be noted that, in (1 0 0) wafers, for typical channel orientation of (1 1 0), the difference between the electron and hole mobilities decreases compared to that of the conventional bulk case. Thus, the midgap work function of 4.6 eV for both nFET and pFET results in comparable strengths for both nFET and pFET. Using this work function for both n- and p-type transistors with equal sizes, the threshold voltage of about 0.4 V was obtained for both devices (results of device simulations). The strength ratio of pFET–nFET was also obtained to be about 0.75. One also should notice that the use of the high aspect ratio for the FinFETs makes using different work functions (along the sidewalls of the fins) for n- and p-type transistors difficult [9,17]. Consequently, in this work, similar to [9], we assumed single gate material for both nFET and pFET (It is imperative to mention that this assumption should not affect the comparative results presented in Section 6). For the SRAM cell characteristics, we performed mixed mode device/circuit simulations. It should be noted that in order to have a compact layout, we chose single fin devices. 3. SRAM design considerations In this section, we describe different operational modes of the conventional 6T SRAM cell shown in Fig. 2 along with the desired back-gate voltage of the transistors.
2. FinFET structure In FinFET devices, the gates on either side of the fin can be tied together or electrically isolated to allow an independent biasing scheme. This is achieved by removing the gate material in the region directly on top of the fin [7,13]. In the tied-gate operating mode (Fig. 1a), the two gates are biased together while in the independent-gate operating mode (Fig. 1b), they are biased independently. We use a 22 nm FinFET technology with device parameters similar to those used in Ref. [9]. The parameters are listed in Table 1. The terminal contact resistances, which were included in the simulations, were calculated based on the model presented in Ref. [14]. In this paper, the results were obtained using 2D Sentaurus Device Simulator [15] with the temperature T = 300 K. In the simulations, the density gradient model along with high field
3.1. Read state Consider the case that VL = ‘‘1’’ and VR = ‘‘0’’ (see Fig. 2). During the read operation, bitlines are precharged to Vdd and the wordline is set to Vdd. This operation raises VR to a value that is determined by the voltage division between NR and AR. This voltage is denoted by Vread. If Vread becomes greater than the trip point voltage of PL and NL (Vtrip), the value of the cell flips and a destructive read occurs. The stability in the read state is measured by the read static noise margin (SNM) [18]. To increase the read SNM, NR should be stronger than AR in order to decrease Vread. Also, the leakage current of PR which is in the OFF state may increase the Vread value decreasing the read
Fig. 1. Schematic structure of double gate FinFETs (a) tied-gate mode and (b) independent-gate mode.
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B. Ebrahimi et al. / Microelectronics Reliability 54 (2014) 2604–2612 Table 2 Bitline voltages and desired back-gate voltages of transistors in different states from stability (read and write) and static power (hold) perspective.
Read Write Hold
Fig. 2. A conventional 6T SRAM cell.
stability. To minimize the leakage, the absolute value of the threshold voltage of PR should be high. On the other hand, PL and AL should be stronger than NL to increase Vtrip. Based on this discussion, the desired back-gate voltages of the transistors from the read stability perspective are Vdd, 0, Vdd, 0, Vdd, and 0 for NR, AR, PR, PL, AL, and NL, respectively. It is worth noting that, in addition to Vtrip and Vread, the gain of the inverter transfer characteristics also impacts the read SNM (higher gains would result in higher read SNMs) [18]. Another parameter in the read state is the access time for which the read current is used as a metric [9]. The read current is the current of the access transistor (AR) whose source is at Vread. From this aspect, if NR and AR become strong and PR becomes weak, the read current increases decreasing the access time [10]. While this parameter is not included in our optimization in favor of the read stability, it will be included in our comparative study. 3.2. Write state While writing a ‘‘1’’ into the cell that stores ‘‘0’’ (Fig. 2), the voltage of BL is set to 0 and that of BR is set to Vdd, and the wordline is asserted. In this case, the node L is discharged through AL. If VL, which is determined by the voltage division between PL and AL, becomes lower than the trip point voltage of PR and NR, the write operation will be accomplished. The stability in the write state is measured by the write margin [19]. To increase the write margin, AL should be stronger than PL and Vtrip of PR–NR should be high. Hence, PR and AR should be stronger than NR. Also, the leakage current of NL which is in the OFF state may help the discharge of the node L increasing the write margin. To maximize the leakage, the threshold voltage of NL should be low. Thus, the desired back-gate voltages of the transistors from the write stability perspective are Vdd, Vdd, Vdd, 0, Vdd, and 0 for AL, PL, NL, PR, AR, and NR, respectively. 3.3. Hold state In most of the time, no read or write operation is performed placing the array cells in the hold mode where the bitlines are precharged to Vdd and the wordline is set to 0. In this mode, the most important parameter is the standby power [20]. In the case of Fig. 2, the transistors AR, PR, and NL are in the subthreshold regions of operation, and hence, their subthreshold currents contribute to the static power. In this state, to minimize the static power, the absolute value of the threshold voltage of these transistors should be high. Hence, the desired back-gate voltages of the transistors from the static power view are 0, Vdd, and 0 for AR, PR, and NL, respectively. The back-gate voltages of other transistors are not important. To summarize our discussion, in Table 2, the bitline voltages and the desired back-gate voltage for different transistors in the SRAM cell of Fig. 2 are listed. In this table, BPX, BNX and BAX are used to resemble the back-gate voltages of the pull-up (P),
BP0
BP1
BN0
BN1
BA0
BA1
BL0
BL1
Vdd 0 Vdd
0 Vdd NI
Vdd 0 NI
0 Vdd 0
0 Vdd 0
Vdd Vdd NI
Vdd Vdd Vdd
Vdd 0 Vdd
pull-down (N), and access (A) transistors, respectively, in the side storing the logic X which can be ‘‘0’’ or ‘‘1’’. Also, BLX denotes the bitline voltage near the node storing the logic X. NI stands for not important. 4. Existing dynamic back-gate voltage techniques The FinFET device has a superior short channel control compared to the planar bulk transistor. However, to have acceptable read and write stabilities in the SRAM cells implemented using these devices, the number of fins of the transistors should be increased (e.g., increasing the fin numbers of pull-down (access) for increasing read (write) stability [9]). Another approach for increasing the stabilities is to use the back-gate of transistors [8– 11]. Using the back-gate, one also can lower the static power. This approach has been invoked in Refs. [8,9] where the back-gate of the access transistors are connected to the adjacent bit-cell storage nodes as shown in Fig. 3. This scheme is referred to as ABG structure here. For the ABG SRAM cell, the read SNM increases compared to the structure which is only composed of tied-gate FinFETs, referred to as DG structure here. In the ABG cell, however, the read current degrades owing to the zero back-gate bias of the discharging access transistor. In the ABG cell, the desired back-gate voltages for the read stability and static power (see Table 2) are applied to the back-gates of all six transistors of the SRAM cell. It has been shown that the read SNMs of the ABG and DG SRAM cells may become equal if the work functions of the gates in the DG structure are increased compared to those in the ABG structure [9]. In this case, the write margin also improves in the ABG cell as compared to that of the DG structure especially at low Vdd’s due to the stronger access transistor [9]. For the area comparison, the layouts for the structures are shown in Fig. 4 where we used the design rules for the FinFET technology reported in Ref. [21]. Similar to [9], we assumed the SOI FinFET technology where n-well to p-well spacing rules can be avoided and the nFET and pFET drains can be directly connected. Compared to increasing the number of fins, the approach connecting the back-gate of access transistors to the adjacent bit-cell storage nodes has the advantage of not increasing the area [9,22]. This is also evident from Fig. 4b and c where there is no extra contact for the back-gate. More specifically, there is one contact for the back-gate of the access transistor and the gates of the pull-down and pull-up transistors.
Fig. 3. Schematics of a 6T SRAM cell where the back-gates of the access transistors are connected to the adjacent bit-cell storage nodes for providing the dynamic feedback (ABG).
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Fig. 4. Layout for 6T SRAM cells (a) DG, (b) ABG with tied-gate pull-up and (c) ABG with independent-gate pull-up.
The authors in Ref. [9] suggested connecting the back-gate of pull-up transistors to a Write Wordline (WWL). In this method, whose layout is shown in Fig. 4c, the area increases by about 12.5% compared to that of the ABG structure with tied-gate pullup due to the additional contact space required for WWL [22]. This line was assumed to route horizontally in a different metal layer than that of the WL [9]. The WWL has been suggested to be set to Vdd during the write state and 0 or an intermediate value during the read and hold states [9]. One of the problems with this approach, as implied from Table 2, is that same back-gate voltage bias is used for both BP0 and BP1 in read and hold states. Assuming NI can be 0, the desired back-gate voltages are Vdd for BP0 and 0 for BP1. Therefore, to have one fixed value for both pull-up transistors in both the operation modes, we should choose a compromising value. In Ref. [9], the authors suggested 0.48 V for a technology of 22 nm gate length when the supply voltage varied from 0.4 V to 1.2 V. Moreover, the approach in Ref. [9] sets the back-gate bias of both pull-up transistors to Vdd during the write mode irrespective of the data being written to the cell, whereas based on the results presented in Table 2, it is most optimal for write margin enhancement to set the back-gate of the pull-up on the node storing logic ‘‘0’’ (BP0) at zero bias and that of the pull-up on the node storing logic ‘‘1’’ (BP1) at Vdd. Additionally, the implementation of this approach requires some circuitry (which has some overhead) for the generation and distribution of the fixed voltage along with setting the WWL to Vdd during the write and 0.48 V during the read and hold states.
5. Proposed dynamic back-gate voltage technique In this work, we suggest a technique in which the back-gate voltages of the pull-up transistors are dynamically adjusted. The values of the voltages are set based on the desired values of each state. Table 2 suggests that, in the hold state, the back-gate voltage of the pull-up transistor whose drain stores logic ‘‘0’’ should be Vdd and the back-gate voltage of the other pull-up transistor is not important. Hence, in our design the back-gates are precharged to Vdd (as is done for the bitlines) to have the highest threshold
voltage for the pull-up transistors. In the write state, the pull-up transistor whose drain stores logic ‘‘1’’, should be weak, and hence, its back-gate voltage should be set to Vdd. In this case, the other pull-up transistor should be strong to have a high Vtrip, and hence, its back-gate voltage should be set to 0. The bias, however, turns on the OFF state pull-up with the back-gate during the write operation increasing the power consumption. First, note that, the use of the midgap work function metals for the gates yields high threshold voltage transistors with rather small ON current (high resistance). Second, turning on the pull-up helps the write operation reducing its required operation time. Thus, the time that we are required to apply this bias is reduced. Table 2 also suggests in the read state, the pull-up transistor whose drain stores logic ‘‘1’’ should have the back-gate voltage of 0. The back-gate voltage of the other pull-up transistor should be Vdd. These values are complement of the desired values for the write operation. Hence, we cannot fix the connection of the back-gates of the pull-up transistors to the corresponding storage nodes to avoid detrimental degradation of the write stability. Since the stored value is not known a priori, we need to choose a fixed value for the back-gate voltages of the pull-up transistors regardless of the stored value. In this work, we propose to set the value based on maximizing the read SNM. We also leave pull-down transistors in the tied-gate mode, because it is the favorable mode from read stability and static power perspective as shown in Table 2. Also, write margin sensitivity to pull-down threshold voltage is much smaller compared to those of access and pull-up transistors [19]. The back-gates of the access transistors are also connected to the adjacent storage nodes (similar to the other ABG structures). This is the favorable case from read stability and static power perspectives as shown in Table 2. To set the desired back-gate voltages of the pull-up transistors based on the operation state of the SRAM cell, we propose the circuit diagram for the SRAM array which is shown in Fig. 5. In the proposed scheme, the pull-up back-gate biases are data dependent and set based on the input data to be written to the cell using an added write driver circuitry as shown in Fig. 5. In this case, proper values of the bitlines and pull-up back-gate voltages should be set
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Fig. 6. Nominal write margin (CWLM) versus Vdd for different SRAM structures.
It should be noted that SRAM stability and performance could also be improved using other means such as 6T SRAM cells with two-fin pull-down or 8T cell structures. Our design, however, would outperform these structures. In the case of the former cell, using sizing to improve the read stability worsens the write stability and vice versa (see e.g., [9]). For example, the two-fin pull-down approach increasing the area by 16.6% [9] improves the read stability while deteriorates the write stability by about the same amount (see Fig. 6 in Ref. [9]), and hence, may not be a good choice for improving both of the read and write stabilities especially at lower supply voltages where the write stability is degraded more. In addition, it increases the power. On the other hand, increasing the number of transistors, as is the case for the latter cell structure, increases the area considerably. For example, the 8T SRAM cell has 30% more area compared to the former structure [28]. The area penalty of our design is about one third of that of the 8T SRAM cell. Fig. 5. The proposed array design for dynamically biasing the back-gate of pull-up transistors.
before the wordline is activated, while in the case of the conventional SRAM cell, the setting of the voltages are performed only for the bitlines. Since the interconnect used for the back-gate voltage has the same length (interconnect dominant capacitance [22]) as that of the bitline, the setting of the voltages should be performed at about the same time. Sharing the added circuitry among the cells of each column makes its area and power overhead negligible. The extra write driver typically induces a very small area penalty [23] (about 0.5% for an array of 128 cells per column [24]). The hold state biasing of the back-gates, which lowers the standby power as well, is performed by an extra precharge circuit, as shown in Fig. 5. As a rule of thumb, the area overhead of the extra precharge circuit should be much less than that of the write driver circuit [25]. An optimum pre-generated back-gate voltage bias (Vopt) for the read state is applied to the back-gate lines via a pair of nMOS switches (Fig. 5). These nMOS sizes are determined to achieve the required voltage swing on the back-gate lines from the precharged value of Vdd set during the hold state (initial state) to the optimum value (Vopt) required for the read operation, within the read cycle. Therefore, these nMOS switches are expected to occupy less area than that of the extra write driver due to the lower voltage swing required on the back-gate lines and the longer time available for this voltage swing to be completed. The optimum back-gate voltage bias (Vopt) can also be generated by a low Vdd voltage reference (e.g., [26,27]). As the voltage reference is shared for the whole chip, its area and power penalty is negligible [26,27]. It should be noted that the layout of the proposed SRAM cell remains similar to Fig. 4c. The difference is that the pull-up backgate lines are assumed to route vertically (on contrary to horizontally in the approach of [9]) in a different metal layer than that of the bitlines to eliminate the cross talk noise to the parallel bitlines.
6. Results and discussion In this part, we study the efficacy of the proposed scheme by comparing its performance with those of the DG structure, the ABG structure proposed in Ref. [8] where the independent-gate mode is used only for the access transistors, the ABG structure with back-gate voltage of 0 and Vdd for the pull-up transistors during the read/hold and write states, respectively [9], and the ABG structure with back-gate voltage of 0.48 V and Vdd for the pull-up transistors during the read/hold and write states, respectively [9]. In the case of the DG structure, to increase the read stability, we increase the gate work function to 4.75 eV. By increasing the gate work function further, the read stability decreases instead of increasing due to the severe subthreshold leakage current increase of the pMOS pull-up as discussed in Section 3. Next, we present the static characteristics of one SRAM cell in each structure with the corresponding backgate bias conditions. 6.1. Nominal study First, we consider the write stability metric (write margin) for which different definitions have been suggested in the literature [19]. In this work, we use the difference between Vdd and the minimum wordline voltage, namely, combined wordline margin (CWLM), that can cause a successful write operation as a metric [19]. It has been shown that this metric has a Gaussian distribution in the presence of process variations [19,29]. The write margin of different structures versus the supply voltage is depicted in Fig. 6. The results reveal that our proposed structure has the highest write margin among different structures even more than the ABG structure, in which the back-gate of the pull-up transistors are connected to Vdd. It should be noticed out the proposed structure has an acceptable write margin even for Vdd’s as low as 0.5 V
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while the area is compact due to using FinFETs with one fin. Additionally, to avoid the half-selected issue for the cells in the selected row, it has been suggested that the whole row is simultaneously written [30]. Using this approach, in this work, we assume 8 cells (one byte) in each row for each SRAM sub-block [31]. On the other hand, the half-selected cells in the same column as that of the cell being written have their wordlines deactivated. Hence, during the short time of the write operation, the storage node voltages of the half-selected cells do not change considerably yielding high halfselected cell stability. As discussed in Section 3.3, the static power is the most important metric in the hold state. In Fig. 7, we compare the static powers of the structures. The results demonstrate that the DG structure has about one order of magnitude higher static power than that of the ABG structure with tied-gate mode pull-up. This may be justified by noting that, due to the higher gate work function in the DG structure, the pull-up transistor has higher subthreshold leakage current. In the case of the independent-gate mode pull-up, if the back-gate voltages of the pull-up transistors are set to 0, the subthreshold leakage current will become unacceptably high. On the other hand, if the compromising value which considers the read stability and static power is used for the back-gates of the pullup transistors, the subthreshold leakage will increase considerably at high supply voltages. The results indicate that our proposed structure and ABG structure with tied-gate pull-up transistors have the least static power. The reason for the lower static power for these structures is that the back-gate voltage of the OFF state pull-up transistor is Vdd resulting in a higher absolute value for the threshold voltage. In Fig. 8, we have plotted the nominal (without considering process variation impacts) read SNM versus the supply voltage for all the structures. As evident from the figure, for the supply voltages larger than 0.6 V, the ABG structure [8] has a higher read SNM than that of the DG structure in spite of increasing the gate work function for the DG structure. Using the independent-gate mode operation for the pull-up transistors decreases the read SNM. This may be attributed to the smaller transconductance of independent-gate FinFET compared to that of the tied-gate one [4]. The smaller transconductance leads to a smaller gain for the inverter determining the transfer characteristic and consequently the read SNM becomes smaller [18]. If the back-gate of the pull-up transistors is connected to the ground, the read SNM decreases due to the increase in the subthreshold leakage current of the pull-up transistors, especially at higher supply voltages. The back-gate of the pullup transistors may be connected to an intermediate fixed voltage. As an example, this value was set to 0.48 V in Ref. [9]. In this case, however, the read SNM decreases due to the smaller transconductance of the independent-gate pull-up transistors and also decrease in the value of Vtrip owing to weak pull-up at lower supply voltages. In the case of our proposed design, the back-gate voltages for the read and hold states can be different. Using the proposed
circuit shown in Fig. 5, we can choose an optimum back-gate voltage based on the supply voltage for the read state. We used simulations to find the optimum values for the maximum read SNM by sweeping the back-gate voltage between 0 and Vdd for each supply voltage. The optimum values considering the read stability are listed in the inset of Fig. 8. Due to the process variations, the optimum value for a given Vdd may vary. To study the sensitivity of the read SNM to the optimum value, we changed the optimum values for all the supply voltages studied in this work by 20% and measured the read SNM. The results showed at most 2.5% change in the value of the SNM. Hence, the preciseness of the voltage generator is not of a critical concern. The results indicate that the read stability of our design is higher than those of the ABG structures with fixed pull-up back-gate voltages of 0 and 0.48 V for the supply voltages between 0.4 V and 0.9 V while lower than those of the DG and ABG structures for the supply voltages between 0.7 V and 0.9 V. The lower read stability may be attributed to the less transconductance of the independent-gate pull-up transistor with respect to the tied-gate one which causes better stability for the DG and ABG structures at high supply voltages. In addition, the read SNM of the proposed technique, similar to that of the ABG [8], is the highest for the supply voltages from 0.4 V to 0.6 V. The read currents for different structures are compared in Fig. 9. As is evident from the figure, the read currents of the ABG structures (including our proposed structure) are more than that of DG structure for lower Vdd’s. This may be attributed to the fact that the lower gate work function effect (lower threshold voltage) dominates the zero back-gate bias of the access transistor (higher threshold voltage) in the case of the ABG structures. At higher supply voltages, the read current of the ABG structure, in which the back-gates of the pull-up transistors are connected to ground, decreases because the subthreshold leakage of the OFF state pullup transistor increases. This raises the value of Vread (the source voltage of the access transistor) leading to a lower overdrive voltage for the (discharging) access transistor, and hence, a smaller read current. At the highest supply voltage (Vdd = 0.9 V), the read
Fig. 7. Nominal static power versus Vdd for different SRAM structures.
Fig. 9. Nominal read current versus Vdd for different SRAM structures.
Fig. 8. Nominal read SNM versus Vdd for different SRAM structures.
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currents of the ABG structures are lower than that of the DG structure because the zero back-gate bias dominates the lower gate work function. This implies that the use of the independent-gate structure only slightly lowers the read speed for the highest Vdd. It should be noted that the midgap work function values used in this work are more appropriate for low power applications. For example, the read current values are very close to those of a SRAM array fabricated using a 28 nm low power SOC process [32]. 6.2. Study of process variation effect Now, we study the impact of the process variation on the SRAM cell structures discussed in this work. In addition to channel length and silicon thickness variations due to the line-edge roughness, there are other sources of variations including random dopant fluctuations as well as work function, fin height, and oxide thickness variations. As the experimental results presented in e.g., [33,34] show, the random dopant fluctuation can be ignored due to the fact that the body is lightly doped. Also, the work function variation can be suppressed by using gate-last process where amorphous metal gate are deposited after the high-temperature annealing and activation process steps [35]. On the other hand, since the real values of fin height and oxide thickness are not determined by the lithography resolution, their variations should not be critical (please see e.g., [33]). The actual values of the channel length and silicon thickness are dictated by the lithography resolution and hence their variations are of key concern (see e.g., [9,10,33]). It should be mentioned that including other variation sources may be readily performed by extending the analysis given below. For this study, we assume that the channel length and silicon thickness have the variations such that the standard variations, namely, rtsi and rLg, respectively, are 7% Lg [9]. The variation of read SNM and CWLM may be very well modeled by a normal distribution [19,29]. Therefore, we assume that these metrics have Gaussian distributions which are functions of twelve random variables. Denoting the metric by y, we may write
y ¼ f ðx1 ; . . . ; x12 Þ;
ð1Þ
where x1,. . ., x12 are the Gaussian random variables with the averages of g1, . . ., g12 and standard deviations of r1,. . ., r12. These twelve random variables are channel lengths and silicon thicknesses of six transistors of the SRAM cell. Hence, we can use the following expression to find their statistical characteristics using bivarient Taylor Series as [36]:
ly ¼ f ðg1 ; . . . ; g12 Þ
ð2Þ
!2 12 X @f ¼ r2i @xi gi i¼1
ð3Þ
r
2 y
Here, we used the cell sigma, the yield figure of merit of the SRAM, which is defined as the minimum amount of variation needed to cause a read or write failure. The cell sigma is given by the mean (l) divided by the standard deviation (r) [9]. Nowadays, six-sigma (6r) yield or larger is required for large SRAM arrays [9]. In Fig. 10, we have plotted the read SNM and CWLM cell sigma yields versus the supply voltage obtained from simulations and using Eqs. (2) and (3). It should be noted that ly’s in Eq. (2) were approximated by their nominal values which were presented in Figs. 6 and 8. Also, since the variations of the read SNM and CWLM were linearly proportional to the variations of the random variables (xi) [19,29], the derivatives in (3), of/oxi, were easily found by using the metric values through the simulations at some values of xi near the nominal values (gi). As is evident from the figure, our proposed structure and the ABG structure with pull-up back-gate voltages equal to 0 have over six-sigma read yield for supply
Fig. 10. (a) Read SNM and (b) CWLM cell sigma yield versus the supply voltage for different SRAM cell structures.
voltages as low as 0.5 V. This is due to the high nominal read SNM and less sensitivity to device parameters especially at low supply voltages. As expected the write yield degrades considerably for low supply voltages. Among these structures, only our proposed structure has over six-sigma write yield down to Vdd equal to 0.55 V (0.15 V below the minimum of the other structures). For our structure, at Vdd = 0.5 V, the write margin cell sigma is slightly lower than six. To have six-sigma write yield, one may lower gate work function of the transistors to 4.57 eV to increase the writability. This work function tuning makes the access (as well as pull-down) nMOS stronger while making the pull-up pMOS weaker. These strength changes improves the write yield such that both the read and write cell sigma yields become above six. In this case, the read current increases by 56% while the static power also increases by 47% compared to the case of no work function tuning. The static power is still 23% lower than that of the structure (without work function tuning) when the supply voltage of 0.6 V is used. Therefore, if a proper work function tuning can be performed, one may use Vdd = 0.5 V to lower the static power (as well as the dynamic power due to a lower supply voltage). With similar work function tuning, we used the gate work function of 4.61 eV, 4.54 eV, 4.49 eV, and 4.61 eV for the DG, ABG, ABG with pull-up back-gate voltage of 0 during the read/hold states, and ABG with pull-up back-gate voltage of 0.48 V during the read/hold states, respectively. This resulted in the minimum operating voltage of 0.65, 0.65, 0.6, and 0.7 V, respectively. These numbers suggest that the proposed structure still could operate with the supply voltage which is 0.1 V lower than that of the other structures. Next, we consider the SNM cell sigma yield for the half-selected cells in the same column of the selected cell shown in Fig. 11. For the read operation (Fig. 11b), the yields for all the structures are very high. In the case of the write operation, while the half-selected disturb is the worst for our proposed structure, it is still higher than six. It should be noted that as the wordlines of half-selected cells are inactive, the storage node voltages of the half-selected cells do not have enough time for changing their values for threatening
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the supply voltage are plotted in Fig. 12. As is observed from the results the proposed structure consumes more dynamic energy compared to those of the other structures. This is due to the more voltage switchings of the lines connected to the back-gates of the pull-up transistors. Since the main contributor to the total power of SRAM is the static power [20,33], the larger dynamic energy for the proposed structure may not be considered as major shortcoming. It should be noticed that since our structure could operate at lower minimum supply voltages, the dynamic power may be lowered by lowering the supply voltage wherever the corresponding speed reduction can be tolerated. The supply voltage reduction also lowers the static power. 7. Conclusions
Fig. 11. Half-selected SNM cell sigma during (a) write and (b) read versus the supply voltage for different SRAM cell structures.
the reliability (SNM, which is a static parameter, is a pessimistic metric) (see e.g., [37]). 6.3. Dynamic energy consumption In this part, we study the energy consumptions of the structures per read and write operations. In the structures considered in this work, the main sources of the dynamic power consumption are the voltage changes of the long wordline, bitlines, and pull-up backgate lines. The increased static currents of the cells during the read and write operations (including those induced due to the application of the back-gate biases) can be neglected as the cells are in the hold state most of the time while the read and write times are very short. To perform this study, we assumed a SRAM block with 8 cells in each row [31] and 128 cells in each column [24] and the line capacitance was taken as 0.25 fF/lm to account for the dominant interconnect capacitance as well as the drain/gate contact capacitance [22]. Hence, we included the additional parasitic capacitances for the pull-up back-gate lines as well as the bitlines. The results for the energy consumptions of all the structures versus
We proposed a dynamic back-gate design for the pull-up transistors of SRAM cells to increase the cell stability during the read and write states while decreasing the static power during hold state. The optimization was performed by dynamically adjusting the voltages of the back-gates of the pull-up transistors in the cell. The voltages were determined in order to have maximum stability during the read and write states and minimum static power during the hold state. During the write operation, we used an extra write driver which sets the desired back-gate voltage of pull-up transistors to considerably increase the write margin. During the hold state, to decrease the static power, the back-gates were precharged to the supply voltage using an extra precharge circuit. The read stability degradation was prevented using proper back-gate voltages generated using nMOS switches. To reduce the area and power overheads, the added circuitry was shared for each column. Also, the proposed structure had the highest write margin among the structures considered in this work. The half-selected issue for the cells in the selected row has been avoided by writing the whole row simultaneously. The half-selected cells in the same column of the selected cell had high stability during read and write operations. Therefore, the proposed cell may be used for the applications where writing the whole row simultaneously is possible. For the cell with single fin FinFETs, the minimum operating voltage for six-sigma yield obtained to be about 0.55 V which was 0.15 V lower than that of a recently proposed structure. In addition, our structure had much less static power. The minimum operating voltage of the proposed structure could be lowered to 0.5 V by some work function tuning while the minimum operating voltage for all other structure was 0.6 V or higher using similar work function tunings. Acknowledgement The first two authors acknowledge the financial support by the Iranian National Science Foundation (INSF). References
Fig. 12. (a) Write energy for one byte (solid lines) and read energy (dotted lines) versus Vdd for different SRAM structures.
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