Integrated VLSI Potentiostat For Cyclic Voltammetry In ... - CiteSeerX
To appear in IEEE ISVLSI 2004, Page 1 of 3
Integrated VLSI Potentiostat For Cyclic Voltammetry In Electrolytic Reactions Harpreet S. Narula and John G. Harris Computational Neuro-Engineering Lab University of Florida, Gainesville, FL, USA harpreet, [email protected]
Abstract This paper describes a CMOS integrated potentiostatic control circuit. The design maintains a constant bias potential between the reference and working electrodes for an amperometric chemical sensor. A technique of converting input currents into time for amperometric measurements is proposed. Redox currents ranging from 1pA to 200nA can be measured with a maximum non-linearity of ±0.1% over this range. The design can be used to generate a cyclic voltammogram for an electrochemical reaction by sweeping the voltages across the range specified by the user. Analog inputs are processed and digital outputs are generated without requiring a power-hungry A/D converter. A prototype chip has been fabricated in the 0.5µm AMI CMOS process. Experimental results are reported showing the performance of the circuit as a chemical sensor.
1. Introduction With the recent advances in the development of micro arrays that can transmit very low signals [5], there is a growing need for precise chemical sensors that can accurately measure the chemical activity while maintaining a fixed potential between electrodes of the chemical reaction. This mandates the need for precise measurement of electrochemical activity caused by certain reactions at the electrodes of an electrochemical cell. Previously, some designs have been proposed for VLSI potentiostats [1, 2, 3, 4]. Each of these designs amplifies smaller currents to the µA range and then measures the input current by calibrating their design at higher current range. By converting input current directly into time we eliminate amplifying circuitry, avoid matching problems and save on area and power consumption. We have designed a potentiostat circuit that accepts an electrical signal, proportional to current flowing through the electrolyte and measure the time it takes to charge or discharge a capacitor. On-chip generation of triangular waveforms for cyclic voltammetry provides accurate measure-
ments for electrolytic reactions. Two circuits have been designed for positive and negative flow of current that charge or discharge the capacitor at a speed proportional to the current flowing through the electrolyte and is given by ∆t =
C∆V Ipot
(1)
where ∆V is the change in voltage across capacitor C, with input current Ipot from the working electrode of the electrochemical cell. Finally we integrated the two circuits so that a single design can be used for both positive and negative flow of currents.
2 Potentiostat Circuit We used a class-II current conveyor to convey input current at a low-impedance terminal (X) to a high-impedance output terminal (Z) while maintaining a constant voltage at the second input terminal (Y). The block diagram of the potentiostat circuit is shown in figure 1. The capacitor (Cd ) is first precharged to VDD through transistor P1 (PMOS) controlled by signal RESET, and then discharged through transistor N1 (NMOS) with the input current flowing through the working electrode of the potentiostat. The comparator reference voltage (Vref ) clamps the voltage drop across the capacitor. As soon as the voltage of the capacitor reaches Vref , a pulse is generated at the output of the comparator and the capacitor is again RESET to voltage VDD through PMOS transistor P1. The time taken for the comparator output to change levels, gives the time equivalent of the current input at the working electrode. This leaves no room for quantization error and requires just one comparator as opposed to a whole A/D converter on a chip. The simulation results showing capacitor voltage (Cd ) vs. time taken by the input current to discharge the capacitor is shown in figure 1. Further, the dual of this design technique was designed using a PMOS transistor at the input for negative currents at the input and finally both the designs were integrated together for bi-directional sensing of current. If we vary ∆V dynamically as shown the ca-
To appear in IEEE ISVLSI 2004, Page 2 of 3
VDD
VDD
P1
Vhi
VDD
Y
Z
Cd
+
Vpot
N1 GND
OTA
+ Comparator -
Vref
+ Comp -
PCH S
GND
vcap Pulse Output
Vlo
SET
Q
vcap
Latch
VDD
R
CLR
C_tri
Q
NDS
+
GND
5
1pA
I Working Electrode
Capacitor Voltage (Volts)
GND
Ib
Comp -
X -
Reference Electrode
Ib
VDD
RESET
4.5
Varying Reference Voltage 4
5pA 3.5
25pA
Figure 2. Block diagram of triangular wave generator. Vhi and Vlo set the maximum and minimum value of the waveform generated
10pA
50pA 100pA
3
bias
500pA Reference Voltage
2.5 0
0.1
0.2
0.3
Time (s)
0.4
0.5 19.95/ 15 19.95/ 15
Figure 1. VLSI Potentiostat Block Diagram with the capacitor voltage plot for different input current levels
19.95/ 15 19.95/ 15
M5
VSS
10.05/ 1.95
VSS
10.05/ 1.95
45/ 1.95 18.15/ 15
5.85/ 1.95
45/ 1.95 M1
In_neg
VDD
Vcasc1
M6
10.05/ 30 VDD
M7
10.05/ 30 VSS
M8
19.95/ 15
M2 In_pos Vcasc2
pacitor voltage plot in figure 1, we can limit the time taken for discharging (charging for the PMOS design) capacitor voltages. We achieve significant improvement in the dynamic range of the signals within a fixed time range. In order to generate cyclic voltammogram for an electrolytic reaction, we have integrated a digital circuit shown in figure 2, to generate triangular waveform on chip. The triangle wave is generated by linearly charging and discharging a capacitor between two reference voltage levels provided as the inputs for generation of triangular waveform. The bias current (Ib ) is generated using a single source and mirrored using modified Wilson current mirrors. Frequency of triangular waveform can be changed by varying Ib .
19.95/ 15
19.95/ 15
19.95/ 15
M3 M4
Figure 3. OTA Schematic
3 Operating Analysis and Design Optimization
low noise at low current levels. The bias current is set to 5µA and transistors may operate in either the weak or strong inversion region depending on their W/L ratios. Analysis of this circuit reveals the input referred thermal noise power to be · ¸ 8ktγ 2gm3 gm7 2 vni,thermal = 1+ + (2) gm1 gm1 gm1
Two important problems related to the design of the time-based converter are input noise and the propagation delay of the comparator. The circuit has been designed to optimize these problems areas. An operation transconductance amplifier (OTA) used for our design is shown in figure 3. Although the circuit topology is a standard design suitable for driving capacitive loads, the sizing of the transistors is critical for achieving
We have sized our devices such that gm3 , gm7
Integrated VLSI Potentiostat For Cyclic Voltammetry In Electrolytic Reactions Harpreet S. Narula and John G. Harris Computational Neuro-Engineering Lab University of Florida, Gainesville, FL, USA harpreet, [email protected]
Abstract This paper describes a CMOS integrated potentiostatic control circuit. The design maintains a constant bias potential between the reference and working electrodes for an amperometric chemical sensor. A technique of converting input currents into time for amperometric measurements is proposed. Redox currents ranging from 1pA to 200nA can be measured with a maximum non-linearity of ±0.1% over this range. The design can be used to generate a cyclic voltammogram for an electrochemical reaction by sweeping the voltages across the range specified by the user. Analog inputs are processed and digital outputs are generated without requiring a power-hungry A/D converter. A prototype chip has been fabricated in the 0.5µm AMI CMOS process. Experimental results are reported showing the performance of the circuit as a chemical sensor.
1. Introduction With the recent advances in the development of micro arrays that can transmit very low signals [5], there is a growing need for precise chemical sensors that can accurately measure the chemical activity while maintaining a fixed potential between electrodes of the chemical reaction. This mandates the need for precise measurement of electrochemical activity caused by certain reactions at the electrodes of an electrochemical cell. Previously, some designs have been proposed for VLSI potentiostats [1, 2, 3, 4]. Each of these designs amplifies smaller currents to the µA range and then measures the input current by calibrating their design at higher current range. By converting input current directly into time we eliminate amplifying circuitry, avoid matching problems and save on area and power consumption. We have designed a potentiostat circuit that accepts an electrical signal, proportional to current flowing through the electrolyte and measure the time it takes to charge or discharge a capacitor. On-chip generation of triangular waveforms for cyclic voltammetry provides accurate measure-
ments for electrolytic reactions. Two circuits have been designed for positive and negative flow of current that charge or discharge the capacitor at a speed proportional to the current flowing through the electrolyte and is given by ∆t =
C∆V Ipot
(1)
where ∆V is the change in voltage across capacitor C, with input current Ipot from the working electrode of the electrochemical cell. Finally we integrated the two circuits so that a single design can be used for both positive and negative flow of currents.
2 Potentiostat Circuit We used a class-II current conveyor to convey input current at a low-impedance terminal (X) to a high-impedance output terminal (Z) while maintaining a constant voltage at the second input terminal (Y). The block diagram of the potentiostat circuit is shown in figure 1. The capacitor (Cd ) is first precharged to VDD through transistor P1 (PMOS) controlled by signal RESET, and then discharged through transistor N1 (NMOS) with the input current flowing through the working electrode of the potentiostat. The comparator reference voltage (Vref ) clamps the voltage drop across the capacitor. As soon as the voltage of the capacitor reaches Vref , a pulse is generated at the output of the comparator and the capacitor is again RESET to voltage VDD through PMOS transistor P1. The time taken for the comparator output to change levels, gives the time equivalent of the current input at the working electrode. This leaves no room for quantization error and requires just one comparator as opposed to a whole A/D converter on a chip. The simulation results showing capacitor voltage (Cd ) vs. time taken by the input current to discharge the capacitor is shown in figure 1. Further, the dual of this design technique was designed using a PMOS transistor at the input for negative currents at the input and finally both the designs were integrated together for bi-directional sensing of current. If we vary ∆V dynamically as shown the ca-
To appear in IEEE ISVLSI 2004, Page 2 of 3
VDD
VDD
P1
Vhi
VDD
Y
Z
Cd
+
Vpot
N1 GND
OTA
+ Comparator -
Vref
+ Comp -
PCH S
GND
vcap Pulse Output
Vlo
SET
Q
vcap
Latch
VDD
R
CLR
C_tri
Q
NDS
+
GND
5
1pA
I Working Electrode
Capacitor Voltage (Volts)
GND
Ib
Comp -
X -
Reference Electrode
Ib
VDD
RESET
4.5
Varying Reference Voltage 4
5pA 3.5
25pA
Figure 2. Block diagram of triangular wave generator. Vhi and Vlo set the maximum and minimum value of the waveform generated
10pA
50pA 100pA
3
bias
500pA Reference Voltage
2.5 0
0.1
0.2
0.3
Time (s)
0.4
0.5 19.95/ 15 19.95/ 15
Figure 1. VLSI Potentiostat Block Diagram with the capacitor voltage plot for different input current levels
19.95/ 15 19.95/ 15
M5
VSS
10.05/ 1.95
VSS
10.05/ 1.95
45/ 1.95 18.15/ 15
5.85/ 1.95
45/ 1.95 M1
In_neg
VDD
Vcasc1
M6
10.05/ 30 VDD
M7
10.05/ 30 VSS
M8
19.95/ 15
M2 In_pos Vcasc2
pacitor voltage plot in figure 1, we can limit the time taken for discharging (charging for the PMOS design) capacitor voltages. We achieve significant improvement in the dynamic range of the signals within a fixed time range. In order to generate cyclic voltammogram for an electrolytic reaction, we have integrated a digital circuit shown in figure 2, to generate triangular waveform on chip. The triangle wave is generated by linearly charging and discharging a capacitor between two reference voltage levels provided as the inputs for generation of triangular waveform. The bias current (Ib ) is generated using a single source and mirrored using modified Wilson current mirrors. Frequency of triangular waveform can be changed by varying Ib .
19.95/ 15
19.95/ 15
19.95/ 15
M3 M4
Figure 3. OTA Schematic
3 Operating Analysis and Design Optimization
low noise at low current levels. The bias current is set to 5µA and transistors may operate in either the weak or strong inversion region depending on their W/L ratios. Analysis of this circuit reveals the input referred thermal noise power to be · ¸ 8ktγ 2gm3 gm7 2 vni,thermal = 1+ + (2) gm1 gm1 gm1
Two important problems related to the design of the time-based converter are input noise and the propagation delay of the comparator. The circuit has been designed to optimize these problems areas. An operation transconductance amplifier (OTA) used for our design is shown in figure 3. Although the circuit topology is a standard design suitable for driving capacitive loads, the sizing of the transistors is critical for achieving
We have sized our devices such that gm3 , gm7
