VLSI potentiostat for amperometric ... - University of Florida
VLSI POTENTIOSTAT FOR AMPEROMETRIC MEASUREMENTS FOR ELECTROLYTIC REACTIONS Harpreet S. Narula and John G. Harris Computational Neuro-Engineering Lab University of Florida, Gainesville, FL, USA harpreet,[email protected]fl.edu 1. ABSTRACT This paper describes a CMOS integrated potentiostatic control circuit. The design maintains a constant bias potential between the reference and working electrodes for an amperometric chemical sensor. A technique of converting input currents into time for amperometric measurements is proposed. Redox currents ranging from 1pA to 200nA can be measured with a maximum non-linearity of ±0.1% over this range. Analog inputs are processed and digital outputs are generated without requiring a power-hungry A/D converter. A prototype chip has been fabricated in the 0.5µm AMI CMOS process. Experimental results are reported showing the performance of the circuit as a chemical sensor. 2. INTRODUCTION With the recent advances in the development of micro arrays that can transmit very low signals [1]-[2], there is a growing need for precise chemical sensors that can accurately measure the chemical activity and maintain fixed potential between electrodes of the chemical reaction. Threats of chemical and biological terror have made it even more important to design portable sensors, many of which can be integrated onto a single IC. This mandates the need for precise measurement of electrochemical activity caused by certain reactions at the electrodes of an electrochemical cell. Previously, some designs have been proposed for VLSI potentiostats [3, 4, 5, 6, 7]. Each of these designs amplifies smaller currents to the µA range and then measures the input current by calibrating their design at higher current range. By converting input current directly into time we eliminate amplifying circuitry, avoid matching problems and save on area and power consumption. We have designed a potentiostat circuit that accepts an electrical signal, proportional to current flowing through the electrolyte (in the electrochemical cell) and measure the time it takes to charge or discharge a capacitor. We eliminate sources Authors thank NSF for funding this project. Funds were provided by NSF award # 0087676.
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of noise and mismatch by directly converting input current into time and then performing time-based computation. A similar approach is discussed using a dual-slope converter [8], but the design suffers from errors due to charge injection and requires complex calibration. Instead our design technique provides better results and we are able to measure current as low as 1pA. The proposed design is more sensitive, portable, inexpensive and consumes lower power than earlier designs. In an electrochemical cell, any change in the potential of the cathodic electrode, results in a flow of current in the electrolyte so the potential of the electrode is maintained. The current will be conveyed using novel nanowires developed in the Martin lab [2] at the University of Florida to the electrodes of our potentiostat circuit. Two designs have been made for positive and negative flow of current that charge or discharge the capacitor at a speed proportional to the current flowing through the electrolyte and is given by ∆t =
C∆V Ipot
(1)
where ∆V is the change in voltage across capacitor C, with input current Ipot from the working electrode of the electrochemical cell. We achieve high resolution by converting the input current into time taken to charge or discharge a capacitor. We further connect the capacitor to a highresolution, low offset comparator [9] to convert the capacitor voltage into digital pulses which can be counted using a digital counter calibrated to precisely measure the input current. Noise is critical in an application with such small currents, therefore the CMOS design has been made to work near the weak inversion region minimizing the noise, using feedback and simplifying the circuit at the input. 3. POTENTIOSTAT DESIGN We used a class-II current conveyor to convey input current at a low-impedance terminal (X) to a high-impedance output terminal (Z) while maintaining a constant voltage at the second input terminal (Y).
,
,6&$6
VDD
tion results showing capacitor voltage (Cd ) vs. time taken by the input current to discharge the capacitor is shown in figure 2.
P1
RESET VDD
Y
Z
Vpot
N1 GND
OTA
+ Comparator -
Cd
+
Vref
VDD Pulse Output
X -
GND
VDD I
X Working Electrode
-
P2 VDD
Y+ Z
Reference Electrode
Vpot
Cc GND
Figure 1: VLSI Potentiostat Block Diagram
RESET
5
N2
+ Comparator -
Pulse Output
Vref
Figure 3: VLSI Potentiostat using PMOS transistor at input, used to charge capacitor to convert input current into time.
1pA
Capacitor Voltage (Volts)
4.5
4
5pA
3.5 25pA
10pA
50pA
3
100pA 500pA Reference Voltage
2.5 0
0.1
0.2
0.3
0.4
0.5
Time (s)
Figure 2: Capacitor Voltage vs. Time: Discharge Time depends on input current
The block diagram of the potentiostat design is shown in figure 1. The capacitor (Cd ) is first precharged to VDD through transistor P1 (PMOS) controlled by signal RESET, and then discharged through transistor N1 (NMOS) with the input current flowing through the working electrode of the potentiostat. The comparator reference voltage (Vref ) clamps the voltage drop across the capacitor. As soon as the voltage of the capacitor reaches Vref , a pulse is generated at the output of the comparator and the capacitor is again RESET to voltage VDD through PMOS transistor P1. The time taken for the comparator output to change levels, gives the time equivalent of the current input at the working electrode. The insignificant quantization noise is this case can be ignored and this design requires just one comparator as opposed to a whole A/D converter on a chip. The simula-
Further, the same design technique was explored using a PMOS transistor for negative input currents as shown in figure 3. In this design, capacitor (Cc ) is charged by the input current through transistor P2. As the voltage across the capacitor reaches Vref , a pulse is generated at the output of the comparator. Capacitor (Cc ) is then reset to 0V by discharging through NMOS transistor N2 in figure 3. We calculate the input current by counting the number of pulses generated using a micro-controller. We achieved better results using this design since input PMOS transistors show lower thermal noise due to the lower mobility coefficient of current carrier holes in PMOS transistors. When the signal is small, discharging the capacitor to Vref = 2.5V takes a very long time (2.5sec for 1pA input current) as compared to the time taken when large current passes through the circuit (2.5msec for 1nA input current). Varying the capacitance (C) or ∆V with change in Ipot in equation 1 helps to work more conveniently over the wide dynamic range. Changing capacitance would not increase the dynamic range and may also require more area on the chip for higher current inputs. Instead if we vary ∆V dynamically as shown in figure 4, we can reduce the time taken for charging (discharging for the design shown in figure 1) capacitor voltages generated by the design shown in figure 3. Using this technique we can limit the maximum response time of the circuit. As shown in in figure 4, limiting the response time to 0.5sec, ∆V = reference voltage = 0.95V for 2.5pA input current. We achieve significant improvement in the dynamic range of the signals within this time range.
,
bias
Capacitor Voltage(Volts)
2.5
25pA 100pA 1nA
19.95/ 15
5pA 19.95/ 15
2
19.95/ 15 19.95/ 15
2.5pA
M5
VSS
10.05/ 1.95
VSS
10.05/ 1.95
45/ 1.95 18.15/ 15
1.5
5.85/ 1.95
45/ 1.95 M1
In_neg
VDD
Vcasc1
M6
10.05/ 30 VDD
M7
10.05/ 30 VSS
M8
19.95/ 15
M2 In_pos Vcasc2
19.95/ 15
1
19.95/ 15
19.95/ 15
M3 M4
Reference Voltage
0.5
0
0
0.5
1
Time(s)
Figure 5: Operational Transconductance Amplifier
Figure 4: Dynamically varying Reference Voltage (of comparator) to increase dynamic range 4. OPERATING ANALYSIS AND DESIGN OPTIMIZATION Two important problems related to the design of the time based converter are:
The propagation delay of the comparator is caused due to the input offset, sensitivity to differential signal, speed and input capacitance of comparator. The input offset voltage of the comparator results in the final capacitor voltage Vf inal , required to generate a proper pulse at the output of the comparator, to be little more (or less) than Vref . This difference in time is due to the comparator offset given by ±tof f = tf inal − tideal =
1. Input Noise
CVof f Iinp
(3)
2. Propagation Delay of Comparator The circuit has been designed to optimize these problems areas. An operation transconductance amplifier used for our design is shown in figure 5. Although the circuit topology is a standard design suitable for driving capacitive loads, the sizing of the transistors is critical for achieving low noise at low current levels. The bias current is set to 5µA and transistors may operate in either the weak or strong inversion region depending on their W/L ratios. Analysis of this circuit reveals the input referred thermal noise power to be 2gm3 8ktγ gm7 2 vni,thermal = 1+ (2) + gm1 gm1 gm1 We have sized our devices such that gm3 , gm7
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of noise and mismatch by directly converting input current into time and then performing time-based computation. A similar approach is discussed using a dual-slope converter [8], but the design suffers from errors due to charge injection and requires complex calibration. Instead our design technique provides better results and we are able to measure current as low as 1pA. The proposed design is more sensitive, portable, inexpensive and consumes lower power than earlier designs. In an electrochemical cell, any change in the potential of the cathodic electrode, results in a flow of current in the electrolyte so the potential of the electrode is maintained. The current will be conveyed using novel nanowires developed in the Martin lab [2] at the University of Florida to the electrodes of our potentiostat circuit. Two designs have been made for positive and negative flow of current that charge or discharge the capacitor at a speed proportional to the current flowing through the electrolyte and is given by ∆t =
C∆V Ipot
(1)
where ∆V is the change in voltage across capacitor C, with input current Ipot from the working electrode of the electrochemical cell. We achieve high resolution by converting the input current into time taken to charge or discharge a capacitor. We further connect the capacitor to a highresolution, low offset comparator [9] to convert the capacitor voltage into digital pulses which can be counted using a digital counter calibrated to precisely measure the input current. Noise is critical in an application with such small currents, therefore the CMOS design has been made to work near the weak inversion region minimizing the noise, using feedback and simplifying the circuit at the input. 3. POTENTIOSTAT DESIGN We used a class-II current conveyor to convey input current at a low-impedance terminal (X) to a high-impedance output terminal (Z) while maintaining a constant voltage at the second input terminal (Y).
,
,6&$6
VDD
tion results showing capacitor voltage (Cd ) vs. time taken by the input current to discharge the capacitor is shown in figure 2.
P1
RESET VDD
Y
Z
Vpot
N1 GND
OTA
+ Comparator -
Cd
+
Vref
VDD Pulse Output
X -
GND
VDD I
X Working Electrode
-
P2 VDD
Y+ Z
Reference Electrode
Vpot
Cc GND
Figure 1: VLSI Potentiostat Block Diagram
RESET
5
N2
+ Comparator -
Pulse Output
Vref
Figure 3: VLSI Potentiostat using PMOS transistor at input, used to charge capacitor to convert input current into time.
1pA
Capacitor Voltage (Volts)
4.5
4
5pA
3.5 25pA
10pA
50pA
3
100pA 500pA Reference Voltage
2.5 0
0.1
0.2
0.3
0.4
0.5
Time (s)
Figure 2: Capacitor Voltage vs. Time: Discharge Time depends on input current
The block diagram of the potentiostat design is shown in figure 1. The capacitor (Cd ) is first precharged to VDD through transistor P1 (PMOS) controlled by signal RESET, and then discharged through transistor N1 (NMOS) with the input current flowing through the working electrode of the potentiostat. The comparator reference voltage (Vref ) clamps the voltage drop across the capacitor. As soon as the voltage of the capacitor reaches Vref , a pulse is generated at the output of the comparator and the capacitor is again RESET to voltage VDD through PMOS transistor P1. The time taken for the comparator output to change levels, gives the time equivalent of the current input at the working electrode. The insignificant quantization noise is this case can be ignored and this design requires just one comparator as opposed to a whole A/D converter on a chip. The simula-
Further, the same design technique was explored using a PMOS transistor for negative input currents as shown in figure 3. In this design, capacitor (Cc ) is charged by the input current through transistor P2. As the voltage across the capacitor reaches Vref , a pulse is generated at the output of the comparator. Capacitor (Cc ) is then reset to 0V by discharging through NMOS transistor N2 in figure 3. We calculate the input current by counting the number of pulses generated using a micro-controller. We achieved better results using this design since input PMOS transistors show lower thermal noise due to the lower mobility coefficient of current carrier holes in PMOS transistors. When the signal is small, discharging the capacitor to Vref = 2.5V takes a very long time (2.5sec for 1pA input current) as compared to the time taken when large current passes through the circuit (2.5msec for 1nA input current). Varying the capacitance (C) or ∆V with change in Ipot in equation 1 helps to work more conveniently over the wide dynamic range. Changing capacitance would not increase the dynamic range and may also require more area on the chip for higher current inputs. Instead if we vary ∆V dynamically as shown in figure 4, we can reduce the time taken for charging (discharging for the design shown in figure 1) capacitor voltages generated by the design shown in figure 3. Using this technique we can limit the maximum response time of the circuit. As shown in in figure 4, limiting the response time to 0.5sec, ∆V = reference voltage = 0.95V for 2.5pA input current. We achieve significant improvement in the dynamic range of the signals within this time range.
,
bias
Capacitor Voltage(Volts)
2.5
25pA 100pA 1nA
19.95/ 15
5pA 19.95/ 15
2
19.95/ 15 19.95/ 15
2.5pA
M5
VSS
10.05/ 1.95
VSS
10.05/ 1.95
45/ 1.95 18.15/ 15
1.5
5.85/ 1.95
45/ 1.95 M1
In_neg
VDD
Vcasc1
M6
10.05/ 30 VDD
M7
10.05/ 30 VSS
M8
19.95/ 15
M2 In_pos Vcasc2
19.95/ 15
1
19.95/ 15
19.95/ 15
M3 M4
Reference Voltage
0.5
0
0
0.5
1
Time(s)
Figure 5: Operational Transconductance Amplifier
Figure 4: Dynamically varying Reference Voltage (of comparator) to increase dynamic range 4. OPERATING ANALYSIS AND DESIGN OPTIMIZATION Two important problems related to the design of the time based converter are:
The propagation delay of the comparator is caused due to the input offset, sensitivity to differential signal, speed and input capacitance of comparator. The input offset voltage of the comparator results in the final capacitor voltage Vf inal , required to generate a proper pulse at the output of the comparator, to be little more (or less) than Vref . This difference in time is due to the comparator offset given by ±tof f = tf inal − tideal =
1. Input Noise
CVof f Iinp
(3)
2. Propagation Delay of Comparator The circuit has been designed to optimize these problems areas. An operation transconductance amplifier used for our design is shown in figure 5. Although the circuit topology is a standard design suitable for driving capacitive loads, the sizing of the transistors is critical for achieving low noise at low current levels. The bias current is set to 5µA and transistors may operate in either the weak or strong inversion region depending on their W/L ratios. Analysis of this circuit reveals the input referred thermal noise power to be 2gm3 8ktγ gm7 2 vni,thermal = 1+ (2) + gm1 gm1 gm1 We have sized our devices such that gm3 , gm7
