power optimized lc vco and mixer co-design - Semantic Scholar
Power Optimized LC VCO & Mixer Co-design Byunghoo Jung, Shubha Bommalingaiahnapallya, and Ramesh Harjani Dept of ECE, University of Minnesota, MN 55455, USA Email: jbh:shubha:[email protected]
Abstract— A capacitively source degenerated buffer provides a negative impedance and can be used as the negative resistance cell in the voltage-controlled oscillator (VCO). This eliminates the need for a negative resistance cell within the VCO itself. Eliminating the negative resistance cell within the VCO allows us to reduce the overall power consumption for a design that combines a VCO with a follow-on mixer stage. Further, as the VCO directly drives the mixer, the input capacitance of the mixer can be incorporated into the degeneration capacitor of the negative resistance cell. In other words, the mixer and VCO when co-designed can result in a significantly more optimal design. This paper presents the design for a prototype 4 GHz LC VCO and a mixer that has been designed for a 5 GHz RF and 1 GHz IF radio application in the 0.18 µm TSMC CMOS technology.
I. I NTRODUCTION Integrated LC VCOs are critical building blocks in highperformance communication systems. The ever-increasing demand for bandwidth places very stringent frequency, power, and noise requirement on such systems. Significant research effort has been put into improving the noise and power performance of integrated LC VCOs. The majority of this effort is targeted at optimizing the LC tank and the negative resistance cell design [1] [2]. And bulk of this previous work is based on the cross-coupled negative resistance cell which offers itself to low-noise and easy differential implementations. Typically, the output of the negative resistance cell is buffered before it drives an internal capacitive load. In this design, the buffer in the VCO and the internal capacitive load presented by the mixer are designed to function as a negative resistance cell. And, the traditional negative resistance cell using cross-coupling is removed from the VCO enabling a low-power and low-noise design. Stated otherwise, this paper presents a low-power low-noise design technique that achieves optimization across the cell boundaries. The basic frequency dependent negative resistance cell is based on capacitive degeneration and has been used previously in [3][4]. Examples of the integrated differential implementations have been presented in [5]-[7].
impedance of a typical double-balanced mixer is dominantly capacitive, it can be used as the source degenerating capacitor - CS . The parallel LC oscillator in steady state can be modelled by the simplified circuit shown in Figure 2. RP represents the tank loss, REq the effective negative resistance generated by the active devices, and CEq the effective shunt capacitance contributed by the active devices in the negative resistance cell. For sustained oscillations, the magnitude of the effective negative resistance |REq | has to be smaller than RP . A. Negative resistance cell The most widely used negative resistance cell is the traditional cross-coupled negative-gm cell because of its simplicity and its ability for differential signaling. A capacitively source degenerated transistor can also generate a negative resistance. Resonator-based VCOs using this negative resistance cell has a very small effective capacitance which not only allows for a high-frequency design but also for a wide tuning range [7]. Even though small-signal analysis is insufficient to completely predict the large-signal behavior of an oscillator, it still provides designers with good insight and compares fairly well with the simulation results suggesting the appropriateness of this approach. Hence, we use small-signal models for the behavioral analysis of the different negative resistance cell. The input admittance and the corresponding effective shunt resistance and capacitance looking into the buffer input is given by : ³ ´ S −CS ωT + jωCS 1 + CCgs (1) YIn = ³ ´2 ¡ ¢ 2 S 1 + CCgs + ωωT
YIn YIn M3
II. LC TANK - BASED VCO D ESIGN Figure 1(a) shows a traditional cross-coupled negative resistance cell with buffer and (b) shows the proposed capacitively source degenerated buffer acting as a negative resistance cell. In many integrated transceiver designs, the buffer drives an internal capacitive load, CL , that can be replaced by CS in Figure 1(b). Because the buffer is working as negative resistance cell, a separate negative resistance cell is not required. Figure 3 shows the case where the VCO output directly drives the differential mixer input port. Since, the differential input
0-7803-8834-8/05/$20.00 ©2005 IEEE.
M4 Ma M1
Mb
M2
CS
Buffer
-R Cell
(a)
Buffer
CS
-R Cell and Buffer
(b)
Fig. 1. Cross-coupled negative resistance cell with buffer (a) and the proposed capacitively source degenerated negative resistance cell using buffer (b).
4393
´2
CS Cgs
+
¡ ωT ¢2
-500
ω
(2)
−0.5CS ωT ³ ´ S 0.5CS 1 + CCgs =³ ´2 ¡ ¢ 2 S 1 + CCgs + ωωT
CEq
-1000
REq [Ω]
REq =
³ 1+
(3)
-1500
-2000
where ωT is gm /Cgs . Equation (2) predicts a negative input resistance that has an absolute value which is inversely proportional to frequency. This topology also gives a high value of the negative to positive transition frequency for REq [7]. These characteristics make the capacitively degenerated negative resistance cell a promising candidate for a high frequency oscillator. Equation (3) predicts that the effective shunt capacitance is directly proportional to frequency and can be much smaller than Cgs or CS which allows for a high frequency oscillator with a wide tuning range. Figure 4 shows the simulated REq and CEq of the proposed negative resistance cell as a function of frequency. The negative resistance cell uses 1.5 mA bias current in each leg. It is essential that |REq | be small enough so as to compensate power loss through the finite Q of the tank and CEq be small enough so as not to limit the frequency tuning range.
-2500 1
[]
10 Frequency [GHz]
160
CEq [fF]
140
120
100
80 1
[]
B. Tank Design
10 Frequency [GHz]
Fig. 4.
Simulated REq (a) and CEq (b) results.
1400
The LC tank is realized by an inductor across the gates of the transistors in the buffer and two MOScap varactors across it. With three and half turns, the 3.8 nH inductor has a 3.02 Ω series resistance. The Q of the inductor at 4 GHz is around 13.6 . The source/drain node of the MOScap is connected to the center tapped varactor control voltage to eliminate the signal loss through source/drain to bulk parasitic capacitance. A MIM capacitor is inserted between the inductor
1200
Impedance [Ohm]
1000 800 600 400 200
-R Cell (active device) 0 1
10 Frequency [GHz]
L
CFix
CVar
Fig. 2.
RP
REq
CEq
Fig. 5.
and MOScap to make varactor biasing easy. The varactor network including MOScap and MIM coupling capacitor has a Q of about 19.8 at 4 GHz. Figure 5 shows the resonance curve of the designed LC tanks where fo is 4 GHz. The simulation includes the parasitic capacitance from the negative resistance cell. The tank Q is about 7.8 , and the impedance at resonance frequency is about 1.273 KΩ. To sustain oscillations, the absolute value of the negative resistance from the designed negative resistance cell has to be less than 1.273 KΩ.
Parallel LC oscillator model.
YIn
Ma
Mb
CS
Resonance curve for the designed LC tank.
CS
C. Common-Mode And Differential-Mode Oscillation
Mixer
YIn,M Fig. 3. Capacitively source degenerated negative resistance cell using internal mixer as load.
One distinct difference between the capacitively degenerated cell and the cross-coupled cell is its common-mode behavior. Each half circuit of the capacitively degenerated cell can provide negative resistance, unlike the cross-coupled cell. To
4394
ZIn,LC
VDD
L
ZBiasL
L
M3
LO+
M4
M5
M6
LO+
LO-
C
ZBiasC
C
VRF+
M1
VRF-
M2
VCon
Fig. 6.
Common mode oscillation mechanism.
Fig. 7.
prevent common-mode oscillation the impedance of the tank bias network which is shown in Figure 6 has to be maximized, and/or the load capacitance of the buffer has to be differential [7]. In the proposed design, the mixer input impedance is used as a load capacitor. The differential input impedance of the mixer is dominantly capacitive, but the common mode input impedance is not dominantly capacitive. This makes the proposed cell less susceptible to common-mode oscillations.
Schematic of the Gilbert Mixer.
Mixer Input Capacitance [fF]
93.5
III. M IXER D ESIGN
93.0
92.5
92.0 1
10 Frequency [GHz]
Fig. 8. Simulated differential input capacitance of the mixer as a function of frequency. 90 Mixer Input Capcitance [fF]
For the mixer, the well-known Gilbert cell topology was used. A simplified schematic is shown in Fig. 7. M1 and M2 act as V-I converters for the RF input. M3 - M6 act switch the tail current totally into one arm or the other at the LO frequency. This achieves multiplication in the current-domain. To minimize the noise figure, we consider the major noise contributors in the mixer at IF. The thermal noise from the load appears directly at the output. The thermal noise from the transconductor is gained by the conversion gain and the white noise from around the odd harmonics of the LO get downconverted to IF. The discrete sampling of the thermal noise of the switches when both the switches are on aliases the thermal noise of the switches to IF. To maximize the conversion gain of the mixer, the transconductance of the mixer has to be maximized. And to increase the linearity of the mixer, the linearity of the RF transconductors has to be increased. The above suggest that linearity, gain and noise-figure(NF) are conflicting requirements. This design optimizes for NF while maintaining sufficient gain and linearity. Drawing 3mA from a 2V supply, the mixer achieves a conversion gain of 6dB, IIP3 of about 0.6dBm and Noise figure of about 10.7dB.
88 Transistor On/Off 86 84 82 80 -1.0
-0.5
0.0
0.5
1.0
LO Voltage [V]
Fig. 9. Simulated differential input capacitance of the mixer as a function of the LO voltage.
VCon CV CV
VB
VB
M1
M2
IV. VCO AND M IXER C O - DESIGN
M3
To optimize the VCO-Mixer combination, it is worthwhile to study the input impedance of the Mixer which appears capacitive due to the Cgs of the MOSFETs. Figure 8 shows the simulated imaginary part of differential input impedance of the designed mixer as a function of frequency. The simulated capacitance is around 93 fF around 4 GHz. The total degeneration capacitor of the buffer must now take into account the input capacitance of the mixer.
4395
RL
RL
LS
CS IB1
CS IB1
VRF+ CC
Fig. 10.
M4
M5
M6
CC M1
M2
IB2
Designed VCO and mixer (Bias details not included).
VRF-
0
-80 Normalized Output Spectrum [dB]
IF
Phase Noise [dBc/Hz]
-90 -100 -110 -120 -130 -140 100
Fig. 11.
10000
Oscillation Frequency [GHz]
-120
-160
0
Simulated phase noise results.
Fig. 13.
4.0
3.9
3.8 0.4
0.8
1
2
3
4
5
Frequency [GHz]
4.1
1.2
1.6
Control Voltage [V]
Fig. 12.
-80
-200 1000 Frequency [KHz]
0.0
LO
-40
Simulated VCO tuning range results.
As the LO swing is high for minimization of the noise, it is necessary to note its effect on the input capacitance of the mixer. Figure 9 shows the simulated imaginary part of differential input impedance of the designed mixer as a function of input voltage. The VCO signal will alternatively turn on and off the M3/M4 pair and M5/M6 pairs. This operation keeps the equivalent input capacitance relatively constant. But as Figure 9 shows, it is still a function of input voltage. Thus, the negative resistance of the designed negative resistance cell has output voltage dependent negative resistance. To sustain constant oscillations, the absolute value of the average negative resistance has to be smaller than the effective parallel resistance of the tank. A 4 GHz VCO with a 5% GHz tuning range and a mixer working as a capacitive load for the VCO have been designed in TSMC 0.18µ m CMOS technology. At 4GHz, the simulated REq ≈ −980 Ω and CEq ≈ 125 fF. The capacitive impedance looking into the mixer works as a portion of the source degeneration capacitance was about 93 fF. Figure 11 shows the simulated phase noise. The phase noise was −88 dBc/Hz and −109.4 dBc/Hz at 100 KHz and 1 MHz offset from 4 GHz respectively. Figure 12 shows more than 0.4 GHz (5%) tuning range. Figure 13 shows the simulated IF spectrum from the designed VCO and Mixer circuit. The closest spur is about 60dB lower. The VCO core consumes 3 mA, and the mixer core drains 3 mA. Both work off a 2 V supply. This low total current supports the low-power capability of the proposed design.
Simulated output spectrum for the VCO and mixer circuit
V. C ONCLUSIONS This paper presents the co-design of a VCO and mixer. The VCO has negative resistance cell using capacitive source degeneration. Instead of using a separate buffer stage that is common in cross-coupled VCO topology, only a buffer is connected to the LC tank, and the capacitive input impedance of mixer stage is used as a source degenerating capacitance for the buffer to generate the required negative resistance. This topology makes the design power efficient and simple, hence robust. The VCO and mixer for 5 GHz RF, 4 GHz LO, and 1 GHz IF wireless radio application are designed in TSMC 0.18 µm CMOS technology. The designed VCO shows −110 dBc/Hz phase noise at 1 MHz offset and 5 % tuning range with 3 mW power consumption. The designed mixer has a +0.6 dBm IIP 3 and consumes 6 mW power. The mixer with the LO signal from the designed VCO shows 10.7 dB NF and 6 dB downconversion gain. The successful operation of the co-designed VCO and mixer shows the appropriateness of the proposed design technique. Although the example in this design shows VCO and mixer co-design case, any other load stage that has capacitive input impedance can be easily co-designed with the VCO. R EFERENCES [1] Donhee Ham and Ali Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, pp. 896909, June 2001. [2] John R. Long and Miles A. Copeland, “The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC’s,” IEEE J. SolidState Circuits, vol. 32, pp. 357-369, Mar. 1997. [3] Robert T. Oyafuso, “An 8−18 GHz FET YIG-Tuned Oscillator,” in IEEE Int. Microwave Symp. Dig., 1979, pp. 183-184. [4] Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, and David L. Harame, “An 11−GHz 3−V SiGe Voltage Controlled Oscillator with Integrated Resonator,” in IEEE J. Solid-State Circuits, vol. 32, pp. 14511454, Sept. 1997. [5] Hugo Veenstra and Edwin van der Heijden, “A 35.2-37.6GHz LC VCO in a 70/100GHz fT /fmax SiGe Technology,” in ISSCC Dig. Tech. Papers, 2004, pp. 394-395. [6] Byunghoo Jung and Ramesh Harjani, “A 20GHz VCO with 5GHz Tuning Range in 0.25µm SiGe BiCMOS,” in ISSCC Dig. Tech. Papers, 2004, pp. 178-179. [7] Byunghoo Jung and Ramesh Harjani, “High-Frequency LC VCO Design Using Capacitive Degeneration,” in IEEE J. Solid-State Circuits, to be published.
4396
Abstract— A capacitively source degenerated buffer provides a negative impedance and can be used as the negative resistance cell in the voltage-controlled oscillator (VCO). This eliminates the need for a negative resistance cell within the VCO itself. Eliminating the negative resistance cell within the VCO allows us to reduce the overall power consumption for a design that combines a VCO with a follow-on mixer stage. Further, as the VCO directly drives the mixer, the input capacitance of the mixer can be incorporated into the degeneration capacitor of the negative resistance cell. In other words, the mixer and VCO when co-designed can result in a significantly more optimal design. This paper presents the design for a prototype 4 GHz LC VCO and a mixer that has been designed for a 5 GHz RF and 1 GHz IF radio application in the 0.18 µm TSMC CMOS technology.
I. I NTRODUCTION Integrated LC VCOs are critical building blocks in highperformance communication systems. The ever-increasing demand for bandwidth places very stringent frequency, power, and noise requirement on such systems. Significant research effort has been put into improving the noise and power performance of integrated LC VCOs. The majority of this effort is targeted at optimizing the LC tank and the negative resistance cell design [1] [2]. And bulk of this previous work is based on the cross-coupled negative resistance cell which offers itself to low-noise and easy differential implementations. Typically, the output of the negative resistance cell is buffered before it drives an internal capacitive load. In this design, the buffer in the VCO and the internal capacitive load presented by the mixer are designed to function as a negative resistance cell. And, the traditional negative resistance cell using cross-coupling is removed from the VCO enabling a low-power and low-noise design. Stated otherwise, this paper presents a low-power low-noise design technique that achieves optimization across the cell boundaries. The basic frequency dependent negative resistance cell is based on capacitive degeneration and has been used previously in [3][4]. Examples of the integrated differential implementations have been presented in [5]-[7].
impedance of a typical double-balanced mixer is dominantly capacitive, it can be used as the source degenerating capacitor - CS . The parallel LC oscillator in steady state can be modelled by the simplified circuit shown in Figure 2. RP represents the tank loss, REq the effective negative resistance generated by the active devices, and CEq the effective shunt capacitance contributed by the active devices in the negative resistance cell. For sustained oscillations, the magnitude of the effective negative resistance |REq | has to be smaller than RP . A. Negative resistance cell The most widely used negative resistance cell is the traditional cross-coupled negative-gm cell because of its simplicity and its ability for differential signaling. A capacitively source degenerated transistor can also generate a negative resistance. Resonator-based VCOs using this negative resistance cell has a very small effective capacitance which not only allows for a high-frequency design but also for a wide tuning range [7]. Even though small-signal analysis is insufficient to completely predict the large-signal behavior of an oscillator, it still provides designers with good insight and compares fairly well with the simulation results suggesting the appropriateness of this approach. Hence, we use small-signal models for the behavioral analysis of the different negative resistance cell. The input admittance and the corresponding effective shunt resistance and capacitance looking into the buffer input is given by : ³ ´ S −CS ωT + jωCS 1 + CCgs (1) YIn = ³ ´2 ¡ ¢ 2 S 1 + CCgs + ωωT
YIn YIn M3
II. LC TANK - BASED VCO D ESIGN Figure 1(a) shows a traditional cross-coupled negative resistance cell with buffer and (b) shows the proposed capacitively source degenerated buffer acting as a negative resistance cell. In many integrated transceiver designs, the buffer drives an internal capacitive load, CL , that can be replaced by CS in Figure 1(b). Because the buffer is working as negative resistance cell, a separate negative resistance cell is not required. Figure 3 shows the case where the VCO output directly drives the differential mixer input port. Since, the differential input
0-7803-8834-8/05/$20.00 ©2005 IEEE.
M4 Ma M1
Mb
M2
CS
Buffer
-R Cell
(a)
Buffer
CS
-R Cell and Buffer
(b)
Fig. 1. Cross-coupled negative resistance cell with buffer (a) and the proposed capacitively source degenerated negative resistance cell using buffer (b).
4393
´2
CS Cgs
+
¡ ωT ¢2
-500
ω
(2)
−0.5CS ωT ³ ´ S 0.5CS 1 + CCgs =³ ´2 ¡ ¢ 2 S 1 + CCgs + ωωT
CEq
-1000
REq [Ω]
REq =
³ 1+
(3)
-1500
-2000
where ωT is gm /Cgs . Equation (2) predicts a negative input resistance that has an absolute value which is inversely proportional to frequency. This topology also gives a high value of the negative to positive transition frequency for REq [7]. These characteristics make the capacitively degenerated negative resistance cell a promising candidate for a high frequency oscillator. Equation (3) predicts that the effective shunt capacitance is directly proportional to frequency and can be much smaller than Cgs or CS which allows for a high frequency oscillator with a wide tuning range. Figure 4 shows the simulated REq and CEq of the proposed negative resistance cell as a function of frequency. The negative resistance cell uses 1.5 mA bias current in each leg. It is essential that |REq | be small enough so as to compensate power loss through the finite Q of the tank and CEq be small enough so as not to limit the frequency tuning range.
-2500 1
[]
10 Frequency [GHz]
160
CEq [fF]
140
120
100
80 1
[]
B. Tank Design
10 Frequency [GHz]
Fig. 4.
Simulated REq (a) and CEq (b) results.
1400
The LC tank is realized by an inductor across the gates of the transistors in the buffer and two MOScap varactors across it. With three and half turns, the 3.8 nH inductor has a 3.02 Ω series resistance. The Q of the inductor at 4 GHz is around 13.6 . The source/drain node of the MOScap is connected to the center tapped varactor control voltage to eliminate the signal loss through source/drain to bulk parasitic capacitance. A MIM capacitor is inserted between the inductor
1200
Impedance [Ohm]
1000 800 600 400 200
-R Cell (active device) 0 1
10 Frequency [GHz]
L
CFix
CVar
Fig. 2.
RP
REq
CEq
Fig. 5.
and MOScap to make varactor biasing easy. The varactor network including MOScap and MIM coupling capacitor has a Q of about 19.8 at 4 GHz. Figure 5 shows the resonance curve of the designed LC tanks where fo is 4 GHz. The simulation includes the parasitic capacitance from the negative resistance cell. The tank Q is about 7.8 , and the impedance at resonance frequency is about 1.273 KΩ. To sustain oscillations, the absolute value of the negative resistance from the designed negative resistance cell has to be less than 1.273 KΩ.
Parallel LC oscillator model.
YIn
Ma
Mb
CS
Resonance curve for the designed LC tank.
CS
C. Common-Mode And Differential-Mode Oscillation
Mixer
YIn,M Fig. 3. Capacitively source degenerated negative resistance cell using internal mixer as load.
One distinct difference between the capacitively degenerated cell and the cross-coupled cell is its common-mode behavior. Each half circuit of the capacitively degenerated cell can provide negative resistance, unlike the cross-coupled cell. To
4394
ZIn,LC
VDD
L
ZBiasL
L
M3
LO+
M4
M5
M6
LO+
LO-
C
ZBiasC
C
VRF+
M1
VRF-
M2
VCon
Fig. 6.
Common mode oscillation mechanism.
Fig. 7.
prevent common-mode oscillation the impedance of the tank bias network which is shown in Figure 6 has to be maximized, and/or the load capacitance of the buffer has to be differential [7]. In the proposed design, the mixer input impedance is used as a load capacitor. The differential input impedance of the mixer is dominantly capacitive, but the common mode input impedance is not dominantly capacitive. This makes the proposed cell less susceptible to common-mode oscillations.
Schematic of the Gilbert Mixer.
Mixer Input Capacitance [fF]
93.5
III. M IXER D ESIGN
93.0
92.5
92.0 1
10 Frequency [GHz]
Fig. 8. Simulated differential input capacitance of the mixer as a function of frequency. 90 Mixer Input Capcitance [fF]
For the mixer, the well-known Gilbert cell topology was used. A simplified schematic is shown in Fig. 7. M1 and M2 act as V-I converters for the RF input. M3 - M6 act switch the tail current totally into one arm or the other at the LO frequency. This achieves multiplication in the current-domain. To minimize the noise figure, we consider the major noise contributors in the mixer at IF. The thermal noise from the load appears directly at the output. The thermal noise from the transconductor is gained by the conversion gain and the white noise from around the odd harmonics of the LO get downconverted to IF. The discrete sampling of the thermal noise of the switches when both the switches are on aliases the thermal noise of the switches to IF. To maximize the conversion gain of the mixer, the transconductance of the mixer has to be maximized. And to increase the linearity of the mixer, the linearity of the RF transconductors has to be increased. The above suggest that linearity, gain and noise-figure(NF) are conflicting requirements. This design optimizes for NF while maintaining sufficient gain and linearity. Drawing 3mA from a 2V supply, the mixer achieves a conversion gain of 6dB, IIP3 of about 0.6dBm and Noise figure of about 10.7dB.
88 Transistor On/Off 86 84 82 80 -1.0
-0.5
0.0
0.5
1.0
LO Voltage [V]
Fig. 9. Simulated differential input capacitance of the mixer as a function of the LO voltage.
VCon CV CV
VB
VB
M1
M2
IV. VCO AND M IXER C O - DESIGN
M3
To optimize the VCO-Mixer combination, it is worthwhile to study the input impedance of the Mixer which appears capacitive due to the Cgs of the MOSFETs. Figure 8 shows the simulated imaginary part of differential input impedance of the designed mixer as a function of frequency. The simulated capacitance is around 93 fF around 4 GHz. The total degeneration capacitor of the buffer must now take into account the input capacitance of the mixer.
4395
RL
RL
LS
CS IB1
CS IB1
VRF+ CC
Fig. 10.
M4
M5
M6
CC M1
M2
IB2
Designed VCO and mixer (Bias details not included).
VRF-
0
-80 Normalized Output Spectrum [dB]
IF
Phase Noise [dBc/Hz]
-90 -100 -110 -120 -130 -140 100
Fig. 11.
10000
Oscillation Frequency [GHz]
-120
-160
0
Simulated phase noise results.
Fig. 13.
4.0
3.9
3.8 0.4
0.8
1
2
3
4
5
Frequency [GHz]
4.1
1.2
1.6
Control Voltage [V]
Fig. 12.
-80
-200 1000 Frequency [KHz]
0.0
LO
-40
Simulated VCO tuning range results.
As the LO swing is high for minimization of the noise, it is necessary to note its effect on the input capacitance of the mixer. Figure 9 shows the simulated imaginary part of differential input impedance of the designed mixer as a function of input voltage. The VCO signal will alternatively turn on and off the M3/M4 pair and M5/M6 pairs. This operation keeps the equivalent input capacitance relatively constant. But as Figure 9 shows, it is still a function of input voltage. Thus, the negative resistance of the designed negative resistance cell has output voltage dependent negative resistance. To sustain constant oscillations, the absolute value of the average negative resistance has to be smaller than the effective parallel resistance of the tank. A 4 GHz VCO with a 5% GHz tuning range and a mixer working as a capacitive load for the VCO have been designed in TSMC 0.18µ m CMOS technology. At 4GHz, the simulated REq ≈ −980 Ω and CEq ≈ 125 fF. The capacitive impedance looking into the mixer works as a portion of the source degeneration capacitance was about 93 fF. Figure 11 shows the simulated phase noise. The phase noise was −88 dBc/Hz and −109.4 dBc/Hz at 100 KHz and 1 MHz offset from 4 GHz respectively. Figure 12 shows more than 0.4 GHz (5%) tuning range. Figure 13 shows the simulated IF spectrum from the designed VCO and Mixer circuit. The closest spur is about 60dB lower. The VCO core consumes 3 mA, and the mixer core drains 3 mA. Both work off a 2 V supply. This low total current supports the low-power capability of the proposed design.
Simulated output spectrum for the VCO and mixer circuit
V. C ONCLUSIONS This paper presents the co-design of a VCO and mixer. The VCO has negative resistance cell using capacitive source degeneration. Instead of using a separate buffer stage that is common in cross-coupled VCO topology, only a buffer is connected to the LC tank, and the capacitive input impedance of mixer stage is used as a source degenerating capacitance for the buffer to generate the required negative resistance. This topology makes the design power efficient and simple, hence robust. The VCO and mixer for 5 GHz RF, 4 GHz LO, and 1 GHz IF wireless radio application are designed in TSMC 0.18 µm CMOS technology. The designed VCO shows −110 dBc/Hz phase noise at 1 MHz offset and 5 % tuning range with 3 mW power consumption. The designed mixer has a +0.6 dBm IIP 3 and consumes 6 mW power. The mixer with the LO signal from the designed VCO shows 10.7 dB NF and 6 dB downconversion gain. The successful operation of the co-designed VCO and mixer shows the appropriateness of the proposed design technique. Although the example in this design shows VCO and mixer co-design case, any other load stage that has capacitive input impedance can be easily co-designed with the VCO. R EFERENCES [1] Donhee Ham and Ali Hajimiri, “Concepts and Methods in Optimization of Integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 36, pp. 896909, June 2001. [2] John R. Long and Miles A. Copeland, “The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC’s,” IEEE J. SolidState Circuits, vol. 32, pp. 357-369, Mar. 1997. [3] Robert T. Oyafuso, “An 8−18 GHz FET YIG-Tuned Oscillator,” in IEEE Int. Microwave Symp. Dig., 1979, pp. 183-184. [4] Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, and David L. Harame, “An 11−GHz 3−V SiGe Voltage Controlled Oscillator with Integrated Resonator,” in IEEE J. Solid-State Circuits, vol. 32, pp. 14511454, Sept. 1997. [5] Hugo Veenstra and Edwin van der Heijden, “A 35.2-37.6GHz LC VCO in a 70/100GHz fT /fmax SiGe Technology,” in ISSCC Dig. Tech. Papers, 2004, pp. 394-395. [6] Byunghoo Jung and Ramesh Harjani, “A 20GHz VCO with 5GHz Tuning Range in 0.25µm SiGe BiCMOS,” in ISSCC Dig. Tech. Papers, 2004, pp. 178-179. [7] Byunghoo Jung and Ramesh Harjani, “High-Frequency LC VCO Design Using Capacitive Degeneration,” in IEEE J. Solid-State Circuits, to be published.
4396
