A Power-Optimized CMOS LC VCO with Wide ... - Semantic Scholar
A Power-Optimized CMOS LC VCO with Wide Tuning Range in 0.5-V Supply Dongmin Park and Seonghwan Cho Korea Advanced Institute of Science and Technology (KAIST) Daejon, Republic of Korea Email: [email protected], [email protected]
Abstract— A power-optimized low-voltage VCO with wide tuning range is proposed. The VCO achieves low power by optimum selection of inductance in the L-C tank. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosted digital tuning technique. It is shown that the power consumption of VCO with a required output swing and phase noise can be minimized if the inductance is chosen such that its LQ and Q/L is maximized. To increase the tuning range, a digital tuning method is used where the output voltage of the VCO is exploited to generate a high voltage for the switches in the digital tuning scheme. The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 µA in 0.5-V supply. Figureof-merit with tuning range of the proposed VCO is -197.1 dB, which is the lowest among the recent state-of-the-art low-voltage VCOs.
I. I NTRODUCTION Due to the explosive growth of low-cost mobile wireless hand-held devices, power consumption has become one of the most important design criteria in digital, analog and RF circuits. To reduce the power consumption of a system, power supply reduction has been a popular method, especially for digital circuits where voltage scaling has been pushed beyond the subthreshold voltage [1]. However, in analog and RF circuits, voltage scaling cannot be sustained mainly due to noise reasons and hence the analog and RF circuits must rely on high supply voltage. Hence, circuit designers have recently been trying to lower the power supply in analog and RF circuits [2], [3], [4], [5]. In RF circuits, there has been active research for low-power low-voltage VCOs [4], [5]. In [4] and [5], low-voltage VCOs are successfully demonstrated but the limited tuning range make it difficult for the VCOs to be used in practical systems. In this paper, a low-voltage CMOS VCO with wide tuning range is proposed. Despite the near threshold supply voltage, the VCO achieves wide tuning range by using digital tuning scheme with voltage boosting technique. In addition, the power consumption is minimized by choosing an optimum value of the inductor in the L-C tank. II. D ESIGN C ONSIDERATIONS OF P OWER -O PTIMIZED VCO S A. The Topology of Low-voltage VCOs While there are several VCO topologies, the complementary cross-coupled VCO topology (Fig. 1(a)) is popular due to its
(a)
(b)
Fig. 1. Conventional VCO. (a) Complementary. (b) nMOS only without tail current source.
ability to reduce 1/f noise [6]. However, this topology is not suitable for low supply voltage because of the voltage headroom cut down by the pMOS and the tail current source. The topology shown in Fig. 1(b) is better suited for near threshold supply voltage since its headroom is no longer limited by the current source or the pMOS. In addition, since the DC output of the VCO is biased at VDD , the output swing of the VCO can be as high as 2VDD . B. L, C Optimization for Low-Power There has been a great deal of research on low-power lowphase-noise VCOs. Unfortunately, little has been discussed on how to choose the optimum value of inductor in an LC-tank. The optimum tank values suggested in [6] minimizes the phase noise under a certain power consumption constraint, rather than minimizing power consumption under a certain phase noise constraint. In addition, it disregards the specification for the output amplitude of the VCO. The approach proposed in this paper minimizes power consumption under a specified
12 10
6 4
60
Optimum point
Low phase noise
3 Low power
40 2
LQ (10-9)
Q/L (109)
4
8
Q
80
5
20 1
2 0
0 2
3
4
5
6
7
8
9
10
0 2
3
4
L (nH) Fig. 3.
phase noise and output amplitude constraints. The single-sideband noise spectral density is expressed as L{∆ω} = 10 log
2F kT Ps
2F kT ≈ 10 log Ps
1+
ω0 2Q∆ω 2
2 ∆ω1/f 3 1+ |∆ω|
ω0 2Q∆ω
(1)
where Ps is the average power dissipated and Q is the quality factor of the tank [7]. From the definition of Q, the Ps can be represented as the following, Ps =
Estored = ωQ
1 2 2 CVamp
ωQ
=
1 2 2 Vamp ω 3 LQ
∝
1 LQ
(2)
where Vamp is the amplitude of the VCO output. Since Vamp is determined by a certain specification, it can be seen that the power consumption is inversely proportional to LQ for a given output amplitude and oscillation frequency. Combining Eq. (1) and Eq. (2), we obtain
L{∆ω} ≈ ∝
6
7
8
9
10
L (nH)
Q vs. L @ 2.4 GHz.
Fig. 2.
5
F kT ω 3 10 log LQ 2 Vamp 1 10 log . Q/L
ω0 Q∆ω
2
(3)
The phase noise of the VCO shown in Eq. (3) is inversely proportional to the value of Q/L. With higher Q/L, the phase noise of VCO improves. From Eq. (2) and Eq. (3), it can be seen that power consumption and phse noise can be minimized if LQ and Q/L are maximized, respectively. However, since Q is a function of L as shown in Fig. 2, LQ and Q/L cannot be maximized simultaneously. This can be seen in Fig. 3, where LQ and Q/L are plotted versus different values of L. Note in this graph that Q/L determines the phase noise while LQ determines the power consumption of the VCO. Therefore, for
Q/L and LQ vs. L @ 2.4 GHz.
a specified phase noise requirement, a lower limit can be set for Q/L. That is, in order to meet the phase noise requirement, the inductor must be chosen such that its Q/L is larger than what is specified by the phase noise requirement. Among the various inductor values which meet this requirement, the inductor should be chosen such that LQ is maximized, in order to minimize power consumption. III. W IDE T UNING R ANGE IN NEAR T HRESHOLD S UPPLY VOLTAGE A critical drawback of the low-voltage VCO is that its control voltage is limited. For a 0.5-V supply, the input range of the control voltage is limited to only a couple of hundreds of millivolts, considering the headroom required for the current source in the charge pump. Therefore, the tuning range of the VCO is severely limited. While the tuning range can be increase by using digital tuning technique [8], the low supply voltage makes it difficult to fully turn on the switches of the digital tuning cells, thereby degrading the quality factor. In order to achieve a high enough voltage to fully turn on the switches, a voltage boosting scheme is proposed as shown in Fig. 4. Since the output of the VCO reaches voltage level as high as 2VDD , the main idea is to regulate this VCO output and use it as the power supply for the digital switches. The voltage boosting circuit consists of a PMOS that regulates the VCO output near its highest voltage and a capacitor that stores this voltage (VDD dig ). In order to maintain the symmetry of the VCO , two voltage boosting circuits are paired as shown in Fig. 4. When Vout n goes low and Vout p goes high, one pMOS is turned on and the other is turned off. The pMOS that is turned on charges the capacitor to VDD dig which is near the maximum VCO output. Once the capacitor is fully charged, the circuit does not consume any power. IV. S IMULATION R ESULTS The VCO is designed using a 0.18-µm CMOS process at 0.5-V supply. The digital tuning block is composed of 3-bit
VDD Vout_n
Vout_p
VDD_dig
Voltage Boosting Circuit
Vout_n
Vout_p VDD_dig
VDD_dig boff
Vout_n
Vout_p
Ma0 Ma3-4
Ma1
Ma2
VDD_dig
Fig. 4.
Schematics of a proposed VCO with the voltage boosting circuit and the digital tuning block [8].
2.8
1.2
2.7
Frequency (GHz)
voltage (V)
1 0.8 0.6 0.4
2.5
2.4
0.2 0 120 n
2.6
2.3
150 n
180 n
210 n
240 n
270 n
300 n
0
0.1
0.2
time (s) Fig. 5. Transient response of VCO output and voltage boosting circuit output.
binary weighted capacitors and the inductance is 9.55 nH with a quality factor of 7.88. The simulation is performed on the extracted layout netlist which includes the parasitic resistance and capacitance of the VCO as well as the peripheral circuitry such as buffers and output pads. The transient response is shown in Fig. 5 where the bold black line represents the output of the voltage boosting circuit and the grey line represents the output of the VCO. It shows the outputs as the digital values of the digital tuning block
0.3
0.4
0.5
Vctrl (V) Fig. 6.
Tuning Range.
changes. The tuning characteristic of the VCO is shown in Fig. 6, where it can be seen that the VCO achieves 18 % tuning range. The phase noise of the VCO at 2.33GHz is shown in Fig. 7, where it can be seen that the VCO achieves phase noise of -120dBc/Hz at 1-MHz offset while consuming 660 µA of current. The result of the VCO is summarized in Table I together with the recent state-of-the-art low-voltage VCOs. The layout of the VCO is shown in Fig. 8.
TABLE I C OMPARISON OF LOW- VOLTAGE VCO S . [4] 0.5 V 570 µA 3.8 GHz 3% -119 dBc/Hz -193 dB -182.5 dB
Supply Voltage Current Consumption Center Frequency Tuning Range Phase Noise (@ 1 MHz) FOM a FOMT b a FOM
[5] 1V 4.6 mA 2.42 GHz 1.7 % -134 dBc/Hz -195 dB -179.6 dB
This work 0.5 V 660 µA 2.56 GHz 18 % -120 dBc/Hz -192 dB -197.1 dB
ω 0 + 10 log PDC [5]. ∆ω 1mW FTR
= L{∆ω} − 20 log
b FOM = FOM − 20 log T in percent [9].
10
where the FTR is the frequency tuning range
0
Phase Noise (dBc/Hz)
-20 -40 -60 -80 -100 -120 -140 -160 1 kHz
10 kHz
100 kHz
1MHz
10MHz
Frequency Offset Fig. 7.
Phase Noise @ 2.33 GHz.
V. C ONCLUSIONS The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 µA at 0.5-V supply. The low power is achieved by a novel LC optimization scheme and the wide tuning range is achieved by digital tuning with voltage boosting technique. VI. ACKNOWLEDGMENTS This work is supported by Samsung Electro-Mechanics CO., LTD. The authors would like to thank M. S. Kim, T. J. Park and H. S. Kim of Samsung Electro-Mechanics CO., LTD and Y. W. Ku of KAIST for his advice and support. The CAD tools have been supported by IC Design Center (IDEC) of KAIST. R EFERENCES [1] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, pp. 310–319, Jan. 2005. [2] G. C. T. Leung and H. C. Luong, “A 1-V 5.2-GHz CMOS synthesizer for WLAN applications,” IEEE J. Solid-State Circuits, vol. 40, pp. 1873– 1882, Nov. 2004. [3] S. Cho and A. P. Chandrakasan, “A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications,” IEEE J. Solid-State Circuits, vol. 39, pp. 731–739, May 2004.
Fig. 8.
Layout of the proposed VCO.
[4] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, pp. 652–660, Mar. 2005. [5] Z. Li and K. K. O., “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE J. Solid-State Circuits, vol. 40, pp. 1296–1302, June 2005. [6] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 33, pp. 179– 194, Feb. 1998. [7] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 36, pp. 896–909, June 2001. [8] A. D. Berny, A. M. Niknejad, and R. G. Meyer, “A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration,” IEEE J. Solid-State Circuits, vol. 40, pp. 909–917, Apr. 2005. [9] J. Kim, J. Plouchart, N. Zamdmer, M.Cherony, Y. Tan, M. Yoon, R. Trzcinski, M. Talbi, J. Safran, A. Ray, and L. Wagner, “A poweroptimized widely-tunable 5-GHZ monolithic VCO in a digital SOI CMOS technology on high resistivity substrate,” in Proc. ISLPED, 2003, pp. 434– 439.
Abstract— A power-optimized low-voltage VCO with wide tuning range is proposed. The VCO achieves low power by optimum selection of inductance in the L-C tank. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosted digital tuning technique. It is shown that the power consumption of VCO with a required output swing and phase noise can be minimized if the inductance is chosen such that its LQ and Q/L is maximized. To increase the tuning range, a digital tuning method is used where the output voltage of the VCO is exploited to generate a high voltage for the switches in the digital tuning scheme. The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 µA in 0.5-V supply. Figureof-merit with tuning range of the proposed VCO is -197.1 dB, which is the lowest among the recent state-of-the-art low-voltage VCOs.
I. I NTRODUCTION Due to the explosive growth of low-cost mobile wireless hand-held devices, power consumption has become one of the most important design criteria in digital, analog and RF circuits. To reduce the power consumption of a system, power supply reduction has been a popular method, especially for digital circuits where voltage scaling has been pushed beyond the subthreshold voltage [1]. However, in analog and RF circuits, voltage scaling cannot be sustained mainly due to noise reasons and hence the analog and RF circuits must rely on high supply voltage. Hence, circuit designers have recently been trying to lower the power supply in analog and RF circuits [2], [3], [4], [5]. In RF circuits, there has been active research for low-power low-voltage VCOs [4], [5]. In [4] and [5], low-voltage VCOs are successfully demonstrated but the limited tuning range make it difficult for the VCOs to be used in practical systems. In this paper, a low-voltage CMOS VCO with wide tuning range is proposed. Despite the near threshold supply voltage, the VCO achieves wide tuning range by using digital tuning scheme with voltage boosting technique. In addition, the power consumption is minimized by choosing an optimum value of the inductor in the L-C tank. II. D ESIGN C ONSIDERATIONS OF P OWER -O PTIMIZED VCO S A. The Topology of Low-voltage VCOs While there are several VCO topologies, the complementary cross-coupled VCO topology (Fig. 1(a)) is popular due to its
(a)
(b)
Fig. 1. Conventional VCO. (a) Complementary. (b) nMOS only without tail current source.
ability to reduce 1/f noise [6]. However, this topology is not suitable for low supply voltage because of the voltage headroom cut down by the pMOS and the tail current source. The topology shown in Fig. 1(b) is better suited for near threshold supply voltage since its headroom is no longer limited by the current source or the pMOS. In addition, since the DC output of the VCO is biased at VDD , the output swing of the VCO can be as high as 2VDD . B. L, C Optimization for Low-Power There has been a great deal of research on low-power lowphase-noise VCOs. Unfortunately, little has been discussed on how to choose the optimum value of inductor in an LC-tank. The optimum tank values suggested in [6] minimizes the phase noise under a certain power consumption constraint, rather than minimizing power consumption under a certain phase noise constraint. In addition, it disregards the specification for the output amplitude of the VCO. The approach proposed in this paper minimizes power consumption under a specified
12 10
6 4
60
Optimum point
Low phase noise
3 Low power
40 2
LQ (10-9)
Q/L (109)
4
8
Q
80
5
20 1
2 0
0 2
3
4
5
6
7
8
9
10
0 2
3
4
L (nH) Fig. 3.
phase noise and output amplitude constraints. The single-sideband noise spectral density is expressed as L{∆ω} = 10 log
2F kT Ps
2F kT ≈ 10 log Ps
1+
ω0 2Q∆ω 2
2 ∆ω1/f 3 1+ |∆ω|
ω0 2Q∆ω
(1)
where Ps is the average power dissipated and Q is the quality factor of the tank [7]. From the definition of Q, the Ps can be represented as the following, Ps =
Estored = ωQ
1 2 2 CVamp
ωQ
=
1 2 2 Vamp ω 3 LQ
∝
1 LQ
(2)
where Vamp is the amplitude of the VCO output. Since Vamp is determined by a certain specification, it can be seen that the power consumption is inversely proportional to LQ for a given output amplitude and oscillation frequency. Combining Eq. (1) and Eq. (2), we obtain
L{∆ω} ≈ ∝
6
7
8
9
10
L (nH)
Q vs. L @ 2.4 GHz.
Fig. 2.
5
F kT ω 3 10 log LQ 2 Vamp 1 10 log . Q/L
ω0 Q∆ω
2
(3)
The phase noise of the VCO shown in Eq. (3) is inversely proportional to the value of Q/L. With higher Q/L, the phase noise of VCO improves. From Eq. (2) and Eq. (3), it can be seen that power consumption and phse noise can be minimized if LQ and Q/L are maximized, respectively. However, since Q is a function of L as shown in Fig. 2, LQ and Q/L cannot be maximized simultaneously. This can be seen in Fig. 3, where LQ and Q/L are plotted versus different values of L. Note in this graph that Q/L determines the phase noise while LQ determines the power consumption of the VCO. Therefore, for
Q/L and LQ vs. L @ 2.4 GHz.
a specified phase noise requirement, a lower limit can be set for Q/L. That is, in order to meet the phase noise requirement, the inductor must be chosen such that its Q/L is larger than what is specified by the phase noise requirement. Among the various inductor values which meet this requirement, the inductor should be chosen such that LQ is maximized, in order to minimize power consumption. III. W IDE T UNING R ANGE IN NEAR T HRESHOLD S UPPLY VOLTAGE A critical drawback of the low-voltage VCO is that its control voltage is limited. For a 0.5-V supply, the input range of the control voltage is limited to only a couple of hundreds of millivolts, considering the headroom required for the current source in the charge pump. Therefore, the tuning range of the VCO is severely limited. While the tuning range can be increase by using digital tuning technique [8], the low supply voltage makes it difficult to fully turn on the switches of the digital tuning cells, thereby degrading the quality factor. In order to achieve a high enough voltage to fully turn on the switches, a voltage boosting scheme is proposed as shown in Fig. 4. Since the output of the VCO reaches voltage level as high as 2VDD , the main idea is to regulate this VCO output and use it as the power supply for the digital switches. The voltage boosting circuit consists of a PMOS that regulates the VCO output near its highest voltage and a capacitor that stores this voltage (VDD dig ). In order to maintain the symmetry of the VCO , two voltage boosting circuits are paired as shown in Fig. 4. When Vout n goes low and Vout p goes high, one pMOS is turned on and the other is turned off. The pMOS that is turned on charges the capacitor to VDD dig which is near the maximum VCO output. Once the capacitor is fully charged, the circuit does not consume any power. IV. S IMULATION R ESULTS The VCO is designed using a 0.18-µm CMOS process at 0.5-V supply. The digital tuning block is composed of 3-bit
VDD Vout_n
Vout_p
VDD_dig
Voltage Boosting Circuit
Vout_n
Vout_p VDD_dig
VDD_dig boff
Vout_n
Vout_p
Ma0 Ma3-4
Ma1
Ma2
VDD_dig
Fig. 4.
Schematics of a proposed VCO with the voltage boosting circuit and the digital tuning block [8].
2.8
1.2
2.7
Frequency (GHz)
voltage (V)
1 0.8 0.6 0.4
2.5
2.4
0.2 0 120 n
2.6
2.3
150 n
180 n
210 n
240 n
270 n
300 n
0
0.1
0.2
time (s) Fig. 5. Transient response of VCO output and voltage boosting circuit output.
binary weighted capacitors and the inductance is 9.55 nH with a quality factor of 7.88. The simulation is performed on the extracted layout netlist which includes the parasitic resistance and capacitance of the VCO as well as the peripheral circuitry such as buffers and output pads. The transient response is shown in Fig. 5 where the bold black line represents the output of the voltage boosting circuit and the grey line represents the output of the VCO. It shows the outputs as the digital values of the digital tuning block
0.3
0.4
0.5
Vctrl (V) Fig. 6.
Tuning Range.
changes. The tuning characteristic of the VCO is shown in Fig. 6, where it can be seen that the VCO achieves 18 % tuning range. The phase noise of the VCO at 2.33GHz is shown in Fig. 7, where it can be seen that the VCO achieves phase noise of -120dBc/Hz at 1-MHz offset while consuming 660 µA of current. The result of the VCO is summarized in Table I together with the recent state-of-the-art low-voltage VCOs. The layout of the VCO is shown in Fig. 8.
TABLE I C OMPARISON OF LOW- VOLTAGE VCO S . [4] 0.5 V 570 µA 3.8 GHz 3% -119 dBc/Hz -193 dB -182.5 dB
Supply Voltage Current Consumption Center Frequency Tuning Range Phase Noise (@ 1 MHz) FOM a FOMT b a FOM
[5] 1V 4.6 mA 2.42 GHz 1.7 % -134 dBc/Hz -195 dB -179.6 dB
This work 0.5 V 660 µA 2.56 GHz 18 % -120 dBc/Hz -192 dB -197.1 dB
ω 0 + 10 log PDC [5]. ∆ω 1mW FTR
= L{∆ω} − 20 log
b FOM = FOM − 20 log T in percent [9].
10
where the FTR is the frequency tuning range
0
Phase Noise (dBc/Hz)
-20 -40 -60 -80 -100 -120 -140 -160 1 kHz
10 kHz
100 kHz
1MHz
10MHz
Frequency Offset Fig. 7.
Phase Noise @ 2.33 GHz.
V. C ONCLUSIONS The proposed VCO achieves phase noise of -120 dBc/Hz at 1-MHz offset and 18 % tuning range while consuming 660 µA at 0.5-V supply. The low power is achieved by a novel LC optimization scheme and the wide tuning range is achieved by digital tuning with voltage boosting technique. VI. ACKNOWLEDGMENTS This work is supported by Samsung Electro-Mechanics CO., LTD. The authors would like to thank M. S. Kim, T. J. Park and H. S. Kim of Samsung Electro-Mechanics CO., LTD and Y. W. Ku of KAIST for his advice and support. The CAD tools have been supported by IC Design Center (IDEC) of KAIST. R EFERENCES [1] A. Wang and A. Chandrakasan, “A 180-mV subthreshold FFT processor using a minimum energy design methodology,” IEEE J. Solid-State Circuits, vol. 40, pp. 310–319, Jan. 2005. [2] G. C. T. Leung and H. C. Luong, “A 1-V 5.2-GHz CMOS synthesizer for WLAN applications,” IEEE J. Solid-State Circuits, vol. 40, pp. 1873– 1882, Nov. 2004. [3] S. Cho and A. P. Chandrakasan, “A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications,” IEEE J. Solid-State Circuits, vol. 39, pp. 731–739, May 2004.
Fig. 8.
Layout of the proposed VCO.
[4] K. Kwok and H. C. Luong, “Ultra-low-voltage high-performance CMOS VCOs using transformer feedback,” IEEE J. Solid-State Circuits, vol. 40, pp. 652–660, Mar. 2005. [5] Z. Li and K. K. O., “A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator,” IEEE J. Solid-State Circuits, vol. 40, pp. 1296–1302, June 2005. [6] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, vol. 33, pp. 179– 194, Feb. 1998. [7] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 36, pp. 896–909, June 2001. [8] A. D. Berny, A. M. Niknejad, and R. G. Meyer, “A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration,” IEEE J. Solid-State Circuits, vol. 40, pp. 909–917, Apr. 2005. [9] J. Kim, J. Plouchart, N. Zamdmer, M.Cherony, Y. Tan, M. Yoon, R. Trzcinski, M. Talbi, J. Safran, A. Ray, and L. Wagner, “A poweroptimized widely-tunable 5-GHZ monolithic VCO in a digital SOI CMOS technology on high resistivity substrate,” in Proc. ISLPED, 2003, pp. 434– 439.
