Quiz 2b (Winter 2012)
McGill University Department of Electrical and Computer Engineering Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Monday Student Name and ID:
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,2,5,6,7,8,9,13) + D(1,12,15) Exercise 2
a) Which gate is not a valid CMOS gate?
(5 points)
b) By observing the PUN and PDN of the invalid logic gate, independently, find the logic function at node Y corresponding to both PUN and PDN. (10 points) c) Regarding the invalid CMOS gate, find four input combinations, under which both PUN and PDN are turned off? (10 points) d) Does the invalid CMOS gate suffer from static power consumption? Explain why? (10 points) Exercise 3 A Berkeley student has designed a CMOS gate by mistake as follows:
a) Find an input combination, which results in a static power consumption problem. (5 points) b) For the above input combination, find the voltage at the node Y, when Vdd=1.8V, and all the NMOS (PMOS) transistors in their ON mode are modeled with a single resistor with the conductance of 2.5G (4G). This voltage at node Y approximately lies within what region (weak-high, weak-low, or the undefined region)? (15 points)
McGill University Department of Electrical and Computer Engineering
Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Monday Solutions
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,2,5,6,7,8,9,13) + D(1,12,15) (Answer) From the book, pages 215-217.
Exercise 2: a) (5 points) Gate#1 is invalid. In CMOS technology, whenever 2 transistors are in parallel in one network, their dual should be in serial in the other network. In gate 1, B and C are in parallel in both PUN and PDN. So, gate 1 is not a valid CMOS gate. b) (10 points) For Gate#1 PUN: A’B’D’+E’C’ PDN: (DE+C(A+B))’=(D’+E’)(C’+A’B’) =E’C’+D’C’+D’A’B’+E’A’B’ not equal to PUN c) (10 points) D=C=0, E=1, AB=01, 10, or 11. Another solution is when E=0, C=1, A=0, B=0, D=1 d) (10 points) No, since there does not exist an input combination under which both PDN and PUN are turned on.
Exercise 3:
a) (5 points) C=1, A=0, B=0 b) (15 points): Y=1.8*(2)/(2+2.5)=0.8V, which is in the undefined region (around VDD/2)
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,2,5,6,7,8,9,13) + D(1,12,15) Exercise 2
a) Which gate is not a valid CMOS gate?
(5 points)
b) By observing the PUN and PDN of the invalid logic gate, independently, find the logic function at node Y corresponding to both PUN and PDN. (10 points) c) Regarding the invalid CMOS gate, find four input combinations, under which both PUN and PDN are turned off? (10 points) d) Does the invalid CMOS gate suffer from static power consumption? Explain why? (10 points) Exercise 3 A Berkeley student has designed a CMOS gate by mistake as follows:
a) Find an input combination, which results in a static power consumption problem. (5 points) b) For the above input combination, find the voltage at the node Y, when Vdd=1.8V, and all the NMOS (PMOS) transistors in their ON mode are modeled with a single resistor with the conductance of 2.5G (4G). This voltage at node Y approximately lies within what region (weak-high, weak-low, or the undefined region)? (15 points)
McGill University Department of Electrical and Computer Engineering
Course: ECSE 323 -Digital Systems Design Winter 2012 Assignment #2 – Monday Solutions
TOPIC: Tabular Method & CMOS Logic Exercise 1
(45 points)
Use the tabular method of Quine-McCluskey to find a minimum cost SOP realization for the function f(x1, …, x4) = Σm(0,2,5,6,7,8,9,13) + D(1,12,15) (Answer) From the book, pages 215-217.
Exercise 2: a) (5 points) Gate#1 is invalid. In CMOS technology, whenever 2 transistors are in parallel in one network, their dual should be in serial in the other network. In gate 1, B and C are in parallel in both PUN and PDN. So, gate 1 is not a valid CMOS gate. b) (10 points) For Gate#1 PUN: A’B’D’+E’C’ PDN: (DE+C(A+B))’=(D’+E’)(C’+A’B’) =E’C’+D’C’+D’A’B’+E’A’B’ not equal to PUN c) (10 points) D=C=0, E=1, AB=01, 10, or 11. Another solution is when E=0, C=1, A=0, B=0, D=1 d) (10 points) No, since there does not exist an input combination under which both PDN and PUN are turned on.
Exercise 3:
a) (5 points) C=1, A=0, B=0 b) (15 points): Y=1.8*(2)/(2+2.5)=0.8V, which is in the undefined region (around VDD/2)
