Quiz 7b (Winter 2012)
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2012
ASSIGNMENT #7B Monday
TOPIC: Sequential logic - Registers - Counters Student Name & ID: Exercise 1
40 points
Using only two number of 3-bit Binary up-counters with synchronous active-high reset and enable inputs (when enable=0 the counter holds its previous value), and minimum number of logic gates, design a dual-mode modulo counter with synchronous reset and enable, which operates as a modulo-35 counter (counts from 0 to 34) when the control input M is equal to 0, and as a modulo-45 counter (counts from 0 to 44) when M=1. Exercise 2: We would like to design a circuit to measure the speed of a car. The circuit consists of a sonar sensor, which sends sonar signals to the target vehicle, and after hitting the car, the signal will return to the device. An officer has to point the device (sensor) directly to the car and hit a reset signal and hold the device in its position, until the sonar signal returns from its round trip and is received by the sensor (it will take just a fraction of a second). Note that the direction of the moving vehicle is directly toward the officer, e.g., in a highway. The sensor on this device follows two phases when the reset signal is hit by the officer (see the figure): Phase 1: After hitting the reset, the sensor sends the first sonar signal and waits, until it is returned. Then it asserts ACK#1 (acknowledge for Phase 1) signal for only one clock cycle (the rest of the time we have ACK#1=0) to indicate that it has received the transmitted signal. Phase 2: Right after the sensor receives the returned transmitted signal, it sends another sonar signal and waits until it is returned again. Then, it asserts ACK#2 (acknowledge for Phase 2) signal for only one clock cycle. The timing of these operations is shown in the figure.
a) Using an n-bit Binary up-counter with active-high synchronous reset and enable inputs, 2n number of D flip-flops with synchronous active-high reset and enable inputs (assume “n” to be a parameter), and an arithmetic unit, which includes one adder, one subtractor, one multiplier, and one divider (you could make use of all the arithmetic elements in parallel), design a circuit, which gives the speed of the car (for simplicity assume that the speed of sound is 300m/s, and also the clock frequency of the digital circuit and counter is f=50MHz). (40 points) b) If we aim to only target cars that are within the distance range of 0 to 600m from the officer, and the frequency of clock that we use for the digital circuit and counter is f=50MHz, what is the lowest possible number of bits that we should choose for the counter, i.e., minimum value of “n”, such that the counter does not face an overflow, while counting. (20 points)
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2012
ASSIGNMENT #7B Monday
TOPIC: Sequential logic - Registers – Counters Exercise 1 Solution:
40 points
Exercise 2:
60 points
Solution: a) We use the counter to count the amount of time it takes for the two sonar signals in Phase 1 and Phase 2 to reach the car and return back to the device. The counter’s reset signal must be connected to the signal “reset=(rst OR ACK#1)”, where “rst” is the input reset signal, that is asserted by the officer. Also when ACK#1 is asserted, the counter must be reset to start counting for Phase 2. The two registers are used to store the value of the counter at the end of the two phases when ACK#1 (ACK#2) is asserted. Hence, the reset signal of both registers is connected to “rst”, and the “enable” signal of Register#1 (#2) is connected to ACK#1 (#2). After Phase 2 finishes we have the value t1 (representing the amount of time for the first round trip in Phase 1) stored in Register#1, and also the value of t2, which represents the amount of time required for the second round trip in Phase 2, stored in Register#2. Now we have: ½ * t1*(1/50MHz)=d1/(300m/s), where “d1” is the distance between the car and the officer, when the first sonar signal reaches the car, Also, ½ * t2*(1/50MHz)=d2/(300m/s), where “d2” is the distance between the car and the officer, when the second sonar signal reaches the car. Note that the division by 2 is according to the fact that t1 and t2 store the round trip times. Now we know that the speed of the car is equal to: V=(50MHz) * (2) * (d1-d2)/(t1+t2)=(300m/s) * (t1-t2)/(t1+t2) Hence, using one adder, one subtractor, one multiplier, and one divider we could obtain V from t1, t2. b) The sound travels the maximum distance, i.e., 600m, in 600/300=2 seconds. Hence, the maximum value of t1 or t2 in terms of seconds (not clock cycles), according to the round trip would be equal to 2*2=4 seconds. Now that we are using a clock with the frequency of 50MHz for the counter, the highest number of clock cycles would be equal to: Cycles = (50MHz) * (4) = 2 * 108 Hence, we need to have at least 28 bits for the counter to cover 228> 2 * 108 cycles.
Winter 2012
ASSIGNMENT #7B Monday
TOPIC: Sequential logic - Registers - Counters Student Name & ID: Exercise 1
40 points
Using only two number of 3-bit Binary up-counters with synchronous active-high reset and enable inputs (when enable=0 the counter holds its previous value), and minimum number of logic gates, design a dual-mode modulo counter with synchronous reset and enable, which operates as a modulo-35 counter (counts from 0 to 34) when the control input M is equal to 0, and as a modulo-45 counter (counts from 0 to 44) when M=1. Exercise 2: We would like to design a circuit to measure the speed of a car. The circuit consists of a sonar sensor, which sends sonar signals to the target vehicle, and after hitting the car, the signal will return to the device. An officer has to point the device (sensor) directly to the car and hit a reset signal and hold the device in its position, until the sonar signal returns from its round trip and is received by the sensor (it will take just a fraction of a second). Note that the direction of the moving vehicle is directly toward the officer, e.g., in a highway. The sensor on this device follows two phases when the reset signal is hit by the officer (see the figure): Phase 1: After hitting the reset, the sensor sends the first sonar signal and waits, until it is returned. Then it asserts ACK#1 (acknowledge for Phase 1) signal for only one clock cycle (the rest of the time we have ACK#1=0) to indicate that it has received the transmitted signal. Phase 2: Right after the sensor receives the returned transmitted signal, it sends another sonar signal and waits until it is returned again. Then, it asserts ACK#2 (acknowledge for Phase 2) signal for only one clock cycle. The timing of these operations is shown in the figure.
a) Using an n-bit Binary up-counter with active-high synchronous reset and enable inputs, 2n number of D flip-flops with synchronous active-high reset and enable inputs (assume “n” to be a parameter), and an arithmetic unit, which includes one adder, one subtractor, one multiplier, and one divider (you could make use of all the arithmetic elements in parallel), design a circuit, which gives the speed of the car (for simplicity assume that the speed of sound is 300m/s, and also the clock frequency of the digital circuit and counter is f=50MHz). (40 points) b) If we aim to only target cars that are within the distance range of 0 to 600m from the officer, and the frequency of clock that we use for the digital circuit and counter is f=50MHz, what is the lowest possible number of bits that we should choose for the counter, i.e., minimum value of “n”, such that the counter does not face an overflow, while counting. (20 points)
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2012
ASSIGNMENT #7B Monday
TOPIC: Sequential logic - Registers – Counters Exercise 1 Solution:
40 points
Exercise 2:
60 points
Solution: a) We use the counter to count the amount of time it takes for the two sonar signals in Phase 1 and Phase 2 to reach the car and return back to the device. The counter’s reset signal must be connected to the signal “reset=(rst OR ACK#1)”, where “rst” is the input reset signal, that is asserted by the officer. Also when ACK#1 is asserted, the counter must be reset to start counting for Phase 2. The two registers are used to store the value of the counter at the end of the two phases when ACK#1 (ACK#2) is asserted. Hence, the reset signal of both registers is connected to “rst”, and the “enable” signal of Register#1 (#2) is connected to ACK#1 (#2). After Phase 2 finishes we have the value t1 (representing the amount of time for the first round trip in Phase 1) stored in Register#1, and also the value of t2, which represents the amount of time required for the second round trip in Phase 2, stored in Register#2. Now we have: ½ * t1*(1/50MHz)=d1/(300m/s), where “d1” is the distance between the car and the officer, when the first sonar signal reaches the car, Also, ½ * t2*(1/50MHz)=d2/(300m/s), where “d2” is the distance between the car and the officer, when the second sonar signal reaches the car. Note that the division by 2 is according to the fact that t1 and t2 store the round trip times. Now we know that the speed of the car is equal to: V=(50MHz) * (2) * (d1-d2)/(t1+t2)=(300m/s) * (t1-t2)/(t1+t2) Hence, using one adder, one subtractor, one multiplier, and one divider we could obtain V from t1, t2. b) The sound travels the maximum distance, i.e., 600m, in 600/300=2 seconds. Hence, the maximum value of t1 or t2 in terms of seconds (not clock cycles), according to the round trip would be equal to 2*2=4 seconds. Now that we are using a clock with the frequency of 50MHz for the counter, the highest number of clock cycles would be equal to: Cycles = (50MHz) * (4) = 2 * 108 Hence, we need to have at least 28 bits for the counter to cover 228> 2 * 108 cycles.
