Resonant DC-DC Flyback Converter
PEDS2009
Design and Implementation of Interleaved QuasiResonant DC-DC Flyback Converter Zi-Shiuan Ling
Tsorng-Juu Liang
Lung-Sheng Yang
Tzuu-Hseng Li
Department of Electrical Engineering, National Cheng-Kung University Tainan, Taiwan, R. O. C. E-mail address: [email protected] Abstract—This paper presents the interleaved quasi-resonant (QR) DC-DC flyback converter, which uses two parallelconnection DC-DC flyback converters. The interleaved technique is used to control the active switches of the two flyback converters. Also, the active switches are turned on at voltagevalley condition to reduce switching losses. Thus, this converter can achieve large output power, low output-current ripple, and high efficiency. The operating principle is discussed. Finally, a prototype circuit with input voltage 300 – 400 V, output voltage 24 V, and output current 8.33 A is implemented to verify the performance.
Vin
is1
Lm1 n:1
QR-I
iso Co
Vo
PWM controller NCP1377
Lk2
ip2
S1
VDS1
VGS1
Ds2
T2
is2
Lm2
QR-II
n:1 Cr2
INTRODUCTION
S2
Interleaved control circuit
The DC power supplies are widely used for many applications. The traditional linear power supplies have the advantages, such as simple structure, high stability, and low output voltage ripple. However, these linear power supplies have the disadvantages, such as large volume and low efficiency. In order to improve the disadvantages, the switching power supplies are developed to provide high power density and efficiency [1, 2]. Many converters, such as buck type, boost type, buck-boost type, forward type, and flyback type, are applied for the switching power supplies. Based on simple structure and lower cost, the flyback converter is often adopted. However, due to the effect of the leakage inductor in the flyback converter, this converter is used for low-power applications. This paper presents interleaved quasi-resonant (QR) flyback converters, which includes two paralleledconnection flyback converters, QR-I and QR-II, as shown in Fig. 1. Thus, the proposed converter can provide large output power. Moreover, the QR technique is used to reduce the switching losses [3-7]. The interleaved technique is utilized to reduce the output-current ripple [8-12].
VGS2
VDS2
Figure. 1 Circuit configuration of interleaved QR DC-DC flyback converter. T D1T
D2T
D3T
VGS1 D1T
VGS2
D2T
D3T
t
t
VDS1
t
iLm1
t
ip1
t
is1 t
VDS2
t
iLm2
t
ip2
II.
R
Cr1
Keywords - interleaved; quasi-resonant; valley switching; flyback converter)
I.
Lk1
ip1
Ds1
T1
OPERATIONAL PRINCIPLE OF PROPOSED CONVERTER
t
is2
The proposed converter is operated in discontinuous conduction mode (DCM). The typical waveforms are shown in Fig. 2. The operating principle is described as follows:
t
iso
t t0
t1 t2 t3
t4 t t t7 5 6
Figure 2. Typical waveforms of the proposed converter.
429
PEDS2009 Mode I [t0, t1]: During this time interval, S1/Ds2 are turned on and S2/Ds1 are turned off. The equivalent circuit is shown in Fig. 3(a). The magnetizing inductor Lm1 is charged from the DC source, so iLm1 is increased linearly. The energy stored in the magnetizing inductor Lm2 is released to the output capacitor Co and the load. Thus, iLm2 is decreased linearly and equals zero at t = t1. ip1 = iLm1
(1)
is 2 = niLm 2
(2)
iLm1 (t ) =
Vin (t − t0 ) Lm
iLm2 (t ) = −
nVo (t − t1 ) Lm
Mode VI [t5, t6]: During this time interval, S1/S2 are turned off and Ds1/Ds2 are turned on. The equivalent circuit is shown in Fig. 3(f). The energies stored in Lm1 and Lm2 are released to Co and the load, so iLm1 and iLm2 are decreased linearly.
iLm 2 (t ) = −
1 2π LmCr 2
(3) (4)
f r1 =
ip1
Vin (t − t3 ) Lm
nV iLm1 (t ) = − o (t − t4 ) Lm
T1
Vin
Ds1 is1
n:1
iso Co
R Vo
iso Co
R
Cr1
(5)
S1
ip2
Lk2
VDS1 T2
Lm2
Ds2 is2
n:1 Cr2 S2
(7)
VDS2
(a) Mode I
Lk1
Mode IV [t3, t4]: During this time interval, S1/Ds2 are turned off and S2/Ds1 are turned on. The equivalent circuit is shown in Fig. 3(d). The energy stored in Lm1 is released to Co and the load via transformer T1, so iLm1 is decreased linearly. Lm2 is still charged by DC source, so iLm2 is increased linearly. is1 = niLm1
(12)
Lm1
(6)
ip 2 = iLm2
(11)
1 2π LmCr1 Lk1
Mode III [t2, t3]: During this time interval, S1/Ds1/Ds2 are turned off and S2 is turned on. The equivalent circuit is shown in Fig. 3(c). Cr1 is charged from the energy stored in Lm1 until VDS1 = Vin + nVo. Lm2 is charged by DC source, so iLm2 is increased. The energy stored in Co is released to the load.
iLm2 (t ) =
nVo (t − t6 ) Lm
Mode VII [t6, t7]: During this time interval, S1/S2/Ds1 are turned off and Ds2 is turned on. The equivalent circuit is shown in Fig. 3(g). Due to iLm1 = 0 and VDS1 = Vin + nVo at t = t6, Lm1 is charged reversely from Cr1. At t = t7, VDS1 is decreased to the valley. In this moment, S1 is turned on. Also, the energy stored in Lm2 is released to Co and the load via T2.
Mode II [t1, t2]: During this time interval, S1 is turned on and S2/Ds1/Ds2 are turned off. The equivalent circuit is shown in Fig. 3(b). Lm1 is still charged from the DC source, so iLm1 is still increased linearly. Owing to iLm2 = 0 and VDS2 = Vin + nVo at t = t1, Lm2 is charged reversely from Cr2. At t = t2, VDS2 is decreased to the valley. In this moment, S2 is turned on. fr 2 =
(10)
is 2 = niLm 2
ip1
T1 Lm1
Vin
Ds1 is1
n:1 Cr1
S1
(8)
Lk2
(9)
ip2
VDS1 T2
Lm2
Ds2 is2
n:1
Mode V [t4, t5]: During this time interval, S1/S2/Ds2 are turned off and Ds1 is turned on. The equivalent circuit is shown in Fig. 3(e). The energy stored in Lm1 is still released to Co and the load via T1, so iLm1 is decreased linearly. Cr2 is charged from the energy stored in Lm2 until VDS2 = Vin + nVo.
Cr2 S2
(b) Mode II
430
VDS2
Vo
PEDS2009 Lk1 ip1
Lm1
Vin
Lk1
Ds1
T1
is1
n:1
iso Co
ip1
R
Vo
T1 Lm1
S1
VDS1 Lk2
Ds2
T2
ip2
is2
Lm2
Lm2
Lm1
Lk1
Ds1 is1
n:1
Vin
Lk2
iso Co
ip1
R
Vo
Lm1
ip2
Lm2
S1 Lk2
Ds2 ip2
is2
T2 Lm2
S2
Lm1
is1
iso Co
III. R
Vo
Lk2 ip2
VDS1 T2
Lm2
Ds2 is2
n:1 Cr2 S2
EXPERIMENTAL RESULTS
To verify the performance of the proposed converter, a laboratory prototype circuit is implemented. The circuit specifications and parameters are selected as Vin = 300 – 400 V, Vo = 24 V, Po = 200W, fs(min) = 50 kHz, Dmax = 0.42, Lm1 = Lm1 = 1.4 mH, Co = 470 μF, and Cr = 560 pF. Figs. 4 – 7 show some experimental waveforms under various input voltage and output current. From Figs. 4(a) – 7(a), one can see that the gate driver signals VGS1 and VGS2 are interleaved and S2 is turned on after S1 is turned off. Moreover, switches S1 and S2 are turned on at the voltage-valley. Due to the interleaved control, the frequency of iso is twice of the frequencies of is1 and is2, as shown in Figs. 4(b) – 7(b). Figs. 8 and 9 shows the output voltage under various input voltage and output current. One can see that the output voltage is almost constant. The measured efficiency under various input voltage and output power is shown in Fig. 6. The maximum efficiency is 86.6 % at the full load.
Cr1 S1
VDS2
Figure 3. Equivalent circuits of proposed converter.
Ds1
n:1
Vin
is2
(g) Mode VII
(d) Mode IV
ip1
Ds2
Cr2
VDS2
T1
VDS1
n:1
Cr2
Lk1
is1
Cr1
n:1
S2
Vo
Ds1
n:1
Vin
VDS1 T2
R
VDS2
T1
Cr1 S1
iso Co
is2
(f) Mode VI
(c) Mode III
ip1
Ds2
Cr2 S2
VDS2
T1
Vo
n:1
Cr2
Lk1
R
VDS1 T2
n:1
S2
iso Co
Cr1
S1
ip2
is1
n:1
Vin
Cr1
Lk2
Ds1
VDS2
(e) Mode V
431
PEDS2009
VGS1
VGS1
VGS2
VGS2
VDS1
VDS1
VDS2
VDS2
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 2 μ s/div
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 2 μ s/div
(a)
(a)
VGS1
VGS1
is1
is1 is2
is2
iso
iso VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
VGS1 : 20 V/div, is1/ is2/ iso : 5 A/div, Time : 2 μ s/div
(b) Figure 6. Experimental waveforms under Vin = 400 V, Vo = 24 V, Io = 1.8 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
(b) Figure 4. Experimental waveforms under Vin = 300 V, Vo = 24 V, Io = 1.8 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
VGS1
VGS1
VGS2
VGS2
VDS1
VDS1
VDS2
VDS2
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 5 μ s/div
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 5 μ s/div
(a)
(a)
VGS1
VGS1
is1
is1
is2
is2
iso
iso
VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
(b) Figure 7. Experimental waveforms under Vin = 400 V, Vo = 24 V, Io = 8.33 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso
(b) Figure 5. Experimental waveforms under Vin = 300 V, Vo = 24 V, Io = 8.33 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
432
PEDS2009 Vo (V) 25
can see that the maximum efficiency is 86.55 ％ and the variation of output voltage is within 1.67％.
24
ACKNOWLEDGMENT
23
The authors gratefully acknowledge financial support from the Research Center of Ocean Environment and Technology of National Cheng Kung University.
22 21 350 V
300 V 20
1
2
3
REFERENCES
400 V 6
5
4
7
8
9
Io (A)
[1]
N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics, John Wiley & Sons, Inc., 2003. [2] R. C. Dugan, M. F. McGranaghan, and H. W. Beaty, Electrical Power Systems Quality, McGraw-Hill, Inc., 1996. [3] H. Noji, T. Kawahara, R. Sato, and H. Tohya, “Analysis and design of current-resonant converter,” in Proc. IEEE PESC, pp.1244-1251, 1988. [4] R. B. Ridley, A. Lotfi, V. Vorperian, and F. C. Lee, “Design and control of a full-wave, quasi-resonant flyback converter,” in Proc. IEEE APEC, pp.41-49, 1988. [5] M. M. Jovanovic, F. C. Y. Lee, and D. Y. Chen, “A zero-currentswitched off-line quasi-resonant converter with reduced frequency range: analysis, design, and experimental results,” IEEE Trans. on Power Electronics, vol. 4, no. 2, pp 205-214, Apr. 1989. [6] V. Vorperian, R. Tymerski, and F. C. Y. Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE Trans. on Power Electronics, vol. 4, no. 2, pp.217-225, Mar. 2005. [7] W. A. Tabisz and F. C. Lee, “Zero-voltage-switching multiresonant technique-a novel approach to improve performance of high-frequency quasi-resonant converters,” IEEE Trans. on Power Electronics, vol. 4, no. 4, pp. 450-458, Oct. 1989. [8] C. Chang and M. A. Knights, “Interleaving technique in distributed power conversion systems,” IEEE Trans. on Circuit and Systems, vol. 42, no. 5, May 1995. [9] D. S. Lo and C. P. Henze, “Development of a DC-to-DC power converter,” in Proc. IEEE APEC, pp. 413-422, 1989. [10] G. C. Hua, W. A. Tabisz, C. S. Leu, N. Dai, R. Watson, and F. C. Lee, “Development of a DC distributed power system,” in Proc. IEEE APEC, vol. 2, pp. 763-769, 1994. [11] C. Chang, “Current ripple bounds in interleaved DC-DC power converters,” in Proc. Int. Conf. on Power Electronics and Drive Systems, vol. 2, pp. 738-743, 1995. [12] D. J. Perreault and J. G. Kassakian, “Distributed interleaving of paralleled power converters,” IEEE Trans. on Circuit and Systems, vol. 44, no. 8, pp. 728-734, Aug. 1997.
Figure 8. Output voltage under different input voltage and output current. Efficiency (%) 90
80
70 300 V 60 30
50
70
350 V
90
110
400 V
130
150
170
190
Po (W) 210
Figure 9. Measured efficiency under different input voltage and output power.
IV.
CONCLUSIONS
This paper presents the interleaved quasi-resonant DC-DC flyback converter. The power switches of this converter are turned on at the voltage-valley by using the quasi-resonant operating under various input voltage and output current. Also, the proposed converter uses two parallel-connection DC-DC flyback converters to increase the output power and uses the interleaved technique to reduce the output-current ripple. Finally, a prototype circuit with input voltage 300 – 400 V, output voltage 24 V, and output current 8.33 A is implemented to verify the performance. From the experimental results, one
433
Design and Implementation of Interleaved QuasiResonant DC-DC Flyback Converter Zi-Shiuan Ling
Tsorng-Juu Liang
Lung-Sheng Yang
Tzuu-Hseng Li
Department of Electrical Engineering, National Cheng-Kung University Tainan, Taiwan, R. O. C. E-mail address: [email protected] Abstract—This paper presents the interleaved quasi-resonant (QR) DC-DC flyback converter, which uses two parallelconnection DC-DC flyback converters. The interleaved technique is used to control the active switches of the two flyback converters. Also, the active switches are turned on at voltagevalley condition to reduce switching losses. Thus, this converter can achieve large output power, low output-current ripple, and high efficiency. The operating principle is discussed. Finally, a prototype circuit with input voltage 300 – 400 V, output voltage 24 V, and output current 8.33 A is implemented to verify the performance.
Vin
is1
Lm1 n:1
QR-I
iso Co
Vo
PWM controller NCP1377
Lk2
ip2
S1
VDS1
VGS1
Ds2
T2
is2
Lm2
QR-II
n:1 Cr2
INTRODUCTION
S2
Interleaved control circuit
The DC power supplies are widely used for many applications. The traditional linear power supplies have the advantages, such as simple structure, high stability, and low output voltage ripple. However, these linear power supplies have the disadvantages, such as large volume and low efficiency. In order to improve the disadvantages, the switching power supplies are developed to provide high power density and efficiency [1, 2]. Many converters, such as buck type, boost type, buck-boost type, forward type, and flyback type, are applied for the switching power supplies. Based on simple structure and lower cost, the flyback converter is often adopted. However, due to the effect of the leakage inductor in the flyback converter, this converter is used for low-power applications. This paper presents interleaved quasi-resonant (QR) flyback converters, which includes two paralleledconnection flyback converters, QR-I and QR-II, as shown in Fig. 1. Thus, the proposed converter can provide large output power. Moreover, the QR technique is used to reduce the switching losses [3-7]. The interleaved technique is utilized to reduce the output-current ripple [8-12].
VGS2
VDS2
Figure. 1 Circuit configuration of interleaved QR DC-DC flyback converter. T D1T
D2T
D3T
VGS1 D1T
VGS2
D2T
D3T
t
t
VDS1
t
iLm1
t
ip1
t
is1 t
VDS2
t
iLm2
t
ip2
II.
R
Cr1
Keywords - interleaved; quasi-resonant; valley switching; flyback converter)
I.
Lk1
ip1
Ds1
T1
OPERATIONAL PRINCIPLE OF PROPOSED CONVERTER
t
is2
The proposed converter is operated in discontinuous conduction mode (DCM). The typical waveforms are shown in Fig. 2. The operating principle is described as follows:
t
iso
t t0
t1 t2 t3
t4 t t t7 5 6
Figure 2. Typical waveforms of the proposed converter.
429
PEDS2009 Mode I [t0, t1]: During this time interval, S1/Ds2 are turned on and S2/Ds1 are turned off. The equivalent circuit is shown in Fig. 3(a). The magnetizing inductor Lm1 is charged from the DC source, so iLm1 is increased linearly. The energy stored in the magnetizing inductor Lm2 is released to the output capacitor Co and the load. Thus, iLm2 is decreased linearly and equals zero at t = t1. ip1 = iLm1
(1)
is 2 = niLm 2
(2)
iLm1 (t ) =
Vin (t − t0 ) Lm
iLm2 (t ) = −
nVo (t − t1 ) Lm
Mode VI [t5, t6]: During this time interval, S1/S2 are turned off and Ds1/Ds2 are turned on. The equivalent circuit is shown in Fig. 3(f). The energies stored in Lm1 and Lm2 are released to Co and the load, so iLm1 and iLm2 are decreased linearly.
iLm 2 (t ) = −
1 2π LmCr 2
(3) (4)
f r1 =
ip1
Vin (t − t3 ) Lm
nV iLm1 (t ) = − o (t − t4 ) Lm
T1
Vin
Ds1 is1
n:1
iso Co
R Vo
iso Co
R
Cr1
(5)
S1
ip2
Lk2
VDS1 T2
Lm2
Ds2 is2
n:1 Cr2 S2
(7)
VDS2
(a) Mode I
Lk1
Mode IV [t3, t4]: During this time interval, S1/Ds2 are turned off and S2/Ds1 are turned on. The equivalent circuit is shown in Fig. 3(d). The energy stored in Lm1 is released to Co and the load via transformer T1, so iLm1 is decreased linearly. Lm2 is still charged by DC source, so iLm2 is increased linearly. is1 = niLm1
(12)
Lm1
(6)
ip 2 = iLm2
(11)
1 2π LmCr1 Lk1
Mode III [t2, t3]: During this time interval, S1/Ds1/Ds2 are turned off and S2 is turned on. The equivalent circuit is shown in Fig. 3(c). Cr1 is charged from the energy stored in Lm1 until VDS1 = Vin + nVo. Lm2 is charged by DC source, so iLm2 is increased. The energy stored in Co is released to the load.
iLm2 (t ) =
nVo (t − t6 ) Lm
Mode VII [t6, t7]: During this time interval, S1/S2/Ds1 are turned off and Ds2 is turned on. The equivalent circuit is shown in Fig. 3(g). Due to iLm1 = 0 and VDS1 = Vin + nVo at t = t6, Lm1 is charged reversely from Cr1. At t = t7, VDS1 is decreased to the valley. In this moment, S1 is turned on. Also, the energy stored in Lm2 is released to Co and the load via T2.
Mode II [t1, t2]: During this time interval, S1 is turned on and S2/Ds1/Ds2 are turned off. The equivalent circuit is shown in Fig. 3(b). Lm1 is still charged from the DC source, so iLm1 is still increased linearly. Owing to iLm2 = 0 and VDS2 = Vin + nVo at t = t1, Lm2 is charged reversely from Cr2. At t = t2, VDS2 is decreased to the valley. In this moment, S2 is turned on. fr 2 =
(10)
is 2 = niLm 2
ip1
T1 Lm1
Vin
Ds1 is1
n:1 Cr1
S1
(8)
Lk2
(9)
ip2
VDS1 T2
Lm2
Ds2 is2
n:1
Mode V [t4, t5]: During this time interval, S1/S2/Ds2 are turned off and Ds1 is turned on. The equivalent circuit is shown in Fig. 3(e). The energy stored in Lm1 is still released to Co and the load via T1, so iLm1 is decreased linearly. Cr2 is charged from the energy stored in Lm2 until VDS2 = Vin + nVo.
Cr2 S2
(b) Mode II
430
VDS2
Vo
PEDS2009 Lk1 ip1
Lm1
Vin
Lk1
Ds1
T1
is1
n:1
iso Co
ip1
R
Vo
T1 Lm1
S1
VDS1 Lk2
Ds2
T2
ip2
is2
Lm2
Lm2
Lm1
Lk1
Ds1 is1
n:1
Vin
Lk2
iso Co
ip1
R
Vo
Lm1
ip2
Lm2
S1 Lk2
Ds2 ip2
is2
T2 Lm2
S2
Lm1
is1
iso Co
III. R
Vo
Lk2 ip2
VDS1 T2
Lm2
Ds2 is2
n:1 Cr2 S2
EXPERIMENTAL RESULTS
To verify the performance of the proposed converter, a laboratory prototype circuit is implemented. The circuit specifications and parameters are selected as Vin = 300 – 400 V, Vo = 24 V, Po = 200W, fs(min) = 50 kHz, Dmax = 0.42, Lm1 = Lm1 = 1.4 mH, Co = 470 μF, and Cr = 560 pF. Figs. 4 – 7 show some experimental waveforms under various input voltage and output current. From Figs. 4(a) – 7(a), one can see that the gate driver signals VGS1 and VGS2 are interleaved and S2 is turned on after S1 is turned off. Moreover, switches S1 and S2 are turned on at the voltage-valley. Due to the interleaved control, the frequency of iso is twice of the frequencies of is1 and is2, as shown in Figs. 4(b) – 7(b). Figs. 8 and 9 shows the output voltage under various input voltage and output current. One can see that the output voltage is almost constant. The measured efficiency under various input voltage and output power is shown in Fig. 6. The maximum efficiency is 86.6 % at the full load.
Cr1 S1
VDS2
Figure 3. Equivalent circuits of proposed converter.
Ds1
n:1
Vin
is2
(g) Mode VII
(d) Mode IV
ip1
Ds2
Cr2
VDS2
T1
VDS1
n:1
Cr2
Lk1
is1
Cr1
n:1
S2
Vo
Ds1
n:1
Vin
VDS1 T2
R
VDS2
T1
Cr1 S1
iso Co
is2
(f) Mode VI
(c) Mode III
ip1
Ds2
Cr2 S2
VDS2
T1
Vo
n:1
Cr2
Lk1
R
VDS1 T2
n:1
S2
iso Co
Cr1
S1
ip2
is1
n:1
Vin
Cr1
Lk2
Ds1
VDS2
(e) Mode V
431
PEDS2009
VGS1
VGS1
VGS2
VGS2
VDS1
VDS1
VDS2
VDS2
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 2 μ s/div
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 2 μ s/div
(a)
(a)
VGS1
VGS1
is1
is1 is2
is2
iso
iso VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
VGS1 : 20 V/div, is1/ is2/ iso : 5 A/div, Time : 2 μ s/div
(b) Figure 6. Experimental waveforms under Vin = 400 V, Vo = 24 V, Io = 1.8 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
(b) Figure 4. Experimental waveforms under Vin = 300 V, Vo = 24 V, Io = 1.8 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
VGS1
VGS1
VGS2
VGS2
VDS1
VDS1
VDS2
VDS2
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 5 μ s/div
VGS1/VGS2 : 20 V/div, VDS1/VDS2 : 400 V/div, Time : 5 μ s/div
(a)
(a)
VGS1
VGS1
is1
is1
is2
is2
iso
iso
VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
VGS1 : 20 V/div, is1/ is2/ iso : 20 A/div, Time : 5 μ s/div
(b) Figure 7. Experimental waveforms under Vin = 400 V, Vo = 24 V, Io = 8.33 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso
(b) Figure 5. Experimental waveforms under Vin = 300 V, Vo = 24 V, Io = 8.33 A. (a) VGS1, VGS2, VDS1, and VDS2 (b) VGS1, is1, is2, and iso.
432
PEDS2009 Vo (V) 25
can see that the maximum efficiency is 86.55 ％ and the variation of output voltage is within 1.67％.
24
ACKNOWLEDGMENT
23
The authors gratefully acknowledge financial support from the Research Center of Ocean Environment and Technology of National Cheng Kung University.
22 21 350 V
300 V 20
1
2
3
REFERENCES
400 V 6
5
4
7
8
9
Io (A)
[1]
N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics, John Wiley & Sons, Inc., 2003. [2] R. C. Dugan, M. F. McGranaghan, and H. W. Beaty, Electrical Power Systems Quality, McGraw-Hill, Inc., 1996. [3] H. Noji, T. Kawahara, R. Sato, and H. Tohya, “Analysis and design of current-resonant converter,” in Proc. IEEE PESC, pp.1244-1251, 1988. [4] R. B. Ridley, A. Lotfi, V. Vorperian, and F. C. Lee, “Design and control of a full-wave, quasi-resonant flyback converter,” in Proc. IEEE APEC, pp.41-49, 1988. [5] M. M. Jovanovic, F. C. Y. Lee, and D. Y. Chen, “A zero-currentswitched off-line quasi-resonant converter with reduced frequency range: analysis, design, and experimental results,” IEEE Trans. on Power Electronics, vol. 4, no. 2, pp 205-214, Apr. 1989. [6] V. Vorperian, R. Tymerski, and F. C. Y. Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE Trans. on Power Electronics, vol. 4, no. 2, pp.217-225, Mar. 2005. [7] W. A. Tabisz and F. C. Lee, “Zero-voltage-switching multiresonant technique-a novel approach to improve performance of high-frequency quasi-resonant converters,” IEEE Trans. on Power Electronics, vol. 4, no. 4, pp. 450-458, Oct. 1989. [8] C. Chang and M. A. Knights, “Interleaving technique in distributed power conversion systems,” IEEE Trans. on Circuit and Systems, vol. 42, no. 5, May 1995. [9] D. S. Lo and C. P. Henze, “Development of a DC-to-DC power converter,” in Proc. IEEE APEC, pp. 413-422, 1989. [10] G. C. Hua, W. A. Tabisz, C. S. Leu, N. Dai, R. Watson, and F. C. Lee, “Development of a DC distributed power system,” in Proc. IEEE APEC, vol. 2, pp. 763-769, 1994. [11] C. Chang, “Current ripple bounds in interleaved DC-DC power converters,” in Proc. Int. Conf. on Power Electronics and Drive Systems, vol. 2, pp. 738-743, 1995. [12] D. J. Perreault and J. G. Kassakian, “Distributed interleaving of paralleled power converters,” IEEE Trans. on Circuit and Systems, vol. 44, no. 8, pp. 728-734, Aug. 1997.
Figure 8. Output voltage under different input voltage and output current. Efficiency (%) 90
80
70 300 V 60 30
50
70
350 V
90
110
400 V
130
150
170
190
Po (W) 210
Figure 9. Measured efficiency under different input voltage and output power.
IV.
CONCLUSIONS
This paper presents the interleaved quasi-resonant DC-DC flyback converter. The power switches of this converter are turned on at the voltage-valley by using the quasi-resonant operating under various input voltage and output current. Also, the proposed converter uses two parallel-connection DC-DC flyback converters to increase the output power and uses the interleaved technique to reduce the output-current ripple. Finally, a prototype circuit with input voltage 300 – 400 V, output voltage 24 V, and output current 8.33 A is implemented to verify the performance. From the experimental results, one
433
