TOPIC: Finite State Machines
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2011
ASSIGNMENT #8A Wednesday March. 16, 2011
TOPIC: Finite State Machines Exercise 1 : Sequence detector We want to design a sequential machine (FSM) that asserts its output Z when it recognizes the following input bit sequence : “..1001..”. The FSM will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the sequence. As an example the input sequence X= "..1001001..." will cause the output to go high twice: Z = "..0001001.." . 1/ Draw the state diagram of this FSM using the Moore’s approach. 2/ Draw the state diagram of this FSM using the Mealy’s approach.
Solution exercise 1: 1/ Moore’s machine:
2/ Mealy’s machine:
Exercise 2: Let’s consider the following state diagram of a Mealy’s machine.
Use the following labeling for variables: X : input, 2 bits : X1, X0 Z : output, 1 bit: Z Y : next state, 2 bits: Y1, Y0 y : present state, 2 bits: y1, y0 1/ Write the VHDL code that implements the FSM. 2a/ Assuming the following state mapping: A=00, B=01, C=10, derive Boolean equations of Y1, Y0 and Z. 2b/ Deduce the corresponding digital circuit implementation. Solution exercise 2
1/ VHDL source code: library IEEE; use IEEE.STD_LOGIC_1164.all; entity FSM is Port ( rst, clk : in STD_LOGIC; X : STD_LOGIC_VECTOR(1 downto 0); Z : out STD_LOGIC);
end FSM; architecture Mealy of FSM is type state_type is (A, B, C); signal state, next_state : state_type; signal Z_tmp : std_logic; begin SYNC_PROC: process (rst, clk) begin if (rst = '1') then state
Winter 2011
ASSIGNMENT #8A Wednesday March. 16, 2011
TOPIC: Finite State Machines Exercise 1 : Sequence detector We want to design a sequential machine (FSM) that asserts its output Z when it recognizes the following input bit sequence : “..1001..”. The FSM will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the sequence. As an example the input sequence X= "..1001001..." will cause the output to go high twice: Z = "..0001001.." . 1/ Draw the state diagram of this FSM using the Moore’s approach. 2/ Draw the state diagram of this FSM using the Mealy’s approach.
Solution exercise 1: 1/ Moore’s machine:
2/ Mealy’s machine:
Exercise 2: Let’s consider the following state diagram of a Mealy’s machine.
Use the following labeling for variables: X : input, 2 bits : X1, X0 Z : output, 1 bit: Z Y : next state, 2 bits: Y1, Y0 y : present state, 2 bits: y1, y0 1/ Write the VHDL code that implements the FSM. 2a/ Assuming the following state mapping: A=00, B=01, C=10, derive Boolean equations of Y1, Y0 and Z. 2b/ Deduce the corresponding digital circuit implementation. Solution exercise 2
1/ VHDL source code: library IEEE; use IEEE.STD_LOGIC_1164.all; entity FSM is Port ( rst, clk : in STD_LOGIC; X : STD_LOGIC_VECTOR(1 downto 0); Z : out STD_LOGIC);
end FSM; architecture Mealy of FSM is type state_type is (A, B, C); signal state, next_state : state_type; signal Z_tmp : std_logic; begin SYNC_PROC: process (rst, clk) begin if (rst = '1') then state
