TOPIC: Finite State Machines
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2012
ASSIGNMENT #8A Friday
TOPIC: Finite State Machines Exercise 1 : Sequence detector We would like to design a sequential machine (FSM) that asserts its output bit Z to “1” when it recognizes the following input bit sequence : “..1001..” occurring at the input bit W over different clock cycles. The FSM will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the sequence. As an example the input sequence W= "..1001001..." will cause the output to go high twice: Z = "..0001001.." . 1/ Draw the state diagram of this FSM using the Moore’s approach. (15 points) 2/ Draw the state diagram of this FSM using the Mealy’s approach. (15 points) 3/ If we would like to detect an “n” bit sequence in general, what is the minimum sufficient number of flip-flops that we require to realize the FSM using Moore and Mealy methods? (10 points) 4/ Under what conditions both Mealy and Moore models require the same number of flip-flops? (5 points) 5/ Under what conditions Mealy and Moore models require different number of flipflops? (5 points) 6/ Looking into the Mealy model in part 2, and by performing a state mapping from 000…0 to 111…1, derive the minimum cost SOP Boolean equations for the next states and the output Z, and then draw the corresponding circuit using D flip-flops. (25 points)
Solution exercise 1: 1/ Moore’s machine:
2/ Mealy’s machine:
3/ We need Moore model.
flip-flops for the Mealy model, and
flip-flops for the
4/ When
, then we have
.
5/ When , then we have , while . Hence, under such conditions, the Mealy model requires flip-flops, while the Moore model needs flip-flops. 6/ The Mealy’s machine requires 4 states, i.e., 2 flip-flops. Let us say that the present states are y1, y0, and the next states are Y1, Y0. The state mapping is as follows: A=00 (y1=0, y0=0), B=01 (y1=0, y0=1), C=10 (y1=1, y0=0), D=11 (y1=1, y0=1). Hence, after using Karnaugh maps and minimizations, here is what we get for the Boolean equations in the SOP form: Z=Wy1y0, Y1=y1’W’y0+W’y1y0’, Y0=W+y1y0’ The values Y1 and Y0 are going to be the input D ports of the two flip-flops, while y1, y0 are the outputs of the D flip-flops. Exercise 2: (25 points) We would like to design the FSM of a simple traffic light using Moore’s model. We are targeting a one-way street for cars, and a cross path for pedestrians. There is a light for the cars, which can either be red, yellow or green. There is also a push-button available for the pedestrians “request”, when they want to cross the street. Furthermore, there is a sensor that tracks the number of cars passing by, indicating whether the traffic is high or low. So, we have an input signal “traffic”, which is generated by the sensor (traffic=0/1 means that traffic is low/high). We have the following states for the FSM: State A = “Green_no_pedestrian”, where cars are passing by and there is no pedestrian waiting State B = “Green_pedestrian_waiting”, where the light is green and cars are passing by, but there is a pedestrian waiting State C = “Yellow” State D = “Red” The FSM has to work according to the following rules: 1- By default we are in State A, when the push-button is not hit. 2- When we are in State A, if the push-button “request” is asserted by the pedestrian and the traffic is low (traffic=0), we should go to the Yellow state. 3- The FSM stays in the Yellow state for 10 clock cycles, and then goes to the Red state. 4- The FSM stays in the Red state for 90 clock cycles and then goes to State A. 5- When we are in State A, if the push-button “request” is asserted by the pedestrian and the traffic is high (traffic=1), we should go to State B.
6- When we are in State B, if anytime, the traffic goes low (traffic=0), we should go to the Yellow state. Otherwise, if the traffic remains high, the FSM stays in State B for 100 clock cycles and then goes to the Yellow state. Using only one 7-bit binary up-counter with synchronous “reset” and “enable” input signals (to count the #of clock cycles within the states B, C, D), describe the FSM for the above traffic light using Moore’s approach and the 4 given states A, B, C, D.
Note that when “main_reset=1” we go to State A, and the counter is reset as well. Solution exercise 2: “Reset” and “enable” of the counter: Reset = (main_reset) OR (Count==99) OR (state==B AND traffic==0) Enable = (state==B) OR (state==C) OR (state==D) FSM:
Winter 2012
ASSIGNMENT #8A Friday
TOPIC: Finite State Machines Exercise 1 : Sequence detector We would like to design a sequential machine (FSM) that asserts its output bit Z to “1” when it recognizes the following input bit sequence : “..1001..” occurring at the input bit W over different clock cycles. The FSM will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the sequence. As an example the input sequence W= "..1001001..." will cause the output to go high twice: Z = "..0001001.." . 1/ Draw the state diagram of this FSM using the Moore’s approach. (15 points) 2/ Draw the state diagram of this FSM using the Mealy’s approach. (15 points) 3/ If we would like to detect an “n” bit sequence in general, what is the minimum sufficient number of flip-flops that we require to realize the FSM using Moore and Mealy methods? (10 points) 4/ Under what conditions both Mealy and Moore models require the same number of flip-flops? (5 points) 5/ Under what conditions Mealy and Moore models require different number of flipflops? (5 points) 6/ Looking into the Mealy model in part 2, and by performing a state mapping from 000…0 to 111…1, derive the minimum cost SOP Boolean equations for the next states and the output Z, and then draw the corresponding circuit using D flip-flops. (25 points)
Solution exercise 1: 1/ Moore’s machine:
2/ Mealy’s machine:
3/ We need Moore model.
flip-flops for the Mealy model, and
flip-flops for the
4/ When
, then we have
.
5/ When , then we have , while . Hence, under such conditions, the Mealy model requires flip-flops, while the Moore model needs flip-flops. 6/ The Mealy’s machine requires 4 states, i.e., 2 flip-flops. Let us say that the present states are y1, y0, and the next states are Y1, Y0. The state mapping is as follows: A=00 (y1=0, y0=0), B=01 (y1=0, y0=1), C=10 (y1=1, y0=0), D=11 (y1=1, y0=1). Hence, after using Karnaugh maps and minimizations, here is what we get for the Boolean equations in the SOP form: Z=Wy1y0, Y1=y1’W’y0+W’y1y0’, Y0=W+y1y0’ The values Y1 and Y0 are going to be the input D ports of the two flip-flops, while y1, y0 are the outputs of the D flip-flops. Exercise 2: (25 points) We would like to design the FSM of a simple traffic light using Moore’s model. We are targeting a one-way street for cars, and a cross path for pedestrians. There is a light for the cars, which can either be red, yellow or green. There is also a push-button available for the pedestrians “request”, when they want to cross the street. Furthermore, there is a sensor that tracks the number of cars passing by, indicating whether the traffic is high or low. So, we have an input signal “traffic”, which is generated by the sensor (traffic=0/1 means that traffic is low/high). We have the following states for the FSM: State A = “Green_no_pedestrian”, where cars are passing by and there is no pedestrian waiting State B = “Green_pedestrian_waiting”, where the light is green and cars are passing by, but there is a pedestrian waiting State C = “Yellow” State D = “Red” The FSM has to work according to the following rules: 1- By default we are in State A, when the push-button is not hit. 2- When we are in State A, if the push-button “request” is asserted by the pedestrian and the traffic is low (traffic=0), we should go to the Yellow state. 3- The FSM stays in the Yellow state for 10 clock cycles, and then goes to the Red state. 4- The FSM stays in the Red state for 90 clock cycles and then goes to State A. 5- When we are in State A, if the push-button “request” is asserted by the pedestrian and the traffic is high (traffic=1), we should go to State B.
6- When we are in State B, if anytime, the traffic goes low (traffic=0), we should go to the Yellow state. Otherwise, if the traffic remains high, the FSM stays in State B for 100 clock cycles and then goes to the Yellow state. Using only one 7-bit binary up-counter with synchronous “reset” and “enable” input signals (to count the #of clock cycles within the states B, C, D), describe the FSM for the above traffic light using Moore’s approach and the 4 given states A, B, C, D.
Note that when “main_reset=1” we go to State A, and the counter is reset as well. Solution exercise 2: “Reset” and “enable” of the counter: Reset = (main_reset) OR (Count==99) OR (state==B AND traffic==0) Enable = (state==B) OR (state==C) OR (state==D) FSM:
