TOPIC: VHDL and Synthesis of Sequential Systems
McGill University Department of Electrical and Computer Engineering Course: ECSE 323-Digital Systems Design
Winter 2012
ASSIGNMENT #9A Friday
TOPIC: VHDL and Synthesis of Sequential Systems Question 1 20 points Write a complete VHDL code (except for describing the libraries) that represents a J-K flip-flop with asynchronous active-high reset and synchronous enable inputs and the complementary outputs Q and Q’ (when reset=1, the output Q is set to zero, and when enable=0, the flip-flop holds its previous value). Solution 1 LIBRARY ieee; -- the library and entity are optional USE ieee.std_logic_1164.all; ENTITY prob1 IS PORT (J, K, Resetn, Enable, Clock : IN STD_LOGIC; Q,Qb : OUT STD_LOGIC ); END prob1; ARCHITECTURE Behavior OF prob1 IS -–this part of the code is mandatory SIGNAL Qint : STD_LOGIC; BEGIN PROCESS (Clock, Resetn) BEGIN IF Resetn = ’1’ THEN Qint
Winter 2012
ASSIGNMENT #9A Friday
TOPIC: VHDL and Synthesis of Sequential Systems Question 1 20 points Write a complete VHDL code (except for describing the libraries) that represents a J-K flip-flop with asynchronous active-high reset and synchronous enable inputs and the complementary outputs Q and Q’ (when reset=1, the output Q is set to zero, and when enable=0, the flip-flop holds its previous value). Solution 1 LIBRARY ieee; -- the library and entity are optional USE ieee.std_logic_1164.all; ENTITY prob1 IS PORT (J, K, Resetn, Enable, Clock : IN STD_LOGIC; Q,Qb : OUT STD_LOGIC ); END prob1; ARCHITECTURE Behavior OF prob1 IS -–this part of the code is mandatory SIGNAL Qint : STD_LOGIC; BEGIN PROCESS (Clock, Resetn) BEGIN IF Resetn = ’1’ THEN Qint
