TOPIC: VHDL and Combinational Logic

McGill University Department of Electrical and Computer Engineering Winter 2012

Course: ECSE 323-Digital Systems Design

Assignment#4 - Monday

Student Name and ID:

TOPIC: VHDL and Combinational Logic Exercise 1 (70 points) a) Design a combinational circuit that computes , where X is an unsigned 4-bit value, and S is an unsigned 2-bit value using minimum number of 4x1 multiplexers. You are only allowed to use 4x1 multiplexers Solution: X=x3,x2,x1,x0, and S=s1,s0. The output has 7 bits Y=y6, y5, y4, y3, y2, y1, y0. Each output requires a 4x1 multiplexer with the select signals being s1, s0. The inputs to the multiplexers are as follows for each output: y6 = y5 = y4 = y3 = y2 = y1 = y0 =

s1s0=00 0 0 0 x3 x2 x1 x0

s1s0=01 0 0 x3 x2 x1 x0 0

s1s0=10 0 x3 x2 x1 x0 0 0

s1s0=11 x3 x2 x1 x0 0 0 0

b) Write a VHDL code describing this circuit using a PROCESS block. Your code must be translated into 4x1 multiplexers from the hardware point of view. Solution: LIBRARY IEEE; Use ieee.std_logic_1164.all; entity circuit1 is port(X: in std_logic_vector(3 downto 0); S: in std_logic_vector(1 downto 0); Y: out std_logic_vector(6 downto 0));

end circuit1;

architecture logicfunct of circuit1 is begin L1: process (X,S) begin L2: case S is when “00” ==> Y Y Y Y