UNIVERSITY OF CALIFORNIA Los Angeles CMOS LC Oscillators for ...

UNIVERSITY OF CALIFORNIA Los Angeles

CMOS LC Oscillators for Low-Power MEMS Applications

A thesis submitted in partial satisfaction of the requirements for the degree Master of Science in Electrical Engineering

by

Ping-Hsuan Hsieh

2004

The thesis of Ping-Hsuan Hsieh is approved.

________________________________ Behzad Razavi

________________________________ Mau-Chung Frank Chang

________________________________ Chih-Kong Ken Yang, Committee Chair

University of California, Los Angeles

2004

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ABSTRACT OF THE THESIS

CMOS LC Oscillators for Low-Power MEMS Applications

by Ping-Hsuan Hsieh

Master of Science in Electrical Engineering University of California, Los Angeles, 2004 Professor C.-K. Ken Yang, Chair

This work presents a complete clock generator for low-power MEMS capacitivesensing circuits including quadrature-coupled LC oscillators and a digital clock generator. Basic operating principles of LC oscillators are provided. A novel technique of switching the capacitive sensor and the capacitor array between the two quadrature-coupled oscillators is introduced to balance the effective capacitive load seen by the four quadrature phases. By identifying different sources of loss in the system, the overall power consumption can be minimized with an optimum switch size. Simulation result shows 6-time improvement in power consumption over the design based on ring oscillators.

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Table of Contents CMOS LC OSCILLATORS FOR LOW-POWER MEMS APPLICATIONS........... 1 CHAPTER 1 INTRODUCTION ..................................................................................... 1 CHAPTER 2 DESIGN OF LC OSCILLATORS........................................................... 7 2.1 PRACTICAL MODEL OF LC OSCILLATORS .................................................................. 8 2.2 QUADRATURE-COUPLED LC OSCILLATORS ............................................................. 11 2.2.1 The Principle of Quadrature-Coupled LC Oscillators .................................... 12 2.2.2 Switching the Load Capacitor between the Quadrature Phases ..................... 13 2.3 SUMMARY ................................................................................................................ 16 CHAPTER 3 POWER CONSUMPTION .................................................................... 18 3.1 OPTIMAL SWITCH SIZE ............................................................................................. 19 3.1.1 Effective Parallel Resistance ........................................................................... 19 3.1.2 Optimization of the Switch Size........................................................................ 21 3.2 ERROR IN SWITCHING TIMING .................................................................................. 23 3.3 SUMMARY ................................................................................................................ 26 CHAPTER 4 CIRCUIT PERFORMANCE ................................................................. 27 4.1 QUADRATURE-COUPLED LC OSCILLATOR ............................................................... 27 4.2 CLOCK GENERATOR ................................................................................................. 29 4.3 THE OVERALL PERFORMANCE .................................................................................. 32 4.4 COMPARISON OF SINUSOIDAL WAVE AND SQUARE WAVE....................................... 36 CHAPTER 5 CONCLUSION........................................................................................ 38 APPENDIX A CMOS LC OSCILLATOR WITH VARIABLE MEAN FREQUENCY ................................................................................................................. 40 A.1 BASIC PRINCIPLE..................................................................................................... 40 A.2 ARCHITECTURE ....................................................................................................... 41 A.3 TONES DUE TO AVERAGING..................................................................................... 43 A.3.1 Frequency Modulation .................................................................................... 43 A.3.2 Amplitude Modulation ..................................................................................... 45 A.3.3 Overall Effect due to Modulation .................................................................... 48 A.4 SWITCHING TIMING ................................................................................................. 49 A.5 EXPERIMENTAL RESULTS ........................................................................................ 50 A.6 CONCLUSION ........................................................................................................... 55 REFERENCES................................................................................................................ 56

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List of Figures Figure 1 Magnetic Field Sensor.......................................................................................... 1 Figure 2 Configurations of the analog signal processing.................................................... 2 Figure 3 The Architecture of the Capacitive Sensor and the following circuits................. 3 Figure 4 operation of an LC oscillator................................................................................ 7 Figure 5 General Circuit Diagram of an LC Oscillator ...................................................... 9 Figure 6. Schematic of an LC Oscillator .......................................................................... 11 Figure 7 General Model of Quadrature-Coupled LC Oscillators ..................................... 12 Figure 8 Switch the load capacitance between the four phases with time........................ 14 Figure 9 Dynamically Switching of the capacitive load between the two oscillators ...... 16 Figure 10 switches’ on-resistance in series with the capacitor array................................ 20 Figure 11 Capacitor Array ................................................................................................ 21 Figure 12 Trade-off in Power Consumption with rail-to-rail oscillation amplitude......... 23 Figure 13 Dynamically switching of the capacitive load between the two oscillators..... 24 Figure 14 Timing Error due to delay of the switching circuitry ....................................... 24 Figure 15 output oscillation waveforms of the quadrature-coupled LC oscillators.......... 28 Figure 16 output oscillation signals of the quadrature-coupled LC oscillators with 1% mismatch ................................................................................................................... 29 Figure 17 The block diagram of the clock generator........................................................ 30 Figure 18 Dynamically switching of the capacitive load between the two oscillators..... 31 Figure 19 Simulated output waveforms of the clock generator........................................ 32 Figure 20 Power trade-off between the oscillator and the multiplexer............................. 33 Figure 21 waveform of the differential oscillation signal................................................. 34 Figure 22 Summary of power consumption in each block ............................................... 36 Figure 23 Complete Architecture Block Diagram ............................................................ 42 Figure 24 The circuit topology changes when switches turn on/off................................. 43 Figure 25 Impedance of the LC tank when the switches are off and on........................... 44 Figure 26 Frequency Modulation...................................................................................... 44 Figure 27 Parasitic Resistance (a) when switches are OFF (b) When switches are ON .. 45 Figure 28 Different Switching Timing ............................................................................. 49 Figure 29 Die Photo of the oscillator................................................................................ 51 Figure 30 The change in average frequency according to different digital input pattern. 51 Figure 31 The DNL of the output average frequency....................................................... 52 Figure 32 Spectrum of the output oscillation signal and the closest tones ....................... 53 Figure 33 Phase Noise Performances ............................................................................... 53

List of Tables Table 1 characteristics of the external inductors and capacitors....................................... 28

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CMOS LC Oscillators for Low-Power MEMS Applications Chapter 1 Introduction Capacitive sensors have a wide variety of possible applications in Micro-ElectroMechanical Systems (MEMS) because the electronic-mechanical interface in such systems is commonly capacitive. In particular, there is a growing interest in low power sensors that require very small power supplies and can be placed on extremely portable devices. An example of their use is in unattended ground sensors (UGS), devices that “provide surveillance, intelligence, and monitoring of areas not suitable for continuous human presence” [1][2]. Design of extremely low-power sensing circuits is vital to achieve the aforementioned goals. Even though the bandwidth requirement for most sensors is low (several kHz), they often require high resolutions and need to operate continuously for long periods of time with small energy sources. There are various ways of organizing and designing these sensing circuits dependent on the application and desired output.

C1

C2 V+

Vmid

V-

Figure 1 Magnetic Field Sensor

1

The application of the sensing circuit under consideration is a magnetic field sensor. As shown in Figure 1, the change in the magnetic field causes a mechanical motion that is sensed through a change in position of a capacitive plate. When the capacitive plate tilts, one of the capacitance increases while the other one decreases. A common way of measuring the capacitance change is to apply a clock waveform at the two ends of the capacitive plates and convert the change in capacitance into an analog signal at the mid-point of the capacitive plate. The two capacitors at the two ends of the capacitive plates form a voltage divider. The amplitude of the signal at the mid-point of the capacitive plate indicates the magnitude of the magnetic field, since the larger the difference between the capacitance of the two capacitors, the larger signal we can get at the mid-point of the capacitive plate.

t

C1

Filter

Vmid C2

C1 Vmid C2

t

ωs

f

Digital Output

(a) Filter Preceding ADC

t

t

ωp

Nyquist Rate ADC

Oversample Rate ADC

Filter ωp

ωs

Digital Output

f

(a) Filter Following ADC Figure 2 Configurations of the analog signal processing

There are several configurations for the analog signal processing as shown in Figure 2. A previous work [3] filters the signal before the ADC (analog-to-digital 2

converter) to select the desirable signal allows the ADC to operate at the Nyquist rate. Chopper stabilization by mixing the analog signal with high clock frequency is used to eliminate flicker (1/f) noise from the circuitry and hence increases the dynamic range. The signal is then demodulated back to base band after amplification before being fed into the ADC. quadrature oscillator

V+

capacitor array

MUX

coupling

sensor

V-

14-bit

clock generator

comparator

Following Successive Approximation Algorithm

digital filter digital output

Figure 3 The Architecture of the Capacitive Sensor and the following circuits

A second type of signal processing first converts the analog signal into a digital value with over-sampling and then filters it in the digital domain. Figure 3 shows the overall architecture of the sensing circuits. The sensor signal is then compared with a reference generated by applying the same clock waveform on a capacitor array with 14bit resolution. The comparator’s output is processed according to a following successive-

3

approximation algorithm and is then fed back to adjust the capacitance of the capacitor array [4]. In conventional successive-approximation analog-to-digital converters, with a sample-and-hold front-end circuit, for the maximum input signal frequency of 1KHz, we need to run the system clock at 28KHz in order to get 14-bit outputs. However, with the sensor’s capacitance changing over time, the system clock has to run with an oversampling rate of 8192 in order to achieve the signal-to-noise ratio of 14 bits effectively. Simulation in Matlab has shown that, with the following successive-approximation algorithm, an over-sampling rate of only 1024 would be required, which is about 2MHz [4]. Our focus is on generating a 2-MHz clock waveform applied onto the sensor and the capacitor array. Notice that the larger the clock waveform, the larger the signal feeding into the comparator. This relaxes the comparator’s design and results in better signal-to-noise ratio. In addition to driving the capacitor sensor, the clock waveform also drives all clocking signal in the system such as the timing-control signal on the comparator. Quadrature phases are often needed for comparator’s operation. Therefore, the goal is to generate quadrature clock waveforms with rail-to-rail amplitude while achieving the minimum power consumption. Since the resolution and the linearity of the capacitor array directly impact the system’s performance, we would like to design a high-resolution capacitor array with large unit capacitance for matching purpose. If we estimate the power needed to drive

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the sensor and the capacitor array based on P ∝ CV 2 f , the power consumption would be considerable because of the large capacitance of the sensor and the capacitor array. There are several different ways of generating clock waveforms. By recycling the power driving the sensor and the capacitor array through an inductor, LC oscillators provide a promising method of generating energy-efficient clock waveforms with its energy-cycling characteristic. In Chapter 2, the basic operating principle and a practical model of LC oscillators are provided, from which power consumption can be estimated. We can generate clocks with quadrature-phase difference by coupling two LC oscillators [5], which retains the power efficiency. However, quadrature-coupled LC oscillators are sensitive to device mismatch as well as loading mismatch [6] especially when the sensor capacitance is dynamically changing. The design in this thesis uses a common strategy of coupling devices with programmable coupling strength.

This thesis also presents a novel

technique of switching the load capacitor between the four oscillators’ outputs in order to balance the capacitive load seen from each phase.

This switching maintains the

quadrature-phase relationship between the two oscillators. Since we intend to minimize the power consumed in the oscillator, different sources of non-idealities, which result in additional power consumption, are identified and minimized in Chapter 3.

Section 3.1 investigates the trade-off in the power

consumed in the oscillators and the drivers to the switches. The analysis leads to an optimum switches’ size.

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Ring oscillators have been recognized as good candidates of generating differential quadrature clocks, especially when the requirement of frequency purity is not stringent.

A comparison in power-consumption performance between the use of

quadrature-coupled LC oscillators and ring oscillators is provided in Chapter 4. Simulation results show that a 83% of power saving is achievable by using quadraturecoupled LC oscillators. Switching the load capacitor between the four quadrature phases causes varying operating frequency. In fact, the operating frequency of one oscillator is slower than the other one when the load capacitor is switched onto it. The time average of the operating frequencies cannot be determined simply by the main resonator but instead depends on the load capacitance and the switching activity. This phenomenon of instantaneous frequency changing motivates a design that tunes the oscillation frequency by dynamically switching in and out the load capacitor. Appendix A discusses a design of a dynamically switching oscillator with simulated and measured results.

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Chapter 2 Design of LC Oscillators For generating 2-MHz clock waveforms and providing system clocks with rail-torail amplitude and low power consumption, a good choice is LC oscillators. In an ideal LC oscillator, energy is stored in the form of magnetic field and electric field as shown in Figure 4. Energy is stored in the magnetic field when the current flowing in the LC tank is the maximum and there is no voltage across the tank. All energy is transferred and stored in the electric field when the voltage across the tank is the maximum. Energy transfers between magnetic field and electric field, oscillating without energy loss. Imax

Vmax

(a) Energy stored in magnetic field

(b) Energy stored in electrical field

Figure 4 operation of an LC oscillator

However, loss is introduced by the non-idealities of different components of the oscillator. A more practical model of the LC oscillator is provided in Section 2.1. We can estimate the power needed to sustain the oscillation by identifying different sources of loss and then calculating the effective parallel resistance across the LC tank. Besides the signal driving the capacitor sensor, the oscillator is responsible for all clocking signal in the system. A fully differential LC oscillator provides both true and

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complementary signals.

However, the timing-control signal of the comparator

necessitates generating clocks with quadrature phase difference. After reviewing different ways of generating quadrature clocks and discussing the design considerations, Section 2.2.1 discusses the operating principle of quadraturecoupled LC oscillators [5] [7]. These oscillators retain the benefit of energy recycling of LC oscillators and potentially consume less power. Important issues such as device and loading mismatches are discussed. As is introduced in Section 2.2.2, the problem of loading mismatch due to the change in the sensor capacitance over time can be solved by a novel technique of switching the load capacitors between the four quadrature outputs to balance the effective capacitive load.

2.1 Practical Model of LC Oscillators Figure 5 shows a general circuit model of an LC oscillator [8]. Besides the LC tank, which is essential for oscillation, the parasitic resistance from the non-idealities of the different components is also included. RC and RL are the series parasitic resistance associated with the inductor and the capacitor.

The output resistance of the

transconductance and the parallel parasitic resistance of the LC tank are combined into Rp. When oscillating, the parasitic resistance consumes energy that is stored in the LC tank. Therefore, in practice, an LC tank alone fails to oscillate. A transconductance GM connected in positive feedback, which effectively exhibits a negative resistance of –1/GM, is introduced to compensate for the losses causing by these non-idealities.

8

Vout

GM Rp

C

L

RC

RL

Figure 5 General Circuit Diagram of an LC Oscillator

One way to build the negative resistance is shown in Figure 6 [9]. The double cross-coupled connection of an NMOS (M1-M2) and a PMOS (M3-M4) differential pair provides a small-signal differential transconductance G M = ( g M , N + g M , P ) 2 across the LC tank, and according to Equation (2), this transconductance needs to be equal to or larger than 1/RP,eff in order to sustain oscillation. By using both NMOS and PMOS crosscoupled differential pairs, the amplification is doubled for the same supply current. We can calculate the transconductance GM needed given the effective parallel resistance as:

R P ,eff =

1 RC (ω 0 C ) + R L (ω 0 C ) 2 + 1

where ω 0 ≅ 1

2

LC

(1) RP

.

For sustaining the oscillation, the loop gain at the oscillation frequency, which is given as H open −loop (ω 0 ) = G M ⋅ R P ,eff , has to be equal to or larger than one. Therefore:

9

GM ≥ 1

RP ,eff

= RC (ω 0 C ) 2 + RL (ω 0 C ) 2 + 1

RP

.

(2)

When the oscillation amplitude is small, based on the Shockley model,

W W   G M = ( g M , N + g M , P ) / 2 =  µ N C ox ( ) N Voverdrive, N + µ P C ox ( ) P Voverdrive, P  2 , L L   => GM = I d ⋅ (

1 Voverdrive, N

+

1 Voverdrive, P

),

(3)

where Id is the bias current and is half of the tail current Itail. Based on Equation (2) and Equation (3),

Id ≥

Voverdrive, N ⋅ Voverdrive, P RP , eff (Voverdrive, N + Voverdrive, P )

.

This represents the minimum power necessary for maintaining the oscillation. When the small-signal loop gain is larger than one, oscillation starts with exponentially increasing amplitude until the circuit non-linearity forces the average loop gain be one. If the oscillation amplitude is large, the cross-coupled differential pairs simply steer the tail current in and out of the LC tank. If the oscillator is biased at low currents, the amplitude of the oscillation changes proportionally to the effective parallel resistance [10]: Vamp =

4 I tail RP ,eff

(4)

π

We can use Equation (4) to calculate the power needed for oscillation for given oscillation amplitude and effective parallel resistance.

10

M6

M5

M3

M4 C

Ibias

L

Vout+

Vout-

RP,eff

M1

M2

Figure 6. Schematic of an LC Oscillator

2.2 Quadrature-Coupled LC Oscillators There are several ways of generating clocks with quadrature phases. Delaying the clock signal by 90 degrees using simple delay lines is one way to generate the quadrature outputs, but this requires precise control on the delay-line delay with the presence of process and temperature variations. A feedback loop can be used but requires additional power consumption and increased circuit complexity. RC-CR network [11] and poly-phase filter [12] can also convert differential oscillation signals into quadrature outputs.

However, both device mismatch and

mismatch between the operating frequency and the RC time constant cause amplitude imbalance and departure from quadrature phase at outputs. This is particularly the case in our application where the operating frequency is changing with the change of the sensor capacitance. Buffers are needed to drive the RC-CR network or the poly-phase

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filter and to amplify the filter output. The buffers keep the filter from degrading the quality factor of the LC tank and compensate the 3dB loss of the filter. These buffers would incur additional power consumption. To maintain low power consumption, we couple two LC oscillators to generate quadrature clocks. Resonating one more LC tank consumes much less power than other buffer-type circuits.

2.2.1 The Principle of Quadrature-Coupled LC Oscillators A general circuit model of quadrature-coupled LC oscillators is shown in Figure 7 [7]. Two identical oscillators are coupled to each other by coupling devices GM,couple which can be implemented a single NMOS transistor. In order to meet the oscillation condition, the total phase around the loop must be 360 degrees. Therefore, the phase difference between the adjacent signals is 180/2=90 degrees.

-1

Vout,1

GM

Vout,2

GM,couple

GM

GM,couple

Figure 7 General Model of Quadrature-Coupled LC Oscillators

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However, the two oscillators are locked in quadrature phase only when their oscillation frequencies and amplitude are exactly the same. If there is mismatch in the oscillation amplitude, the phase difference between the two output signals deviates from 90 degrees [6]. If the capacitive loads seen by the two oscillators are different, the two oscillators may fail to lock and operate at different frequencies. Mismatch in device size due to process variations and unequal coupling from other signals either electrically or magnetically due to imperfect layout may also cause amplitude and frequency mismatch. Increasing the bias current and thus the strength of the coupling devices helps to improve the quadrature coupling but degrades the phase noise performance [6]. The stronger the coupling devices are, the more the coupled oscillators behave like a ring oscillator while the LC tank tries to maintain the frequency purity with the benefit of energy cycling. The relative sizing of the positive-feedback-connected transconductance GM and the coupling device GM,couple depends on the potential device mismatch and the requirement on the phase noise performance. The coupling strength can be digitally controllable as shown in Figure 7 to maintain quadrature outputs with minimal coupling and hence reduce phase noise and power consumption.

2.2.2 Switching the Load Capacitor between the Quadrature Phases As explained in the previous section, different capacitive load seen by the two coupled-LC oscillators causes different operating frequencies and may cause a failure to lock in quadrature phase. Interestingly in our system, the additional capacitive load coming from the capacitor array and the sensor is only seen by one of the two LC oscillators and hence causes an imbalance in capacitive loading. This imbalance cannot 13

be compensated by inserting a fixed capacitor onto the other oscillator since the capacitance of the sensor as well as the capacitor array is changing with time. A novel solution is to switch the capacitor array and the sensor capacitor between the four quadrature phases with time as shown in Figure 8. Therefore, the average load capacitance in time as seen by the four-phase signals is the same as long as the capacitive load from the capacitor array and the sensor changes slowly as compared to the oscillation frequency and load switching.

Notice that the instantaneous operating

frequency of one oscillator with the additional load capacitor is slower than the other one. Therefore, the total capacitance of the capacitor array and the sensor capacitor should be small ( ≅ 4.5% in this design) as compared to the main capacitance in the resonator. Otherwise, the difference of instantaneous operating frequencies of the two oscillators would be too large to maintain quadrature clocks. OSCI

OSCI

Negative Gm I1

Negative Gm

Coupling I2

Q1

Q2

Sensor Capacitor Load Capacitor Capacitor Array

Figure 8 Switch the load capacitance between the four phases with time

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The switching of the load capacitor should be timed such that the charge on the load capacitor does not degrade the oscillating signals. Ideally, the voltage across the load capacitor before disconnecting from the LC tank and after reconnecting to the tank should be the same. Any voltage difference between the load capacitor and the LC tank at the instant when the switches are being connected results in an energy loss. This is equivalent to a parallel resistance across the LC tank. Therefore, any timing error degrades the LC tank’s quality factor, Q, which in turn implies more power consumption. A more detailed analysis is given in Chapter 3. The timing of the signals controlling the switches needs to be synchronized with the oscillation signals. The ON duration of the switches depends on the instantaneous operating frequency, which is determined by the instantaneous load capacitance. Therefore, the control signal on the switches must be generated from the four I/Q signals themselves rather than external pulse-shaped voltage sources. The switching point can be at the zero-crossing points as shown in Figure 9. The switches’ controlling signals and the waveform across the capacitor that is used to sense the difference between the two sensor capacitors are also shown in Figure 9.

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I1

Q1

I2

Q2 Voltage across the capacitor

Figure 9 Dynamically Switching of the capacitive load between the two oscillators

Since the instantaneous operating frequency changes with the switching of the load capacitance (the sensor and the capacitor array), the technique applies to a different method of tuning frequency. The average frequency can be changed by dynamically switching in and out a load capacitor. This technique of tuning frequency by switching the load capacitor for an RF application is introduced and discussed in detail in Appendix A.

2.3 Summary This chapter provides a practical model of LC oscillators and discusses the principle of quadrature-coupled LC oscillators. By identifying each component’s nonidealities, the power consumption needed to sustain oscillation can be estimated and minimized. Quadrature-coupled LC oscillators generate quadrature oscillation signals

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while maintaining low-power consumption. However, quadrature-coupled LC oscillators are sensitive to device and load mismatches. A novel technique of switching the load capacitors between the two oscillators is introduced to balance the effective capacitive load seen by the four quadrature phases. The switching activity requires additional power consumption. Chapter 3 first investigates the trade-off of power consumptions in the LC oscillators and the power needed for switching. As discussed in Section 2.2.2, the switching timing needs to be synchronized with the oscillation signals. Delay in the circuits generating the switches’ controlling signals results in timing error. Section 3.2 provides analytical analysis of the timing error and the resulting additional power consumption. Section 3.2 also discusses the design considerations.

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Chapter 3 Power Consumption In design of sensing circuits in portable devices, low power consumption is usually a requirement. One of the goals in this research is to optimize the power consumptions of different blocks and minimize the overall power consumption. In this chapter, we identify the different sources of power consumption and discuss the according design consideration. As introduced in Section 2.1, the parasitic resistance from the non-idealities of different components in one LC oscillator directly determines the minimum power consumption for maintaining the oscillation. Using high-quality off-chip capacitors and inductors as the main resonator can substantially improve the power consumption performance. Although poor matching of external components entails stronger coupling strength to maintain quadrature clock outputs, carefully selected external components with digitally controllable coupling devices suffice. Moreover, the technique of switching the capacitor array and the sensor capacitor between the four quadrature phases introduces additional loss because of the switches’ on-resistance appearing as parasitic resistance in series with the load capacitor. Although increasing the switches’ physical size reduces the on-resistance, this increases the power needed for the drivers to turn on and off the switches. As Section 3.1 shows, the trade-off between the switches’ on-resistance and gate capacitance leads to an optimal choice of switch size from power consumption point of view. Section 3.2 discusses the timing of switching the load capacitor. Switching timing error is another source of additional

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power consumption. Any voltage difference between the load capacitor and the resonator at the instant when the switches are being turned on causes an energy loss and is equivalent to a parallel resistance across the resonator. This loss degrades the tank’s quality factor and increases the power consumption.

3.1 Optimal Switch Size 3.1.1 Effective Parallel Resistance To switch the load capacitor between the four quadrature clock phases, the switches alternatively load the two oscillators. The on-resistance of the switches is equivalent to parasitic resistance in series with the load capacitor as shown in Figure 10. With the existence of the on-resistance, it consumes additional power to maintain oscillation. To calculate the effective parallel resistance, for the resonator that consists of more than one capacitor, we need to generalize Equation (1) as the following.

R P ,eff =

1

∑R

C ,i

i

=

(ω 0 C i ) 2 + ∑ RL ,k ( k

1 2 1 ) + RP ω 0 Lk 1

∑R

C ,i

(ω 0 C i )

i

2

1 1 + RC ,main (ω 0 C main ) + R L ,main ( )2 + RP ω 0 Lmain

(5)

2

LoadCapacitor

= R P ,eff , LoadCapacitor // R P ,eff ,original where ω 0 = 1

∑ L ⋅ ∑C k

k

i

≅1

Lmain ⋅ C main .

i

Here, the effective parallel resistance can be considered as a parallel combination of the effective parallel resistance from the main LC tank and from the load capacitor.

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Negative Gm Cmain

coupling

RC

Negative Gm Cmain

RC

Lmain

RL

Main LC Tank Lmain

RL controlling signal

RON Driver

RON

Capacitor Array

Load Capacitor Sensor Capacitor

Figure 10 switches’ on-resistance in series with the capacitor array

Based on Equation (5), the effective parallel resistance differs for different capacitor-array architectures even with the same switch size, leading to different power consumption. Therefore, two 14-bit capacitor array architectures are considered here. As shown in Figure 11, “Architecture A” refers to a capacitor array with 5-bit binary weighted capacitor units, 3 bits of thermometer-encoded capacitor units, and 6 bits of larger thermometer-encoded capacitor units. “Architecture B” refers to a capacitor array with 6-bit binary weighted capacitor units and 8 bits of thermometer-encoded capacitor units. Therefore, there are 75 switches in architecture A and 261 switches in architecture B. For both architectures, the capacitor array exhibits the maximum loss when the equivalent capacitance seen from the oscillator is the maximum. The minimum equivalent parallel resistance of architecture A is: R P ,min = +

1 Ronω 0 [(1C 0 ) + (2C 0 ) + (4C 0 ) + (8C 0 ) 2 + (16C 0 ) 2 + 7(32C 0 ) 2 + 31(256C 0 ) 2 ] 2

2

2

2

1 Ronω 0 [32(256C 0 ) 2 ]

(6).

2

20

Here we estimate the unit capacitance, C0, to be roughly 3.88fF based on the capacitor array’s layout topology using TSMC 0.18-µm technology. osc

1C0

oscb

2C0

16C0

32C0

32C0 256C0

256C0

3-bit thermometer 6-bit thermometer

5-bit digital

Architecture A osc

1C0

2C0

oscb

4C0

32C0

64C0

6-bit digital

64C0

64C0

8-bit thermometer

Architecture B

Figure 11 Capacitor Array

3.1.2 Optimization of the Switch Size Based on Equation (4), Equation (5), and Equation (6), to reduce the power consumed in the oscillator, the parasitic resistance in series with any capacitor in the resonator, and thus the switches’ on-resistance, has to be small. For pass-transistor-type switches, we can estimate the on-resistance by the following equations based on the Shockley model,

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Ron =

1 . W W µ nCox ( ) n (Voverdrive, n ) + µ pCox ( ) p (Voverdrive, p ) L L

Therefore, for the switches’ on-resistance to be small, we need to increase the switches’ physical size. However, this increases gate capacitance of the switches and therefore increases the power consumed in the clock driving these switches based on the relationship that Pclocking ∝ C switchV 2 f .

Taking these two power consumptions into

account, we can optimize the switch size. As we can see from Figure 9, each oscillator sees the capacitive load only during one-third of the period. With the assumption that the cross-coupled differential pairs steer the tail current in and out of the LC tank and also knowing the equivalent parallel resistance from the capacitive load based on Equation (6), according to Equation (4), we can make an estimation of the additional power consumption needed for the two oscillators to have rail-to-rail oscillation amplitude when switching the capacitive load. As shown in Figure 12, the additional power consumption of the quadraturecoupled LC oscillators increases proportionally to the switch on-resistance while the driver’s power consumption is in reverse proportion to the switch on-resistance. By summing up the two power consumptions, we get the minimum power consumption of 6.38µW at Ron=800Ω in architecture A and 5.45µW at Ron=2.8KΩ in architecture B with the unit capacitance C0=3.88fF and the supply voltage of 1.8V. Notice that the curve is quite flat with larger switch on-resistance. With only a small power penalty we choose significantly smaller switch size. The smaller switches can reduce the charge injection due to the switching activities.

22

100

6.38-µW with switch resistance = 800-Ohms. 5.45-µW with switch resistance = 2.8K-Ohms.

Power (uW)

10

Architecture A with 75 switches Architecture B with 261 switches 1

Driver Power Additional Oscillator Power 0.1 0.0E+00

1.0E+03

2.0E+03

3.0E+03

4.0E+03

5.0E+03

6.0E+03

7.0E+03

Series Resistance (Ohm)

Figure 12 Trade-off in Power Consumption with rail-to-rail oscillation amplitude

3.2 Error in Switching Timing As explained in the previous chapter, the voltage across the load capacitor before disconnecting from the main LC tank and after reconnecting to the tank should be the same to avoid degrading the quality factor of the tank. Therefore the controlling signal on the switches has to be generated from the four quadrature signals themselves rather than external pulse-shaped voltage sources to minimize the attenuation and hence power consumption. The ideal curves of the switches’ controlling signals and the waveform across the capacitor used to sense the difference between the two sensor capacitors are shown in Figure 9 and are repeated here in Figure 13.

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I1

Q1

I2

Q2 Voltage across the capacitor

Figure 13 Dynamically switching of the capacitive load between the two oscillators

∆t1

∆t2

I1

Q1

Voltage across the capacitor

Time (ns)

Figure 14 Timing Error due to delay of the switching circuitry

24

However, there is a small deviation from the ideal point of switching to the clock edge due to the delay of the circuits generating the controlling signals as shown in Figure 14. Assume the timing error is ∆t1 when the switch turns on and is ∆t2 when the switch turns off. By estimating the voltage difference between the load capacitor and the LC tank to be:

∆V = V swing * 2π * f osc * (∆t1 + ∆t 2 ) , where Vswing * 2π * f osc is the slope around the zero-crossing points, we can calculate the energy loss due to the switching timing error as:

C V + C load (Vo + ∆V ) 2 1 1 1 2 C mainVo + C load (Vo + ∆V ) 2 − (C main + C load )( main o ) 2 2 2 C main + C load 1 C C ⇒ ∆E = ( main load )∆V 2 , 2 C main + C load ∆E =

where C load =

1 1 14 ⋅ ( ⋅ 2 ⋅ C 0 ) is the maximum capacitance of the 14-bit capacitor array, 2 2

and Cmain is the capacitance of the main LC tank. Since the switching timing error happens twice every three periods for each oscillator, we can calculate the equivalent parallel resistance by calculating the power consumption as: Vswing 2 ∆E * f osc = 3 2 Req ⇒ Req =

2

3 C main + C load 1 ( ) 3 2 2 C main C load f osc ⋅ [2π ⋅ (∆t1 + ∆t 2 )]

(7)

Notice that the equivalent parallel resistance does not depend on the oscillation amplitude. Smaller harmonic mean of Cmain and Cload helps to reduce this additional

25

power consumption. For the timing error, ∆t1 and ∆t2, to be small, the driver inside the clock generator needs to be carefully designed, which introduces another trade-off on power consumption.

3.3 Summary As the non-idealities in different components of one LC oscillator determines the minimum power for maintaining the oscillation, this chapter provides analytical method to decide the optimal switch size to minimize the additional power consumption due to the switching activity. The timing error between the switches’ controlling signals and the oscillation signals is also discussed. Analytical results are provided to estimate the additional power consumption due to this timing error.

26

Chapter 4 Circuit Performance 4.1 Quadrature-Coupled LC Oscillator The test chip is designed and simulated with 0.18-µm 1.8-V TSMC CMOS technology. The quadrature-coupled LC oscillators are designed to have the simulated oscillation amplitude of 1.4V. Rail-to-rail oscillation amplitude can be achieved by increasing the bias current. In order to have rail-to-rail output oscillation amplitude, the LC oscillators have to operate in voltage-limited regime [13], where the oscillation amplitude has small relationship with the bias current and the power consumption. In other words, any change in the overall effective parallel resistance due to the switching of the load capacitance must only have a small effect on the oscillation amplitude. However, when operating in the voltage-limited regime, power is wasted with little oscillation amplitude increases. Therefore, we would like to design the oscillators with the tail current driving the maximum possible oscillation amplitude. The lease phase noise performance is another advantage of operating at the border of the current-limited regime and the voltage-limited regime [13]. Table 1 shows the characteristics of the external inductors and capacitors. The total quality factor of the LC tank at 2MHz is expected to be more than 1650.

external components

inductor (Lmain)

capacitor (Cmain)

inductance/capacitance

15µH

352pF

ω0 = 1

Lmain ⋅ C main

13.762Mrad/s ≅ 2.19MHz

27

parasitics

Rs,max=0.02Ω

Gp,max=2.217µΩ-1

Qmin @ 2M-Hz

9425

2000

combined Qmin @ 2M-Hz

1650

Rp,min @ 2M-Hz

373KΩ

Table 1 characteristics of the external inductors and capacitors

The coupling devices are designed to have 2 bits of adjustability. Figure 15 shows the output oscillation waveforms with matched devices and Figure 16 shows the waveforms with 1% of mismatch in the two main capacitors. With all the coupling devices turned on, which flows the same current as the main –Gm circuits, the phase difference between the two oscillators is 101.89 degrees.

However, the oscillation

amplitudes of the two oscillators are different, which will cause degradation of the overall system. Therefore, off-chip tunable capacitors with high quality factor are used to reduce the mismatch.

Figure 15 output oscillation waveforms of the quadrature-coupled LC oscillators

28

Figure 16 output oscillation signals of the quadrature-coupled LC oscillators with 1% mismatch

4.2 Clock Generator As described in Section 2.2.2, there is additional loss if the switches’ controlling signals and the oscillation signals are not properly synchronized.

Therefore, the

controlling signal must be generated from the four I/Q signals themselves rather than external pulse-shaped voltage sources. Figure 17 shows the block diagram of the clock generator. Without using variable delay lines as the design in Appendix A, the devices are sized to minimize the propagation delay through the clock generator and thus minimize the timing error between the switches’ controlling signals and the oscillation signals’ zero-crossing points.

29

CONQ1

CONI1

CONI2

CONQ2 start

Q1

I1

I2

Q2 reset

I2 LATCH

Q CONI2

Qb CONQ1 From the previous stage

Q

To the next stage

DFF Qb

reset path

Figure 17 The block diagram of the clock generator

The mechanism of generating the controlling signals is similar a token passed through the four I/Q signals. When the token is passed to signal I1, I1 can be digitized to generate CONI1 and turn on the switch connecting I1 and the load capacitor. After the switch turns off, I1 passes the token to Q1 and resets CON1 at the same time. The bottom plot in Figure 17 is a single block diagram of each stage in the clock generator. A toggled D-flip-flop is to close the path from input to output after passing the token to the next stage. A reset signal forces all control signals be low for startup so that no switches is on, then a positive pulse in the start signal gives the token. Notice that, the direction of passing the token is important. For the token to be passed correctly, I1 must lead Q1 by 270 degrees as shown in Figure 18. A wrong direction, namely passing the token from I1 to Q2 which have 90-degree phase difference,

30

can result in all controlling signals being high and the two oscillators cease to oscillate. Multiplexers are placed in front of each stage, assuring the direction is correct. Either I1 leads Q1 by 270 degrees or Q1 leads I1 by 270 degrees is equal likely to happen and cannot be predicted during the simulation stages. However, it is fixed due to the devices and the environment mismatch between the two oscillators after fabrication. o

270 I1

direction of passing the token

Q1 I2 Q2 Voltage across the capacitor

Figure 18 Dynamically switching of the capacitive load between the two oscillators

Figure 19 shows the simulated output waveforms of the clock generator. The simulation results show that the timing error between the switches’ controlling signals and the oscillation signals are ∆t1 = 2.3624 ns and ∆t 2 = 2.86761ns . According to Equation (7), the equivalent parallel resistance caused by this timing error is 11.42MΩ, which can be ignored when compared to the main LC tank loss.

31

Figure 19 Simulated output waveforms of the clock generator

4.3 The overall performance Both of the capacitance and the additional loss coming from the capacitor array are the maximum when Cup and Cdown are in the balanced situation. Figure 19 shows the output oscillation waveforms when the quadrature-coupled LC oscillators are mostly disturbed under this circumstance. With different switches’ sizes, Figure 20 shows the simulation results of the power consumption in the quadrature-coupled LC oscillators and the multiplexer that controls the switches according to the controlling signals generated from the clock

32

generator in order to have the same oscillation amplitude as without switching. The additional power consumption of the quadrature-coupled LC oscillators increases proportionally to the switch on-resistance while the driver’s power consumption is in reverse proportion to the switch on-resistance. The simulation results show the existence of an optimum switches’ size. 67µW@RS=1.25KOhms

66.5µW @ RS=2.1KOhms

8.00E+01

7.00E+01

Oscillator Power + MUX Power

6.00E+01

Oscillator Power + Multiplexer Power

5.00E+01

Multiplexer Power 4.00E+01 3.00E+01

2.00E+01

Oscillator Power

1.00E+01 0.000E+00 5.000E+02 1.000E+03 1.500E+03 2.000E+03 2.500E+03 3.000E+03 3.500E+03

Series Resistance

Figure 20 Power trade-off between the oscillator and the multiplexer

The switches are implemented with both NMOS/PMOS sizes of 1.4µm/0.18µm. The simulated switch’s on-resistance is 1.25KΩ.

The simulation result shows that,

1.544µW of additional power in each LC oscillator is required. This is 24% less than the calculated value of 2.026µW based on Equation (4) and Equation (6). The sum of the LC oscillators’ power consumption and the multiplexer’s power consumption is just 0.5µW

33

more than the minimum power consumption obtained if the switches are implemented to have 2.1Kohms series resistance. Figure 21 shows a closer view of the differential oscillation signals’ amplitude.

Figure 21 waveform of the differential oscillation signal

The step-like waveforms result from the amplitude modulation as a side effect of the switching activities. As explained in Appendix A, a main reason of the amplitude modulation is the difference in the oscillation amplitude when the switches are on and off due to the dynamic variation in the effective parallel resistance. The time constant of this amplitude change is proportional to the resonator’s quality factor times the period of the oscillation.

τ = 2 * C total * RP ,eq =

Q

π

* Tcycle

Since the quality factor of the external components is expected to be at least 1650,

34

even with the existence of on-chip loss, we can still expect the time constant of this amplitude modulation to be several oscillation periods that the oscillation amplitude is a perfect average of the two oscillation amplitudes when the switches are always off and on. Therefore, the step-like waveforms are mainly due to the finite energy of the inductor being distributed to different capacitance at the instant when the switches are turned on or off. Figure 22 shows a summary of the power consumption in each block in the system. The overall power consumption of the quadrature-coupled LC oscillators is 26.66µW, in which, 18.51µW is the inherent power consumption required for the two oscillators to have 1.4V oscillation amplitude. (1.544µW*2)=3.1µW is the additional power required by the switching activities. The rest 5µW is the power consumption of the coupling devices. 26.6 6 µ w 35.928 µ w quadrature os cillator

s ensor

c apacitor array

V+

MUX

C up coupling

C down V-

14-bit

clo ck g ene rator

co m parator

F ollow ing S ucce s sive A ppro xim ation A lg orithm

38µ w

digital filter digital outp ut

35

Figure 22 Summary of power consumption in each block

4.4 Comparison of Sinusoidal Wave and Square Wave Using 4-stage differential ring oscillator can easily generate square-wave clocks with quadrature phase difference. Not like quadrature-coupled LC oscillators which may fail to oscillate, ring oscillator can keep functioning when the capacitive loads of different outputs are different or changing although the phase relationship between different outputs deviates from 90 degrees. Therefore, it is not necessary to switch the load capacitor between the four quadrature phases.

There is no trade-off on power

consumption with switches’ physical size, either. However, the 14-bit capacitor array exhibits large capacitance compared to the usual active device sizes. The deviation of the phase relationship of different outputs from 90 degrees will be large if only on capacitor array is used. The design of the following comparator becomes difficult because of the tighter timing constraint. In order to maintain close to quadrature phase relationship between different outputs, at least 4 capacitor arrays should be used. This requires extremely large area. The power consumption of the overall system increases as well. To make a simple comparison, for the ring oscillator to drive the 4 14-bit capacitor arrays with square wave would consume at least: 1 1 1 1 Pringosc = 4 ⋅ ⋅ C load ⋅ Vswing ⋅ Vdd ⋅ f osc = 4 ⋅ ( ⋅ ⋅ 214 ⋅ 3.88 f ) ⋅ 1.4 ⋅ 1.8 ⋅ 2M ≅ 160 µW , 2 2 2 2

36

1 1 where C load = ( ⋅ ⋅ 214 ⋅ C 0 ) is the maximum capacitance of the 14-bit capacitor array 2 2 seen from the oscillator. This is 6 times larger than the power needed than if using quadrature-coupled LC oscillator with capacitor-array architecture A as shown in the simulation result in Figure 22.

37

Chapter 5 Conclusion A complete 2-MHz clock generator for low-power MEMS capacitive-sensing circuits is designed and simulated with 0.18-µm 1.8-V TSMC CMOS technology. Based on the architectural requirement, the generator is composed of quadrature-coupled LC oscillators and a digital clock generator for the clocking signals of the rest of the system. In order to reduce the overall power consumption, LC oscillators are used to resonate the capacitive sensor and the capacitor array, which exhibit substantial capacitance. Simulation result shows 6-time difference in power consumption between the choice of quadrature-coupled LC oscillators and a ring oscillator. The quadraturecoupled LC oscillators also provide quadrature output signals as mandated by the rest of the system.

A novel technique of switching the load capacitors between the two

oscillators is introduced to balance the effective capacitive load seen by the four quadrature phases. By identifying different sources of loss, the overall power consumption can be minimized. Because of the switching activity, the trade-off between the switches’ onresistance and gate capacitance leads to an optimal choice of switch size from power consumption point of view. The clock generator is designed to synchronize the switches’ controlling signals and the oscillation signals. Furthermore, the devices in the clock generator are properly sized to minimize the timing error in order to further reduce the additional power due to the switching.

38

In the future, the circuits need to be fabricated with the rest of the system. Measurement results are needed in order to verify the idea of switching the load capacitor between the two oscillators.

39

Appendix A CMOS LC Oscillator with Variable Mean Frequency This work presents a fully integrated CMOS LC oscillator with digital tuning. The frequency tuning is by averaging over two oscillation frequencies. The average frequency is determined by the digital input pattern, which switches a small unit of capacitance on and off the main capacitor. Measurement in a 0.18-µm CMOS test-chip shows that 5 bits of additional resolution can be achieved. With the inductor dominating the quality factor, Q, the phase noise remains almost the same, not affected by this averaging activity.

A.1 Basic Principle An LC oscillator can be tuned continuously with varactors or discretely by connecting different capacitors across a fixed inductor [14]. Using a large varactor to achieve the desired tuning range can often introduce significant phase noise due to the varactor’s non-linearity and the random voltage fluctuation on the control voltage [10]. Moreover, the VCO gain, Kv (Hz/V), is typically not constant, which my require further design considerations.

Designers often use digitally controllable capacitors in

conjunction with the varactor to extend the tuning range while maintaining reasonable phase noise performance. A purely digital controlled approach has not been used for LC oscillator tuning because the frequency step is discrete and limited by the precision of capacitance in different technologies.

40

This work describes a fine frequency-tuning technique indicating the potential of a digitally tuned LC oscillator. The technique continuously switches a small unit of capacitance from the main LC tank. By changing the digital input pattern, the mean frequency of the output oscillation signals changes by averaging over the two frequencies. For example, if in every (x+y) cycles, the switches are on for x cycles and off for y cycles, the average frequency can be expressed as:

fm ≅

y ⋅ f main + x ⋅ ( f main + ∆f ) , ( x + y)

(5)

where the operating frequency is fmain when the switches are off, and (fmain+∆f) when the switches are on. The capacitance resolution limits the ∆f while the average frequency depends on x and y. As will be shown, although the switching introduces tones and sidebands, the close-in phase noise is not significantly perturbed.

A.2 Architecture The basic circuit building block, shown in Figure 23, consists of a CMOS oscillator with a main LC tank, a small unit of capacitor C0 connected to the main capacitor through CMOS switches, a differential to single-ended amplifier, a D flip-flop, and a set of two parallel variable delay lines that controls the switches. The negative resistance of the oscillator is formed by both NMOS and PMOS cross-coupled devices [9]. The negative gm not only compensates the loss from the lowQ on-chip inductor but also the on-resistance of the switches. Since the instantaneous oscillation frequency changes when the switches are on and off, the duration for each digital input bit has to be different depending on whether 41

the switches are on or off. Therefore, the digital signal that is switching the capacitor C0 must be properly synchronized by the LC outputs. The differential to single-ended amplifier buffers the LC output and the D flip-flop uses the buffered clock to synchronize the digital input pattern. For accurate switching, the design compensates for the difference in the D flipflop’s clock-to-Q delay for rising and falling edges. Two delay lines, which can be tuned independently, drive the rising and falling edges separately so that the switching occurs exactly at multiples of the oscillation period. Digital Pattern Input

Negative Gm

D

Q DFF

C0 main LC tank

Delay Control #1

Delay Control #2

tri-state buffer

Figure 23 Complete Architecture Block Diagram

Notice that, with x and y in Eq. (5) being fractional numbers instead of integers, we can have finer frequency step smaller than

42

∆f . ( x + y)

A.3 Tones due to Averaging A.3.1 Frequency Modulation The

digitally

controlled

dynamic

switching

effectively

modulates

the

instantaneous operating frequency of the LC oscillator. If the edges of the switches’ controlling signals are sharp enough, the circuit topology changes immediately after the switches are turned on or off. Since the current and voltage of the negative resistance circuit are always in phase, the circuit can only operate at the frequency where the LC tank exhibits zero-phase impedance as shown in Figure 25. Therefore, the operating frequency changes immediately after the switches are turned on or off.

Negative

Negative

Gm

Gm Ztank,O

Ztank,OFF Cmain

RC

Lmain

RL

N Cmain

RC

Lmain

RL

RON (a) When switches are OFF

C0

RON

(b) When switches are ON

Figure 24 The circuit topology changes when switches turn on/off

43

Z tank,OFF

Phase

Magnitude

Z tank,ON

ω2

ω1

Figure 25 Impedance of the LC tank when the switches are off and on

Figure 26 Frequency Modulation

The result of the frequency modulation appears as additional tones in the frequency spectrum that depend on the input pattern. For instance, the oscillator can operate at the same average frequencies from two different modulation signals; i.e. [ f main + ( f main + ∆f )] [2 f main + 2( f main + ∆f )] and . 2 4

44

The first case illustrates tones at

multiples of fm/2. While in the second case, the tones are located at multiples of fm/4, which are harmonics of the base modulating frequency. Both cases are shown in Figure 26. As expected, the longer period of the modulating signal results in harmonics closer to the operating frequency. The height of the side tones depends on the ratio of

C0 . The larger the ratio is, C main

the higher the side tones.

A.3.2 Amplitude Modulation The dynamic switching introduces dynamic variation in the effective parallel resistance, which is explained in detail in Chapter 2 and 3, in the oscillator. This appears as amplitude modulation in addition to the frequency modulation. There are two factors of this variation: 1) change in LC frequency, and 2) CMOS switch on-resistance.

Negative Negative

Gm

Gm Cmain

RC

Lmain

RL

Cmain

RC

Lmain

RL

RON

(a)

C0

RON

(b)

Figure 27 Parasitic Resistance (a) when switches are OFF (b) When switches are ON

45

RP , eff (t ) =

1 1 RC (ω0Cmain ) 2 + RL ( )2 ω0 Lmain

//

1 (2 RON )(ω0C0 ) 2

(6)

As shown in Figure 27 and Eq. (6), first, since the instantaneous operating frequency ( ω0 ) is different when the switches are on and off, the effective resistance due to the loss in different components (the first term in Eq. (6)) changes as the operating frequency changes [8]. The second factor is less significant because the on-resistance of the CMOS switches is quite small and the switched capacitor, C0, in series is also very small. In cyclostationary state, when the oscillator is biased at low currents, the amplitude of the oscillation changes proportionally to the effective parallel resistance [10]. (If the bias current is high such that the output oscillation amplitude is saturated, we will not see much amplitude modulation.) However, with the dynamic switching, it takes time for the negative-Gm circuits to restore the oscillation amplitude to its new final value immediately after the switches are turning on or off.

We can derive the time

constant based on the following analysis. The analysis applies to both turning on and turning off the switches. For simplicity, assume that the average negative-Gm is inversely proportional to the oscillation amplitude (valid when the oscillator is biased at low currents). Also assume that the effective parallel resistance is R1 before the switching and R2 after the switching. Gm(t ) =

K , where K is a constant. A(t )

46

We know that Gm(0) =

1 1 and Gm(∞) = . R1 R2

The resulting parallel combination of the negative-Gm and effective parallel resistance after the switching is [

1 − Gm(t )]−1 , which is the “resistance” seen from the R2

pure LC tank. Based on the basic principle of oscillation, if this resulting combination is positive, 2 ⋅ C ⋅[

the

amplitude

decreases

exponentially

with

a

time

constant

of

1 − Gm(t )]−1 , where C is the capacitance in the pure LC tank after the switching. R2

Therefore, Gm(t) increases until the combination reaches zero and the oscillation amplitude is constant.

A(t + ∆t ) = A(t ) ⋅ exp[−

K ∆t 1 ( − )] . 2 ⋅ C R2 A(t )

  ∆t 1 K   − )  − 1 (  exp − 2 ⋅ C R2 A(t )   A(t + ∆t ) − A(t )   => = A(t ) ⋅  . ∆t ∆t      

  ∆t 1 K   )  − 1 ( −  exp − 2 ⋅ C R2 A(t )   A(t + ∆t ) − A(t )   =lim A(t ) ⋅  => lim . ∆t ∆t ∆t →0 ∆t →0       => A' (t ) = A(t ) ⋅

−1 1 K ) ( − 2 ⋅ C R2 A(t )

We can finally derive that: A(t ) = K ⋅ R2 + K ⋅ ( R1 − R 2 ) ⋅ exp(−

47

t ). 2 ⋅ C ⋅ R2

Notice that, the larger the quality factor of the LC tank is, the longer it takes for the oscillation amplitude to reach its final value.

A.3.3 Overall Effect due to Modulation The frequency and amplitude modulation described above have the same modulating frequency as the digital input pattern. Therefore, the tones and sidebands resulting from these two factors are at the same frequencies. The amplitude modulation has less effect than the frequency modulation. The amplitude modulation only changes the closest tone by less than 1.5dB depending on the digital input pattern and the bias current. Although we can achieve virtually continuous frequency tuning by using arbitrarily long modulation period, the signal sideband of an application limits the period and hence bounds the tuning resolution.

48

A.4 Switching Timing

(A)

(B)

(C)

OFF

OFF

ON

OFF

OFF

ON

OFF

ON

OFF

ON

ON

OFF

OFF

ON

ON

ON

Figure 28 Different Switching Timing

The switching of the capacitor should be timed such that the charge on C0 does not degrade the oscillating signals. Ideally, the voltage across C0 before disconnecting from the LC tank and after reconnecting to the tank should be the same. Any voltage error is equivalent to a parallel resistance across the LC tank and degrades the quality factor, Q. The condition can be satisfied at a number of points as illustrated in Figure 28. The switching can occur at the zero crossing points separated by a half-cycle (A), at the zero crossing points separated by a full-cycle (B), or at the peaks of the oscillation (C), Although half-cycle timing is easier, switching points in (A) are sensitive to common-mode shifts in the delay of the delay line. Noise such as a supply bounce can introduce a large voltage error on the capacitor.

49

Using full-cycle delay for timing

eliminates common-mode delay-line variations (B), but the oscillator phase is easily perturbed at zero-crossing points by switch timing noise [15]. Although switching at the peaks of the waveform (C) results in some residual charge on C0 due to the amplitude modulation described previously, it has the least impact on phase-noise performance. However, generating the correct phase shift can be difficult since it requires a quartercycle shift from the clock zero crossings. The overall phase noise is slightly worse than an un-switched LC oscillator also because of the dynamic variations in the effective parallel resistance. Since the on-chip inductor dominates the Q, we expect the switching to have only a modest impact on the phase noise.

A.5 Experimental Results The chip was fabricated with 0.18-µm 1.8-V National CMOS technology. The oscillator uses a 9.58nH spiral inductor with Q of 4.89 at 900MHz. Figure 30 shows the measured output frequency with different digital input pattern. With a modulation period of 32, the output average frequency decreases by approximately ∆f /32 as the number of ones in the digital input pattern increases.

50

Main inductor

Main capacitor C0 Negative gm, Differential Amplifier, D flip-flop, and variable delay line

Figure 29 Die Photo of the oscillator

Digital input pattern with period of 32 668

output frequency (MHz)

667 666 665 664 663 662 661 660 659 0

4

8

12

16

20

24

28

number of ones in the digital input pattern

32

Figure 30 The change in average frequency according to different digital input pattern

51

DNL

0.3 0.2

LSB

0.1 0

-0.1 -0.2 -0.3 -0.4 0

4

8

12

16

20

24

28

number of ones in the digital input pattern

32

Figure 31 The DNL of the output average frequency

In Figure 31, the measured differential non-linearity (DNL) for different digital input pattern is plotted. The magnitude of the maximum DNL is roughly –0.3 LSB. Figure 32 is the output frequency spectrum showing the impact of the side tones due to the frequency and amplitude modulations when the digital input pattern consist of 1 zero and 31 ones. The switched capacitance, C0, is roughly 2% of the tank capacitance, Cmain.

With fmain=666.878MHz and (fmain+∆f)=660.355MHz, the resulting average

frequency is fm=660.54MHz, ∆f /32 higher than (fmain+∆f). The closest tone occurs at 639.84MHz, which is roughly fm/32 away from fm and is 42.81dB lower than the main frequency. The frequency difference between the side tones is roughly fm /32. The second and third closest tones occur at 619MHz and 598.24MHz and are 50.263dB and 53.023dB lower than the main frequency.

52

53.02dB

50.26dB 42.81dB

Figure 32 Spectrum of the output oscillation signal and the closest tones

(A)

(B)

(C)

62.33dB

660.355MHz

63.92dB

62.02dB

660.54MHz

666.878MHz

Figure 33 Phase Noise Performances

Figure 33 shows the measured phase noise performances.

At a 200-kHz

frequency offset, the measured phase noise at fm is -106.79dBc/Hz. Compared to 108.69dBc/Hz at fmain and -107.10dBc/Hz at (fmain+∆f), the phase noise is not significantly affected by the averaging activity. According to the measurement results, by changing the delay of the two delay lines, different switch timing results in roughly 0.5dB difference in phase noise.

53

Increasing the period of modulating signals can result in an additional 1dB phase noise improvement. If the center frequency is shifted to 2.4GHz, based on the same architecture with modulation period of 128, the performance satisfies the requirements of the IEEE 802.11b standard. In the specification, the center frequency should be within ±60kHz of the nominal center frequency, and the transmitted spectral products must be