Varactor-driven Temperature Compensation of CMOS ... - IEEE Xplore
Varactor-driven Temperature Compensation of CMOS Floating-gate Current Memory Ming Gu, Shantanu Chakrabartty Department of Electrical and Computer Engineering, Michigan State University East Lansing, MI 48824-1226 USA {guming1, shantanu}@egr.msu.edu
Abstract—Floating-gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on floatinggate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated floatinggate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the floatinggate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the floating-gates. We validate the proof-ofconcept using measurement results obtained from prototype current memory cells fabricated in a 0.5µm CMOS process. Index Terms—Current memory, neural systems, temperature compensation, floating-gate transistors, sub-threshold, analog processors
I. I NTRODUCTION Implementation of analog processors and neural systems [1], [2] require compact storage of a large number of analog parameters (voltage or current). In this regard, floating-gate (FG) transistors are attractive for implementing high-density, non-volatile current memories. Two types of FG currentmemories have been reported in literature and are summarized in Fig. 1. The first variant of the FG current memory [3] shown in Fig. 1(a) consists of a pre-compensation stage formed by a FG transistor P1 and an output transistor P2 , which forms the current memory cell. A and B are the floating-gate nodes where the charge is stored. Because the nodes are completely insulated by high quality silicon-dioxide, any charge trapped on it is retained for a long period of time (8 bits retention accuracy for less than 8 years) [2], [3]. If QA and QB denote the charge stored on nodes A and B respectively, then the output current Iout can be expressed as QB − QA Iout ≈ Iref exp κ , (1) CT UT where κ is the gate-efficiency factor, CT is the total capacitance seen at nodes A and B, and UT = kT /q is the thermal voltage which is directly proportional to temperature T . Equation (1) illustrates that Iout exhibits an exponential dependence with respect to temperature. The second variant of the FG current memory [4], [5] as shown in Fig. 1(b) overcomes this problem by using a modified version of a standard PTAT. Note that instead of using different sizes of 978-1-4673-0219-7/12/$31.00 ©2012 IEEE
pMOS transistors in the current mirror, the circuit uses a floating-gate voltage element formed by the capacitor C. If the charge on C is denoted by Q and if all the transistors are biased in weak-inversion, then the output current is given by Iout ≈ κQ/CT R,
(2)
where CT is again the total capacitance seen at node D. Provided the resistance R is compensated for temperature, the output current will also be compensated for temperature. However, compared to the current memory in Fig. 1(a), the memory shown in Fig. 1(b) requires a large resistance (>100MΩ) for generating sub-threshold currents, which prohibits its application for high-density arrays. Also, the quality of temperature compensation deteriorates at ultra-low currents or when active resistances are used for emulating a large R. In this paper, we propose an alternative approach for implementing high-density, temperature compensated floatinggate current memories. The approach uses a voltage controlled capacitor (varactor) to adapt the floating-gate capacitance CT in equation (1) such that the product CT UT remains constant with respect to temperature. Hence, the output current is only determined by the differential charge stored on the floatinggate nodes and is theoretically independent of the temperature. The paper is organized as follows: Section II introduces the basic compensation principle which is then verified in section III using measurement results obtained from the fabricated current-memory cells. Section IV concludes the paper with some final remarks. II. VARACTOR BASED F LOATING - GATE T EMPERATURE C OMPENSATION The architecture of the proposed varactor-based floatinggate current memory cell is shown in Fig. 2. It consists of a reference cell formed by two floating-gate transistors P1 and P2 . Note that in addition to the usual control-gate capacitor Cc and tunneling capacitor Ctun , all the floating-gate transistors have a varactor Cv connected to their respective gates. The currents through P1 and P2 (measured using an on-chip analog-to-digital converter) are controlled by a control module which sets the control-gate voltage Vc and tuning voltage Vx using an off-chip digital-to-analog converter. If the charge on the floating-gate nodes A and B are denoted by Q1 and Q2 , then the gate voltages for the pMOS transistors P1
2095
A
held constant according to
B
P1
P2 C
CT UT = κ
C
I ref
I out
Thus, if the current I2 is compensated for temperature, then according to equation (7), the current through the memory cells are also temperature compensated. In principle, I2 could be generated by a bandgap reference circuit [6] or by a circuit similar to Fig. 1(b). For this implementation, we tried to maintain I2 to be constant by co-adapting the control-gate voltage Vc along with the tuning voltage Vx .
D P2
C
N1
N2
(6)
which leads to the expression for the output current Iout generated through the memory cell as I2 Q3 − Q2 = exp log(K) . (7) Iout Q1 − Q2
(a)
P1
Q1 − Q2 log(K)
P3
I out
A. Varactor Implementation and Second-order Effects
The varactor has been realized using a MOS capacitor which operates in an accumulation mode [7]. The cross-sectional architecture and the layout of the MOS-cap is shown in Fig. 3 (b) along with the floating-gate transistor, the control-gate and the tunneling-node. The use of MOS-cap as a varactor introduces Fig. 1. Topology of conventional current memory cell: (a) pre-compensation based; (b) PTAT based. second-order effects into the equation (7): • Derivation of equation (7) assumed that the floatinggate transistors including the variable capacitors Cv are and P2 are given by matched with respect to each other. Unfortunately, each Q1 + Cc · Vc + Cv · Vx + Ctun · Vtunnel + Cb · Vdd floating-gate node is programmed to a different potential, VA ≈ , (3) CT which will lead to mismatch in Cv . In weak-inversion, Q2 + Cc · Vc + Cv · Vx + Ctun · Vtunnel + Cb · Vdd however, the difference between respective gate-voltages VB ≈ . (4) CT is small (less than 100mV), which reduces the effect of the mismatch. • The variation of Cv with respect to the tuning voltage Buffer Buffer Vx is non-linear as shown in the measured response in Vtunnel V Vtunnel tunnel Fig. 5. Therefore, Vx and Vc has to be biased properly to Ctun Ctun Ctun ensure: (a) sub-threshold biasing of the transistors; and Q1 Q2 Q3 (b) high-sensitivity of Cv with respect to Vx . P1 P2 P3 A B • The MOS-cap C also varies with temperature. However, C C C C C C v Vc ... the temperature model of a MOS varactor is too complex CV CV CV Vx for any closed-form calibration, which motivates adapting ... Vx in an online manner. I out I1 I2 III. E XPERIMENTAL RESULTS R
+
+
Control Algorithm
Fig. 2. cells
Memory Cell
Proposed floating-gate based current reference and current memory
When P1 and P2 are biased in weak-inversion, the respective ratio of their drain-currents I1 and I2 is given by Q1 − Q2 I2 = exp κ . (5) I1 CT UT The control module in Fig. 2 monitors I1 and I2 and ensures that the their ratio remains constant across temperature variations by tuning the voltage Vx which changes the capacitance CT . Letting K = I2 /I1 , then the the parameter CT UT is also
An array of varactor-based FG current memory cells has been prototyped in a 0.5µm standard CMOS process. Table I summarizes the specification of the fabricated prototype and Fig. 4 shows its micrograph. Programming of the FG memory cells is based on the hot-electron injection and FowlerNordheim (FN) tunneling, whose details have been presented elsewhere [1], [3] and has been omitted here for the sake of brevity. In the first set of experiments, the floating-gate voltage VA was measured (using a voltage buffer shown in Fig 2) when Cv was determined Vx was tuned and Vc = 1.2V . The ratio Cc based on the sensitivity analysis of the current I1 with respect to Vx and Vc . The measurement result in Fig. 5 shows that
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the capacitance is inversely proportional to Vx and shows the largest change in capacitance occurs at Vx = 1.25V . The experiment also demonstrates that Cv can be varied over a large dynamic range with respect to Vx , which should be sufficient to compensate for large temperature variations.
VFG VX
n
n 0.5
N ! Well 0.4
VX
Cv/Ctotal
(a)
P-Well
VFG
0.3 0.2
N-Well Metal1
0.1 0
Poly1 N active P active Floating-gate Transistor
Varactor
Fig. 5.
Cc
Ctun
(b) Fig. 3. (a) Cross-sectional architecture of MOS varactor (b) Layout for memory cell in Fig. 2
TABLE I S PECIFICATION OF THE FABRICATED
Fabrication Process Die Size Size of P1 -P3 Cc
1
1.5 Vx (V)
2
2.5
The C-V curve of MOS capacitor
Poly2
Vtunnel
VC
0.5
PROTOTYPE
Standard CMOS 0.5µm 3000µm × 3000µm 6µm/3µm 100fF
The next set of experiment measures the ratio of currents I2 /I1 and I2 /Iout as the voltages Vc and Vx are varied. The experimental results shown in Fig. 6(a) and (b) validate that in the weak-inversion regime, the current ratios are approximately invariant with respect to Vc whereas vary proportional to Vx . That validates the relationship given by equation (6). For the last set of experiments, we measured the current ratios under two different temperatures, namely 80◦ F and 90◦ F, when the voltages Vc is fixed to be 2V and Vx is varied. The results shown in Fig. 7(a) and (b) demonstrate that with the increase in temperature, the respective current ratios decrease as indicated by the relationship in equation (6). The I2 control algorithm then varies Vx to ensure that the ratio is I1 maintained to be constant. The trajectory of the Vx traversed by the control algorithm is shown in Fig. 7(a) and Fig. 7(b) I2 shows the corresponding value of the ratio . The result Iout I2 also shows a small error in the compensation of which Iout is due to the mismatch in the floating-gate capacitance. Fig. 2 shows that the cause of this mismatch is due to the connection to the unity-gain buffer in the reference cell. However, the results show that the current through the memory cell shows much less variation with respect to temperature compared to an uncompensated current memory cell. This simple demonstration validates the proof-of-concept temperature compensation for the proposed floating-gate current memory. IV. C ONCLUSIONS AND D ISCUSSION
Fig. 4.
Die microphotograph of the chip
In this paper, we have presented the design of a novel, compact array of floating-gate current memory which is compensated for variations in temperature. The current stored in the memory cell is theoretically determined by the differential charge stored on the floating-gate current references and our analysis indicate that temperature compensation can 2097
3
6 I2 / IOut
I2 / I1
2.5 2 1.5
4 2
1.6
1 2
1.6
1.4 2.2
0
1.2
2.4 Vc (V)
1.4 2
2.2
Vx (V)
2.4 Vc (V)
(a) Fig. 6.
(a) Measured response plotting
Vx (V)
(b) I2 I2 with respect to Vc and Vx ; (b) Measured response plotting with respect to Vc and Vx I1 Iout
T=80 F T=90 F
T=80 F 0.6
10
1.2
T=90 F
0.4
10
δ Vx
I2/Iout
I2/I1
0.5
10
δ Vx
Temperature change δ(I2/I1)
0.3
10
control algorithm 0.1
0.2
10
1.1
1.2
1.3 1.4 Vx (V)
1.5
10
1.6
(a) Fig. 7. and
(a) Measured response plotting
90◦ F.
1.1
1.2
1.3 1.4 Vx (V)
1.5
1.6
(b)
I2 I2 with respect to Vx under 80◦ F with respect to Vx under 80◦ F and 90◦ F; (b) Measured response plotting I1 Iout
be achieved at current levels down to a few picoamperes. Using measured results from fabricated memory cells, we have demonstrated a proof-of-concept validation of the proposed compensation technique. However, several factors will limit the accuracy of the proposed techniques which includes: (a) mismatch between different varactors and floating-gate capacitances; and (b) second-order effects where the charge stored on the floating-gates alter the varactor response. Future work in this area will focus on mitigating these effects and implementing the control algorithm using on-chip continuoustime analog circuits. R EFERENCES [1] S. Chakrabartty and G. Cauwenberghs, “Sub-microwatt analog VLSI trainable pattern classifier,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1169–1179, May. 2007.
[2] A. Bandyopadhyay, G. J. Serrano, and P. Hasler, “Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2% of accuracy over 3.5 decades,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2107–2114, Sep. 2006. [3] A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, C. Petre, S. Koziol, F. Baskaya, C. M. Twigg, and P. Hasler, “A floating-gate-based fieldprogrammable analog array,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1781–1794, Sep. 2010. [4] V. Srinivasan, G. Serrano, C. Twigg, and P. Hasler, “A compact programmable cmos reference with ±40µv accuracy,” in IEEE Custom Integrated Circuits Conference, Sep. 2006, pp. 611–614. [5] N. Lajnef, S.Chakrabartty, and N.Elvin, “A sub-microwatt piezo-floatinggate sensor for long-term fatigue monitoring in biomechanical implants,” in IEEE Conference on Engineering in Medicine and Biology (EMBC 2006), New York, 2006. [6] B. Razavi, Design of analog CMOS integrated circuits. McGraw-Hill Science/Engineering/Math, Aug. 2000. [7] R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS-Gm LC VCOs,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1325–1332, Aug. 2003.
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Abstract—Floating-gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on floatinggate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated floatinggate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the floatinggate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the floating-gates. We validate the proof-ofconcept using measurement results obtained from prototype current memory cells fabricated in a 0.5µm CMOS process. Index Terms—Current memory, neural systems, temperature compensation, floating-gate transistors, sub-threshold, analog processors
I. I NTRODUCTION Implementation of analog processors and neural systems [1], [2] require compact storage of a large number of analog parameters (voltage or current). In this regard, floating-gate (FG) transistors are attractive for implementing high-density, non-volatile current memories. Two types of FG currentmemories have been reported in literature and are summarized in Fig. 1. The first variant of the FG current memory [3] shown in Fig. 1(a) consists of a pre-compensation stage formed by a FG transistor P1 and an output transistor P2 , which forms the current memory cell. A and B are the floating-gate nodes where the charge is stored. Because the nodes are completely insulated by high quality silicon-dioxide, any charge trapped on it is retained for a long period of time (8 bits retention accuracy for less than 8 years) [2], [3]. If QA and QB denote the charge stored on nodes A and B respectively, then the output current Iout can be expressed as QB − QA Iout ≈ Iref exp κ , (1) CT UT where κ is the gate-efficiency factor, CT is the total capacitance seen at nodes A and B, and UT = kT /q is the thermal voltage which is directly proportional to temperature T . Equation (1) illustrates that Iout exhibits an exponential dependence with respect to temperature. The second variant of the FG current memory [4], [5] as shown in Fig. 1(b) overcomes this problem by using a modified version of a standard PTAT. Note that instead of using different sizes of 978-1-4673-0219-7/12/$31.00 ©2012 IEEE
pMOS transistors in the current mirror, the circuit uses a floating-gate voltage element formed by the capacitor C. If the charge on C is denoted by Q and if all the transistors are biased in weak-inversion, then the output current is given by Iout ≈ κQ/CT R,
(2)
where CT is again the total capacitance seen at node D. Provided the resistance R is compensated for temperature, the output current will also be compensated for temperature. However, compared to the current memory in Fig. 1(a), the memory shown in Fig. 1(b) requires a large resistance (>100MΩ) for generating sub-threshold currents, which prohibits its application for high-density arrays. Also, the quality of temperature compensation deteriorates at ultra-low currents or when active resistances are used for emulating a large R. In this paper, we propose an alternative approach for implementing high-density, temperature compensated floatinggate current memories. The approach uses a voltage controlled capacitor (varactor) to adapt the floating-gate capacitance CT in equation (1) such that the product CT UT remains constant with respect to temperature. Hence, the output current is only determined by the differential charge stored on the floatinggate nodes and is theoretically independent of the temperature. The paper is organized as follows: Section II introduces the basic compensation principle which is then verified in section III using measurement results obtained from the fabricated current-memory cells. Section IV concludes the paper with some final remarks. II. VARACTOR BASED F LOATING - GATE T EMPERATURE C OMPENSATION The architecture of the proposed varactor-based floatinggate current memory cell is shown in Fig. 2. It consists of a reference cell formed by two floating-gate transistors P1 and P2 . Note that in addition to the usual control-gate capacitor Cc and tunneling capacitor Ctun , all the floating-gate transistors have a varactor Cv connected to their respective gates. The currents through P1 and P2 (measured using an on-chip analog-to-digital converter) are controlled by a control module which sets the control-gate voltage Vc and tuning voltage Vx using an off-chip digital-to-analog converter. If the charge on the floating-gate nodes A and B are denoted by Q1 and Q2 , then the gate voltages for the pMOS transistors P1
2095
A
held constant according to
B
P1
P2 C
CT UT = κ
C
I ref
I out
Thus, if the current I2 is compensated for temperature, then according to equation (7), the current through the memory cells are also temperature compensated. In principle, I2 could be generated by a bandgap reference circuit [6] or by a circuit similar to Fig. 1(b). For this implementation, we tried to maintain I2 to be constant by co-adapting the control-gate voltage Vc along with the tuning voltage Vx .
D P2
C
N1
N2
(6)
which leads to the expression for the output current Iout generated through the memory cell as I2 Q3 − Q2 = exp log(K) . (7) Iout Q1 − Q2
(a)
P1
Q1 − Q2 log(K)
P3
I out
A. Varactor Implementation and Second-order Effects
The varactor has been realized using a MOS capacitor which operates in an accumulation mode [7]. The cross-sectional architecture and the layout of the MOS-cap is shown in Fig. 3 (b) along with the floating-gate transistor, the control-gate and the tunneling-node. The use of MOS-cap as a varactor introduces Fig. 1. Topology of conventional current memory cell: (a) pre-compensation based; (b) PTAT based. second-order effects into the equation (7): • Derivation of equation (7) assumed that the floatinggate transistors including the variable capacitors Cv are and P2 are given by matched with respect to each other. Unfortunately, each Q1 + Cc · Vc + Cv · Vx + Ctun · Vtunnel + Cb · Vdd floating-gate node is programmed to a different potential, VA ≈ , (3) CT which will lead to mismatch in Cv . In weak-inversion, Q2 + Cc · Vc + Cv · Vx + Ctun · Vtunnel + Cb · Vdd however, the difference between respective gate-voltages VB ≈ . (4) CT is small (less than 100mV), which reduces the effect of the mismatch. • The variation of Cv with respect to the tuning voltage Buffer Buffer Vx is non-linear as shown in the measured response in Vtunnel V Vtunnel tunnel Fig. 5. Therefore, Vx and Vc has to be biased properly to Ctun Ctun Ctun ensure: (a) sub-threshold biasing of the transistors; and Q1 Q2 Q3 (b) high-sensitivity of Cv with respect to Vx . P1 P2 P3 A B • The MOS-cap C also varies with temperature. However, C C C C C C v Vc ... the temperature model of a MOS varactor is too complex CV CV CV Vx for any closed-form calibration, which motivates adapting ... Vx in an online manner. I out I1 I2 III. E XPERIMENTAL RESULTS R
+
+
Control Algorithm
Fig. 2. cells
Memory Cell
Proposed floating-gate based current reference and current memory
When P1 and P2 are biased in weak-inversion, the respective ratio of their drain-currents I1 and I2 is given by Q1 − Q2 I2 = exp κ . (5) I1 CT UT The control module in Fig. 2 monitors I1 and I2 and ensures that the their ratio remains constant across temperature variations by tuning the voltage Vx which changes the capacitance CT . Letting K = I2 /I1 , then the the parameter CT UT is also
An array of varactor-based FG current memory cells has been prototyped in a 0.5µm standard CMOS process. Table I summarizes the specification of the fabricated prototype and Fig. 4 shows its micrograph. Programming of the FG memory cells is based on the hot-electron injection and FowlerNordheim (FN) tunneling, whose details have been presented elsewhere [1], [3] and has been omitted here for the sake of brevity. In the first set of experiments, the floating-gate voltage VA was measured (using a voltage buffer shown in Fig 2) when Cv was determined Vx was tuned and Vc = 1.2V . The ratio Cc based on the sensitivity analysis of the current I1 with respect to Vx and Vc . The measurement result in Fig. 5 shows that
2096
the capacitance is inversely proportional to Vx and shows the largest change in capacitance occurs at Vx = 1.25V . The experiment also demonstrates that Cv can be varied over a large dynamic range with respect to Vx , which should be sufficient to compensate for large temperature variations.
VFG VX
n
n 0.5
N ! Well 0.4
VX
Cv/Ctotal
(a)
P-Well
VFG
0.3 0.2
N-Well Metal1
0.1 0
Poly1 N active P active Floating-gate Transistor
Varactor
Fig. 5.
Cc
Ctun
(b) Fig. 3. (a) Cross-sectional architecture of MOS varactor (b) Layout for memory cell in Fig. 2
TABLE I S PECIFICATION OF THE FABRICATED
Fabrication Process Die Size Size of P1 -P3 Cc
1
1.5 Vx (V)
2
2.5
The C-V curve of MOS capacitor
Poly2
Vtunnel
VC
0.5
PROTOTYPE
Standard CMOS 0.5µm 3000µm × 3000µm 6µm/3µm 100fF
The next set of experiment measures the ratio of currents I2 /I1 and I2 /Iout as the voltages Vc and Vx are varied. The experimental results shown in Fig. 6(a) and (b) validate that in the weak-inversion regime, the current ratios are approximately invariant with respect to Vc whereas vary proportional to Vx . That validates the relationship given by equation (6). For the last set of experiments, we measured the current ratios under two different temperatures, namely 80◦ F and 90◦ F, when the voltages Vc is fixed to be 2V and Vx is varied. The results shown in Fig. 7(a) and (b) demonstrate that with the increase in temperature, the respective current ratios decrease as indicated by the relationship in equation (6). The I2 control algorithm then varies Vx to ensure that the ratio is I1 maintained to be constant. The trajectory of the Vx traversed by the control algorithm is shown in Fig. 7(a) and Fig. 7(b) I2 shows the corresponding value of the ratio . The result Iout I2 also shows a small error in the compensation of which Iout is due to the mismatch in the floating-gate capacitance. Fig. 2 shows that the cause of this mismatch is due to the connection to the unity-gain buffer in the reference cell. However, the results show that the current through the memory cell shows much less variation with respect to temperature compared to an uncompensated current memory cell. This simple demonstration validates the proof-of-concept temperature compensation for the proposed floating-gate current memory. IV. C ONCLUSIONS AND D ISCUSSION
Fig. 4.
Die microphotograph of the chip
In this paper, we have presented the design of a novel, compact array of floating-gate current memory which is compensated for variations in temperature. The current stored in the memory cell is theoretically determined by the differential charge stored on the floating-gate current references and our analysis indicate that temperature compensation can 2097
3
6 I2 / IOut
I2 / I1
2.5 2 1.5
4 2
1.6
1 2
1.6
1.4 2.2
0
1.2
2.4 Vc (V)
1.4 2
2.2
Vx (V)
2.4 Vc (V)
(a) Fig. 6.
(a) Measured response plotting
Vx (V)
(b) I2 I2 with respect to Vc and Vx ; (b) Measured response plotting with respect to Vc and Vx I1 Iout
T=80 F T=90 F
T=80 F 0.6
10
1.2
T=90 F
0.4
10
δ Vx
I2/Iout
I2/I1
0.5
10
δ Vx
Temperature change δ(I2/I1)
0.3
10
control algorithm 0.1
0.2
10
1.1
1.2
1.3 1.4 Vx (V)
1.5
10
1.6
(a) Fig. 7. and
(a) Measured response plotting
90◦ F.
1.1
1.2
1.3 1.4 Vx (V)
1.5
1.6
(b)
I2 I2 with respect to Vx under 80◦ F with respect to Vx under 80◦ F and 90◦ F; (b) Measured response plotting I1 Iout
be achieved at current levels down to a few picoamperes. Using measured results from fabricated memory cells, we have demonstrated a proof-of-concept validation of the proposed compensation technique. However, several factors will limit the accuracy of the proposed techniques which includes: (a) mismatch between different varactors and floating-gate capacitances; and (b) second-order effects where the charge stored on the floating-gates alter the varactor response. Future work in this area will focus on mitigating these effects and implementing the control algorithm using on-chip continuoustime analog circuits. R EFERENCES [1] S. Chakrabartty and G. Cauwenberghs, “Sub-microwatt analog VLSI trainable pattern classifier,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1169–1179, May. 2007.
[2] A. Bandyopadhyay, G. J. Serrano, and P. Hasler, “Adaptive algorithm using hot-electron injection for programming analog computational memory elements within 0.2% of accuracy over 3.5 decades,” IEEE J. Solid-State Circuits, vol. 41, no. 9, pp. 2107–2114, Sep. 2006. [3] A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, C. Petre, S. Koziol, F. Baskaya, C. M. Twigg, and P. Hasler, “A floating-gate-based fieldprogrammable analog array,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1781–1794, Sep. 2010. [4] V. Srinivasan, G. Serrano, C. Twigg, and P. Hasler, “A compact programmable cmos reference with ±40µv accuracy,” in IEEE Custom Integrated Circuits Conference, Sep. 2006, pp. 611–614. [5] N. Lajnef, S.Chakrabartty, and N.Elvin, “A sub-microwatt piezo-floatinggate sensor for long-term fatigue monitoring in biomechanical implants,” in IEEE Conference on Engineering in Medicine and Biology (EMBC 2006), New York, 2006. [6] B. Razavi, Design of analog CMOS integrated circuits. McGraw-Hill Science/Engineering/Math, Aug. 2000. [7] R. L. Bunch and S. Raman, “Large-signal analysis of MOS varactors in CMOS-Gm LC VCOs,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1325–1332, Aug. 2003.
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