00Solutions to Midterm Fall 2009
00Solutions to Midterm Fall 2009 Question 1: Boolean Logic Theory (15 marks) Given the following function: f (a,b,c,d) = " m(0,1,4,5,7,8,10,13,14,15) : a) List all prime implicants, indicating which are essential. b) Show the minimum Sum-of-Products (SoP) expression. c) Draw the circuit implementing the minimum SoP from part (b). You can use any type of gates.!How many AND and OR gates would be needed to implement the original, non-minimal function f(a,b,c,d) ? Hint: You can use either the Karnaugh Map or Quine-McCluskey method to perform the function minimization in part (b).
Solution: a) The K-Map in Figure 1.a shows all of the prime implicatns circled. The 1’s that have been covered only once are indicated with an asteriks: • Essential prime implicants: a’c’, bd, • Other prime implicants: b’c’d’, ab’d’, acd’, abc.
Figure 1: K-Maps for Question 1 Alternatively, we can use Quine-McCluskey method to find prime and essential implicants.
Finding Prime Implicants: 0. 0000 √ -----------1. 0001 √ 4. 0100 √ 8. 1000 √ ----------5. 0101 √ 10. 1010 √ ----------7. 0111 √ 13. 1101 √ 14. 1110 √ ----------15. 1111 √ (0,1) 000_ √ (0,4) 0_00 √ (0,8) _000 ----------------(1,5) 0_01 √ (4,5) 010_ √ (8,10) 10_0 ----------------(5,7) 01_1 √ (5,13) _101 √ (10,14) 1_10 ------------------(7,15) _111 √ (13,15) 11_1 √ (14,15) 111_ (0,1,4,5) 0_0_ (5,7,13,15) _1_1 Prime Implicants are: b’c’d’, ab’d’, acd’, abc, a’c’, bd Determining Essential Prime Implicants:
Prime Implicants b’c’d’ _000 ab’d’ 10_0 acd’ 1_10 abc 111_ a’c’ 0_0_ bd _1_1
0 0000 √
1 0001
4 0100
5 0101
7 0111
8 1000 √
10 1010
√
√
13 1101
√
14 1110
√ √
√
√
√
15 1111
√
√ √
√
√
√
Essential Prime Implicants are: a’c’, bd Other Prime Implicants are: b’c’d’, ab’d’, acd’, abc. b) On the second K-Map, the essential prime implicants have been shaded, Figure 1.b, highlighting the three 1’s remaining to be covered. We need two terms to cover them, as least one of which must cover two of these remaining 1’s. The three possible solutions are: f(a,c,b,d) = a’c’ + bd + acd’ + b’c’d’ f(a,c,b,d) = a’c’ + bd + ab’d’ + acd’ f(a,c,b,d) = a’c’ + bd + ab’d’ + abc. c) The sample two-level SoP circuit for the first minimized equation is in Figure 2. The two remaining possible solutions from part b) are equally easy to draw. The original, non-minimized function f was described in terms of 10 minterms, each having 4 variables. Assuming that the straight and inverted signals are available at the inputs to the circuit, the original, non-minimized SoP of f could be implemented using 10 4-inpit AND gates, and 1 10-input OR gate. In total, there would be 11 gates. However, in practice, 10-input OR gate is not implementable, hence we would need to use few OR gates of fewer inputs (for example instead we could use 2 5-input OR gates, and 1 2-input OR gate).
Figure 2: Circuit Implementation of Function f from Part b of Question 1
Question 2: CMOS Circuit Technology Design (10 marks)
Design a CMOS logic gate that implements the function: Y = A + BC + BD . On the schematics indicate which transistors belong to the pull-up and which to the pull-down network. !
Solution: Start with the logic circuit Y’ = A + BC + BD. This function can be immediately implemented using PDN (NMOS transistors), Figure 3.
Figure 3: PDN Network for Question 2 PMOS network is constructed by symmetrical reflection of NMOS Network, Figure 4.
Figure 4: CMOS Implementation of Y = (A+BC+BD)'
Question 3: VHDL (10 marks) Write a complete VHDL description of a circuit that implements the Boolean function y = x1 x2 + x1 x3 ! x3 x4 . Use simple assignment statements, each having no more than 2 signals on the right hand side.
Solution: entity Q3 is port(x1, x2, x3, x4 : in std_logic; y : out std_logic); end Q3; architecture A of Q3 is signal i1, i2, i3, i4 : std_logic; begin i1
Solution: a) The K-Map in Figure 1.a shows all of the prime implicatns circled. The 1’s that have been covered only once are indicated with an asteriks: • Essential prime implicants: a’c’, bd, • Other prime implicants: b’c’d’, ab’d’, acd’, abc.
Figure 1: K-Maps for Question 1 Alternatively, we can use Quine-McCluskey method to find prime and essential implicants.
Finding Prime Implicants: 0. 0000 √ -----------1. 0001 √ 4. 0100 √ 8. 1000 √ ----------5. 0101 √ 10. 1010 √ ----------7. 0111 √ 13. 1101 √ 14. 1110 √ ----------15. 1111 √ (0,1) 000_ √ (0,4) 0_00 √ (0,8) _000 ----------------(1,5) 0_01 √ (4,5) 010_ √ (8,10) 10_0 ----------------(5,7) 01_1 √ (5,13) _101 √ (10,14) 1_10 ------------------(7,15) _111 √ (13,15) 11_1 √ (14,15) 111_ (0,1,4,5) 0_0_ (5,7,13,15) _1_1 Prime Implicants are: b’c’d’, ab’d’, acd’, abc, a’c’, bd Determining Essential Prime Implicants:
Prime Implicants b’c’d’ _000 ab’d’ 10_0 acd’ 1_10 abc 111_ a’c’ 0_0_ bd _1_1
0 0000 √
1 0001
4 0100
5 0101
7 0111
8 1000 √
10 1010
√
√
13 1101
√
14 1110
√ √
√
√
√
15 1111
√
√ √
√
√
√
Essential Prime Implicants are: a’c’, bd Other Prime Implicants are: b’c’d’, ab’d’, acd’, abc. b) On the second K-Map, the essential prime implicants have been shaded, Figure 1.b, highlighting the three 1’s remaining to be covered. We need two terms to cover them, as least one of which must cover two of these remaining 1’s. The three possible solutions are: f(a,c,b,d) = a’c’ + bd + acd’ + b’c’d’ f(a,c,b,d) = a’c’ + bd + ab’d’ + acd’ f(a,c,b,d) = a’c’ + bd + ab’d’ + abc. c) The sample two-level SoP circuit for the first minimized equation is in Figure 2. The two remaining possible solutions from part b) are equally easy to draw. The original, non-minimized function f was described in terms of 10 minterms, each having 4 variables. Assuming that the straight and inverted signals are available at the inputs to the circuit, the original, non-minimized SoP of f could be implemented using 10 4-inpit AND gates, and 1 10-input OR gate. In total, there would be 11 gates. However, in practice, 10-input OR gate is not implementable, hence we would need to use few OR gates of fewer inputs (for example instead we could use 2 5-input OR gates, and 1 2-input OR gate).
Figure 2: Circuit Implementation of Function f from Part b of Question 1
Question 2: CMOS Circuit Technology Design (10 marks)
Design a CMOS logic gate that implements the function: Y = A + BC + BD . On the schematics indicate which transistors belong to the pull-up and which to the pull-down network. !
Solution: Start with the logic circuit Y’ = A + BC + BD. This function can be immediately implemented using PDN (NMOS transistors), Figure 3.
Figure 3: PDN Network for Question 2 PMOS network is constructed by symmetrical reflection of NMOS Network, Figure 4.
Figure 4: CMOS Implementation of Y = (A+BC+BD)'
Question 3: VHDL (10 marks) Write a complete VHDL description of a circuit that implements the Boolean function y = x1 x2 + x1 x3 ! x3 x4 . Use simple assignment statements, each having no more than 2 signals on the right hand side.
Solution: entity Q3 is port(x1, x2, x3, x4 : in std_logic; y : out std_logic); end Q3; architecture A of Q3 is signal i1, i2, i3, i4 : std_logic; begin i1
