74dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma ... - Nima Maghari
IEEE 2008 Custom Intergrated Circuits Conference (CICC)
74dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35dB Opamp Gain Nima Maghari, Sunwoo Kwon and Un-Ku Moon School of EECS, Oregon State University, Corvallis, OR 97331 Abstract—In this paper a new multi-loop delta-sigma modulator is presented. This multi-loop modulator is insensitive to low gain opamps while maintaining the stability advantage. As a proof of concept, a prototype was implemented to show the functionality of this structure. Measurement results shows that with open-loop opamp gain of only 35dB, this prototype achieves over 74dB SNDR at oversampling ratio of 16. The sampling frequency is 20MHz and the total power dissipation is 3.2mW from a 1.2V power supply.
I. I NTRODUCTION Improvement in digital communication systems as well as popularity of portable systems has increased the demand for low-voltage low-power analog-to-digital converters (ADCs) over the past few years. Among various ADCs, delta-sigma modulators (DSMs) are well suited for low-to-medium bandwidth high-resolution conversion due to their noise shaping plus oversampling property. The oversampling nature of these ADCs will vastly reduce the capacitor size for low-speed high-accuracy application such as audio ADCs, and it will greatly relax the anti-aliasing filter requirements in medium speed applications. The drawback of the oversampled system is that the signal bandwidth is only a small fraction of the overall bandwidth. Consequently, to increase the signal bandwidth, higher sampling speed is required, which increases power dissipation. The alternative approach is to enhance the noise shaping property by increasing the order of the modulator. The two most commonly used delta-sigma modulator structures are the single loop high order modulator and the multistage noise shaping (MASH) structure. The single loop high order DSM can provide high signal-to-noise ratio (SNR) with relaxed circuit elements, but it is prone to instability. In high order modulators, the stable input range, which is defined by the maximum input signal range that leads to proper operation of the modulator, is limited. This range mostly depends on the number of levels used in the quantizer and the order of the modulator. On the other hand, the MASH structure can guarantee the stability by employing extra/cascaded ADCs or modulators to enhance its noise shaping property, but it requires high accuracy integrators to minimize the quantization error leakage resulting from the classic mismatch problem between the analog and the digital transfer functions [1]. This will become more challenging in submicron process due to the intrinsic gain reduction of transistors. Moreover, in low-voltage applications, high opamp gain requirement will often result in multi-stage opamps where both stability and
978-1-4244-2018-6/08/$25.00 ©2008 IEEE
power dissipation will be a dominant limiting factor of the overall performance. This work describes the IC implementation of the SturdyMASH (SMASH) modulator [2] to overcome the need of high opamp gain requirements and accurate modulator coefficients. It will be shown that similar performance of the MASH structures can be achieved by employing opamps with DC gain around 30dB. Low gain requirements will enable using simple opamps with large available output swing even in very low-voltage applications. This paper is organized as follows: In Section II, a brief review of SMASH modulator is presented followed by the system level architecture for this implementation. Section III gives details of the circuit implementation of the prototype ADC. Measurements results are provided in Section IV and finally conclusions are drawn in Section V. II. SMASH D ELTA -S IGMA M ODULATOR A general two-loop SMASH DSM is illustrated in Fig. 1, where LSi , LN i and Ei denote the signal loop filter, noise loop filter and quantization error of the ith stage, respectively. Unlike the traditional MASH structure where the output of the second loop is subtracted from the output of the first loop via digital filters (ST F2D and N T F1D ) outside the modulator loop, in this architecture the output of the second loop is subtracted from the first stage output inside the loop. In other words, the digital summing block is moved inside the first loop and all digital filters are eliminated. Writing down the signal transfer function (STF) and the noise transfer function (NTF) for the SMASH structure shown in Fig. 1 yields YSM ASH = ST F1 X+N T F1 (1−ST F2 )E1 −N T F1 N T F2 E2 . (1)
X
L S1(z)
LN1 (z)
E1
L S2 (z) LN2 (z)
E1 Q1
YSMASH
STF2D
YMASH
E2 Q2
NTF1D
Fig. 1. MASH (shown in gray) and SMASH (shown with the dashed line) structures.
7-4-1
101
z-1 -1
0.5z 1-z -1
X
shown with the dashed line in Fig. 1. This relaxes the matching requirements of the DACs in the second loop.
E1 -1
z 1-z -1
Q1
Y
III. C IRCUIT D ESIGN A. Operational Amplifiers
E2
0.5z -1 1-z-1
E1
Fig. 2.
2z-1 1-z-1
Q2
Implemented 2+2 SMASH modulator.
In order to achieve proper noise shaping for both of the quantization errors, i.e., E1 and E2 in a 2+2 SMASH structure, the second stage signal transfer function should satisfy ST F2 = 2z −1 − z −2 .
(2)
It is instructive to note that in the SMASH structure both quantization errors will be shaped by the order of the modulator while in the regular MASH structure, only the last quantization error will be shaped and all other quantization errors will be canceled out via digital filters. Theoretically, it is possible to cancel E1 in SMASH structure by choosing ST F2 = 1 [3]. However, this demands extracting E1 , feeding it to the second loop and finally subtracting it from the output of the first loop, all without any delay which is not feasible. For this design, the modulator shown in Fig. 2 was chosen. It can be seen that the second loop satisfies the criteria of (2). The first loop uses distributed signal feedforward topology to minimize the swing requirements of the integrators. The delay in the signal feedforward path is due to the non-zero delay of the quantizer and feedback path, and it will result in less than 0.1dB in-band peaking in signal transfer function. The modulator coefficients are chosen to minimize the output swing of integrators while maximizing their feedback factor. Although the second loop should have a specific signal transfer function, there are no specific constrains on the first loop signal and noise transfer functions. In this architecture, multi-bit quantizers are preferred to alleviate the swing requirements at the output of the integrators. To linearize the input digital-to-analog converter (DAC), dynamic element matching (DEM) should be used since any nonideality in this DAC will appear at the output of the modulator, unshaped. Depending on the number of quantization levels and the DEM technique employed, this operation might take up to a half of the clock period. To reduce the DEM complexity and eliminate the need of fast digital adder in the modulator loop, the digital adder inside the modulator is replaced with two additional DACs at the input of the first and second integrators and one digital adder outside both loops [4]. Later, it will be shown that the DAC associated with the second loop output at the input of the modulator will only have a negligible effect on total noise and power contributions. It is worth noting that any error in the second loop will be multiplied by the first loop NTF because the output of the second loop is effectively fed to the output of the first loop,
Due to the fact that no digital filters are used in this topology, the analog transfer function accuracy requirements are relaxed, enabling to use low gain opamps. Matlab simulations shows that 28dB opamp gain is sufficient to provide over 80dB signal-to-quantization noise-ratio (SQNR). To add a safety margin for effective gain degradation due to the feedback factor [5] and also process and temperature variations, opamps with 35dB open loop gain (based on transistor level simulations) are designed. Shown in Fig. 3, simple opamps with NMOS cascode transistors are chosen to satisfy the required gain with large available output swing. In contrast to MASH structure where high gain opamps often result in two-stage or gain boosted topologies with increased power dissipation, in SMASH architecture a single stage opamp with no additional gain boosting techniques allows low-power operation and results in a simpler design. Continuous-time common-mode feedback is used to set the output commonmode of the opamps to the desired value. B. Quantizers 3-bit quantizers are used for this implementation. This will ensure the modulator stability even for the input signals close to the full-scale range. Multi-bit quantizers will also reduce both the in-band and the out-of-band quantization noise, resulting in improved SQNR. A switched-capacitor (SC) summer is used in front of each pre-amplifier to add the input signal, output of the second integrator and the reference voltages as demonstrated in Fig. 4. It is critically important to reset the pre-amplifier in order to minimize any memory effects from gate-drain capacitance of the input transistors [6]. To eliminate this effect, the input transistor is reset in every period. The operation of this circuit is as follows: In φ1 , the input signal is sampled on CQ1 while the comparator offset is sampled on CQ2 and the gate-drain capacitance of the input transistor is discharged. In the next phase, the output of the
7-4-2
VDD
Vo−
R
R
Vo+
Vb2 Vcmo
Vin+
Vin−
Vb1
opamp
Fig. 3.
CMFB
Opamp used for integrators.
102
VDD DA1
ϕ1
ϕ1
ϕ2 ref(i)
ϕ2 CQ2 Vint2+
ϕ1
ref ref +
8x
CDA1
DA1
ϕ1d
X
ϕ1
Vbias
Vcm
Fig. 4.
DAC A SC Network
X
Complementary
ϕ1 CQ1
ϕ 2d
ϕ2 4x
Passive summer in front of the pre-amplifier.
CS
ref + ref -
CDB1
DB1
second integrator is connected to CQ2 while CQ1 provides the reference voltage generated from the resistor ladder. At the falling edge of φ2 , the comparator latches the data of the pre-amplifier (latches are not shown for simplicity). The same structure is used for the second loop. However, the output of the second loop will not utilize the full dynamic range of its quantizer due to the fact that the input of the second loop is only the quantization error of the first stage. Therefore, extra comparators are removed. This will reduce the complexity of the DAC associated with the second loop output at the input of the modulator by removing the extra capacitors, minimizing the impact of this DAC to the overall noise and power contributions. C. Error Extraction It is vital to extract the quantization error of the first loop accurately enough to be contained within the overall noise budget. This is due to the fact that any error in this extraction will be only shaped by the first loop. Since no active adder was used in front of the quantizer, this error cannot be extracted in conventional way (e.g., by subtracting the input of the quantizer from its output). In this architecture, error extraction is done at the input of the second loop using output of the first quantizer (Q1 out ), input signal (X) and the second integrator output (Vint2 ). In other words, the first stage quantization error is equal to E 1 = Q1
out
− Vint2 − z −1 X.
(3)
z -1
E1 -1
z 1-z -1
Q1
Y
Q 1_ out
Vint 2
0.5z -1 1-z-1 Fig. 5.
Extraction of the first loop quantization error.
ϕ 2d
Fig. 6. Input of the modulator. DACB uses half as many elements of DACA (single-ended shown for simplicity).
be seen that the signal fed to the second loop is the advanced version of the signal fed to the first quantizer. This will only result in a small signal component in the second loop and it will not affect the noise shaping property. In this prototype, all the summations are done at the inputs of the third and fourth integrators to eliminate the need of an extra active element. D. Input Switches and DACs To avoid signal dependent loading on the references of the DACs, the sampling capacitors at the input of the modulator and the input DACs are separated. This is shown in Fig. 6 where DACA and DACB denote the DACs associated with the first loop and second loop outputs at the input of the modulator, respectively. A 1pF sampling capacitor for the input signal, total of 1pF capacitor for DACA and a total of 0.5pF capacitor for DACB are used. The actual design uses fully-differential implementation. Data weighed averaging (DWA) is used to linearize the input DACs of the modulator. First loop uses a 3-bit DWA and the second loop employs a 2-bit DWA. Both DACs work in φ2 leaving sufficient time for DEM operation to take place. Bootstrap switches presented in [7] are used for sampling the input signal to guarantee the linearity of the sampled signal. The bootstrap switch is circled with the dashed line in Fig. 6.
A conceptual block diagram is depicted in Fig. 5 where only second and third integrators are shown for simplicity. It can
X
ϕ2
ϕ1 DB1
DACB
CI
ϕ2d
IV. M EASUREMENT R ESULTS The prototype ADC was fabricated in a 0.18μm 2-Poly 5-Metal CMOS process. Fig. 7 shows the die photograph of the prototype IC. The active area is 1.6 x 1.2 mm2 . Fig. 8 shows a 32k-sample measured output spectra with 92kHz -6dB fullscale (FS) sine-wave input signal. The 3rd and 5th harmonics are at -98dB and -94dB, respectively. The noise floor is at -105dB within the signal band. The same opamp gain using MASH topology would result in severe performance degradation. Fig. 9 illustrates the measured SNR and SNDR of the prototype chip as a function of the input signal power. The maximum measured dynamic range, SNR and SNDR are 76.9dB, 75.6dB and 74.6dB, respectively.
7-4-3
103
TABLE I P ERFORMANCE S UMMARY
Fig. 7.
−20
Die photograph
Fin=92 kHz Ain= −6 dBFS
PSD (dB)
1.2V 20MHz
Oversampling Ratio
16
Dynamic Range
76.9dB
SNR
75.6dB
SNDR
74.6dB
Power Dissipation
2.1mW Analog 1.1mW Digital
Technology
0.18μm 2P5M CMOS
Active Area
1.92 mm2
quantizers and the resistor ladders. Further power optimization is possible in both digital and analog parts; however, this prototype ADC was primarily intended to demonstrate the feasibility of SMASH modulators.
SNDR=70.6 dB
−40 −60
V. C ONCLUSION
−80
A fourth order SMASH modulator prototype IC implementation details and results were presented in this paper. It was shown that even with using very low gain opamps the obtained performance is comparable with that of the MASH structure utilizing costly high gain opamps. This major advantage over traditional multi-loop architectures not only allows low-voltage operation, but it will also result in lower power dissipation. The passive switched-capacitor summer and error extraction, together with the unique modulator topology, enables processing large input signals with robust stability.
−100 −120 −140 3
4
10
5
6
10 10 Frequency (Hz)
Fig. 8.
10
Measured output spectrum.
SNDR SNR
70
ACKNOWLEDGMENT The authors would like to thank National Semiconductor for providing fabrication of the prototype IC and also R. Gregoire and P. Kurahashi for their useful comments. This work was supported by Semiconductor Research Corporation (SRC) under contract 2005-HJ-1308.
60
SNR, SNDR (dB)
Supply Voltage Sampling Frequency
50 40 74.6
30
R EFERENCES
20 10 −1.5 −70
Fig. 9.
−60
−50
−40 −30 Input Power(dBFS)
−20
−10
0
SNR and SNDR versus input power.
This prototype was tested at 1.2V analog and digital power supplies. Because a passive adder is used in front of the quantizer, input signals close to the full-scale voltage (FS=1.2V) can be processed by the modulator. In this design, the minimum power supply voltage was limited by the digital power supply. Analog power supply can be further reduced down to 1V with minimal degradation. Table I summarizes the measured performance of the prototype ADC. The total power dissipated in analog part is 2.1mW where 1.2mW of this power is dissipated in the opamps and the rest is dissipated in the
[1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, 2005, pp. 127-136. [2] N. Maghari, S. Kwon, G. C. Temes, and U. Moon, “Sturdy-MASH Δ-Σ Modulator” Electron. Lett., vol. 42, pp. 1269-1270, Oct. 2006. [3] P. Benabes, A. Gauthier, and R. Kielbasa, “New High-Order Universal Σ-Δ Modulators,” Electron. Lett., vol. 31, pp. 8-9, Jan. 1995. [4] S. Kwon and F. Maloberti, “A 14mW Multi-bit Δ-Σ Modulator with 82dB SNR and 86dB DR for ADSL2+,” ISSCC Dig. Tech. Papers, pp. 68-69, Feb. 2006. [5] Y. Geerts, M. S. .J. Steyaert, and W. Sansen, “A High Performance multibit ΔΣ CMOS ADC,” IEEE J. Solid-State Circuits, vol 35, No. 12, pp. 1829-1840, Dec. 2000. [6] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, “A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm Digital CMOS,” IEEE J. Solid-State Circuits, vol 40, No. 7, pp. 1499-1505, July 2005. [7] M. Dessouky, and M. Kaiser, “Very low-voltage digital-audio Δ-Σ modulator with 88-dB dynamic range using local switch bootstrapping,” IEEE J. Solid-State Circuits, vol 36, No. 3, pp. 349-355, Mar. 2001.
7-4-4
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74dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35dB Opamp Gain Nima Maghari, Sunwoo Kwon and Un-Ku Moon School of EECS, Oregon State University, Corvallis, OR 97331 Abstract—In this paper a new multi-loop delta-sigma modulator is presented. This multi-loop modulator is insensitive to low gain opamps while maintaining the stability advantage. As a proof of concept, a prototype was implemented to show the functionality of this structure. Measurement results shows that with open-loop opamp gain of only 35dB, this prototype achieves over 74dB SNDR at oversampling ratio of 16. The sampling frequency is 20MHz and the total power dissipation is 3.2mW from a 1.2V power supply.
I. I NTRODUCTION Improvement in digital communication systems as well as popularity of portable systems has increased the demand for low-voltage low-power analog-to-digital converters (ADCs) over the past few years. Among various ADCs, delta-sigma modulators (DSMs) are well suited for low-to-medium bandwidth high-resolution conversion due to their noise shaping plus oversampling property. The oversampling nature of these ADCs will vastly reduce the capacitor size for low-speed high-accuracy application such as audio ADCs, and it will greatly relax the anti-aliasing filter requirements in medium speed applications. The drawback of the oversampled system is that the signal bandwidth is only a small fraction of the overall bandwidth. Consequently, to increase the signal bandwidth, higher sampling speed is required, which increases power dissipation. The alternative approach is to enhance the noise shaping property by increasing the order of the modulator. The two most commonly used delta-sigma modulator structures are the single loop high order modulator and the multistage noise shaping (MASH) structure. The single loop high order DSM can provide high signal-to-noise ratio (SNR) with relaxed circuit elements, but it is prone to instability. In high order modulators, the stable input range, which is defined by the maximum input signal range that leads to proper operation of the modulator, is limited. This range mostly depends on the number of levels used in the quantizer and the order of the modulator. On the other hand, the MASH structure can guarantee the stability by employing extra/cascaded ADCs or modulators to enhance its noise shaping property, but it requires high accuracy integrators to minimize the quantization error leakage resulting from the classic mismatch problem between the analog and the digital transfer functions [1]. This will become more challenging in submicron process due to the intrinsic gain reduction of transistors. Moreover, in low-voltage applications, high opamp gain requirement will often result in multi-stage opamps where both stability and
978-1-4244-2018-6/08/$25.00 ©2008 IEEE
power dissipation will be a dominant limiting factor of the overall performance. This work describes the IC implementation of the SturdyMASH (SMASH) modulator [2] to overcome the need of high opamp gain requirements and accurate modulator coefficients. It will be shown that similar performance of the MASH structures can be achieved by employing opamps with DC gain around 30dB. Low gain requirements will enable using simple opamps with large available output swing even in very low-voltage applications. This paper is organized as follows: In Section II, a brief review of SMASH modulator is presented followed by the system level architecture for this implementation. Section III gives details of the circuit implementation of the prototype ADC. Measurements results are provided in Section IV and finally conclusions are drawn in Section V. II. SMASH D ELTA -S IGMA M ODULATOR A general two-loop SMASH DSM is illustrated in Fig. 1, where LSi , LN i and Ei denote the signal loop filter, noise loop filter and quantization error of the ith stage, respectively. Unlike the traditional MASH structure where the output of the second loop is subtracted from the output of the first loop via digital filters (ST F2D and N T F1D ) outside the modulator loop, in this architecture the output of the second loop is subtracted from the first stage output inside the loop. In other words, the digital summing block is moved inside the first loop and all digital filters are eliminated. Writing down the signal transfer function (STF) and the noise transfer function (NTF) for the SMASH structure shown in Fig. 1 yields YSM ASH = ST F1 X+N T F1 (1−ST F2 )E1 −N T F1 N T F2 E2 . (1)
X
L S1(z)
LN1 (z)
E1
L S2 (z) LN2 (z)
E1 Q1
YSMASH
STF2D
YMASH
E2 Q2
NTF1D
Fig. 1. MASH (shown in gray) and SMASH (shown with the dashed line) structures.
7-4-1
101
z-1 -1
0.5z 1-z -1
X
shown with the dashed line in Fig. 1. This relaxes the matching requirements of the DACs in the second loop.
E1 -1
z 1-z -1
Q1
Y
III. C IRCUIT D ESIGN A. Operational Amplifiers
E2
0.5z -1 1-z-1
E1
Fig. 2.
2z-1 1-z-1
Q2
Implemented 2+2 SMASH modulator.
In order to achieve proper noise shaping for both of the quantization errors, i.e., E1 and E2 in a 2+2 SMASH structure, the second stage signal transfer function should satisfy ST F2 = 2z −1 − z −2 .
(2)
It is instructive to note that in the SMASH structure both quantization errors will be shaped by the order of the modulator while in the regular MASH structure, only the last quantization error will be shaped and all other quantization errors will be canceled out via digital filters. Theoretically, it is possible to cancel E1 in SMASH structure by choosing ST F2 = 1 [3]. However, this demands extracting E1 , feeding it to the second loop and finally subtracting it from the output of the first loop, all without any delay which is not feasible. For this design, the modulator shown in Fig. 2 was chosen. It can be seen that the second loop satisfies the criteria of (2). The first loop uses distributed signal feedforward topology to minimize the swing requirements of the integrators. The delay in the signal feedforward path is due to the non-zero delay of the quantizer and feedback path, and it will result in less than 0.1dB in-band peaking in signal transfer function. The modulator coefficients are chosen to minimize the output swing of integrators while maximizing their feedback factor. Although the second loop should have a specific signal transfer function, there are no specific constrains on the first loop signal and noise transfer functions. In this architecture, multi-bit quantizers are preferred to alleviate the swing requirements at the output of the integrators. To linearize the input digital-to-analog converter (DAC), dynamic element matching (DEM) should be used since any nonideality in this DAC will appear at the output of the modulator, unshaped. Depending on the number of quantization levels and the DEM technique employed, this operation might take up to a half of the clock period. To reduce the DEM complexity and eliminate the need of fast digital adder in the modulator loop, the digital adder inside the modulator is replaced with two additional DACs at the input of the first and second integrators and one digital adder outside both loops [4]. Later, it will be shown that the DAC associated with the second loop output at the input of the modulator will only have a negligible effect on total noise and power contributions. It is worth noting that any error in the second loop will be multiplied by the first loop NTF because the output of the second loop is effectively fed to the output of the first loop,
Due to the fact that no digital filters are used in this topology, the analog transfer function accuracy requirements are relaxed, enabling to use low gain opamps. Matlab simulations shows that 28dB opamp gain is sufficient to provide over 80dB signal-to-quantization noise-ratio (SQNR). To add a safety margin for effective gain degradation due to the feedback factor [5] and also process and temperature variations, opamps with 35dB open loop gain (based on transistor level simulations) are designed. Shown in Fig. 3, simple opamps with NMOS cascode transistors are chosen to satisfy the required gain with large available output swing. In contrast to MASH structure where high gain opamps often result in two-stage or gain boosted topologies with increased power dissipation, in SMASH architecture a single stage opamp with no additional gain boosting techniques allows low-power operation and results in a simpler design. Continuous-time common-mode feedback is used to set the output commonmode of the opamps to the desired value. B. Quantizers 3-bit quantizers are used for this implementation. This will ensure the modulator stability even for the input signals close to the full-scale range. Multi-bit quantizers will also reduce both the in-band and the out-of-band quantization noise, resulting in improved SQNR. A switched-capacitor (SC) summer is used in front of each pre-amplifier to add the input signal, output of the second integrator and the reference voltages as demonstrated in Fig. 4. It is critically important to reset the pre-amplifier in order to minimize any memory effects from gate-drain capacitance of the input transistors [6]. To eliminate this effect, the input transistor is reset in every period. The operation of this circuit is as follows: In φ1 , the input signal is sampled on CQ1 while the comparator offset is sampled on CQ2 and the gate-drain capacitance of the input transistor is discharged. In the next phase, the output of the
7-4-2
VDD
Vo−
R
R
Vo+
Vb2 Vcmo
Vin+
Vin−
Vb1
opamp
Fig. 3.
CMFB
Opamp used for integrators.
102
VDD DA1
ϕ1
ϕ1
ϕ2 ref(i)
ϕ2 CQ2 Vint2+
ϕ1
ref ref +
8x
CDA1
DA1
ϕ1d
X
ϕ1
Vbias
Vcm
Fig. 4.
DAC A SC Network
X
Complementary
ϕ1 CQ1
ϕ 2d
ϕ2 4x
Passive summer in front of the pre-amplifier.
CS
ref + ref -
CDB1
DB1
second integrator is connected to CQ2 while CQ1 provides the reference voltage generated from the resistor ladder. At the falling edge of φ2 , the comparator latches the data of the pre-amplifier (latches are not shown for simplicity). The same structure is used for the second loop. However, the output of the second loop will not utilize the full dynamic range of its quantizer due to the fact that the input of the second loop is only the quantization error of the first stage. Therefore, extra comparators are removed. This will reduce the complexity of the DAC associated with the second loop output at the input of the modulator by removing the extra capacitors, minimizing the impact of this DAC to the overall noise and power contributions. C. Error Extraction It is vital to extract the quantization error of the first loop accurately enough to be contained within the overall noise budget. This is due to the fact that any error in this extraction will be only shaped by the first loop. Since no active adder was used in front of the quantizer, this error cannot be extracted in conventional way (e.g., by subtracting the input of the quantizer from its output). In this architecture, error extraction is done at the input of the second loop using output of the first quantizer (Q1 out ), input signal (X) and the second integrator output (Vint2 ). In other words, the first stage quantization error is equal to E 1 = Q1
out
− Vint2 − z −1 X.
(3)
z -1
E1 -1
z 1-z -1
Q1
Y
Q 1_ out
Vint 2
0.5z -1 1-z-1 Fig. 5.
Extraction of the first loop quantization error.
ϕ 2d
Fig. 6. Input of the modulator. DACB uses half as many elements of DACA (single-ended shown for simplicity).
be seen that the signal fed to the second loop is the advanced version of the signal fed to the first quantizer. This will only result in a small signal component in the second loop and it will not affect the noise shaping property. In this prototype, all the summations are done at the inputs of the third and fourth integrators to eliminate the need of an extra active element. D. Input Switches and DACs To avoid signal dependent loading on the references of the DACs, the sampling capacitors at the input of the modulator and the input DACs are separated. This is shown in Fig. 6 where DACA and DACB denote the DACs associated with the first loop and second loop outputs at the input of the modulator, respectively. A 1pF sampling capacitor for the input signal, total of 1pF capacitor for DACA and a total of 0.5pF capacitor for DACB are used. The actual design uses fully-differential implementation. Data weighed averaging (DWA) is used to linearize the input DACs of the modulator. First loop uses a 3-bit DWA and the second loop employs a 2-bit DWA. Both DACs work in φ2 leaving sufficient time for DEM operation to take place. Bootstrap switches presented in [7] are used for sampling the input signal to guarantee the linearity of the sampled signal. The bootstrap switch is circled with the dashed line in Fig. 6.
A conceptual block diagram is depicted in Fig. 5 where only second and third integrators are shown for simplicity. It can
X
ϕ2
ϕ1 DB1
DACB
CI
ϕ2d
IV. M EASUREMENT R ESULTS The prototype ADC was fabricated in a 0.18μm 2-Poly 5-Metal CMOS process. Fig. 7 shows the die photograph of the prototype IC. The active area is 1.6 x 1.2 mm2 . Fig. 8 shows a 32k-sample measured output spectra with 92kHz -6dB fullscale (FS) sine-wave input signal. The 3rd and 5th harmonics are at -98dB and -94dB, respectively. The noise floor is at -105dB within the signal band. The same opamp gain using MASH topology would result in severe performance degradation. Fig. 9 illustrates the measured SNR and SNDR of the prototype chip as a function of the input signal power. The maximum measured dynamic range, SNR and SNDR are 76.9dB, 75.6dB and 74.6dB, respectively.
7-4-3
103
TABLE I P ERFORMANCE S UMMARY
Fig. 7.
−20
Die photograph
Fin=92 kHz Ain= −6 dBFS
PSD (dB)
1.2V 20MHz
Oversampling Ratio
16
Dynamic Range
76.9dB
SNR
75.6dB
SNDR
74.6dB
Power Dissipation
2.1mW Analog 1.1mW Digital
Technology
0.18μm 2P5M CMOS
Active Area
1.92 mm2
quantizers and the resistor ladders. Further power optimization is possible in both digital and analog parts; however, this prototype ADC was primarily intended to demonstrate the feasibility of SMASH modulators.
SNDR=70.6 dB
−40 −60
V. C ONCLUSION
−80
A fourth order SMASH modulator prototype IC implementation details and results were presented in this paper. It was shown that even with using very low gain opamps the obtained performance is comparable with that of the MASH structure utilizing costly high gain opamps. This major advantage over traditional multi-loop architectures not only allows low-voltage operation, but it will also result in lower power dissipation. The passive switched-capacitor summer and error extraction, together with the unique modulator topology, enables processing large input signals with robust stability.
−100 −120 −140 3
4
10
5
6
10 10 Frequency (Hz)
Fig. 8.
10
Measured output spectrum.
SNDR SNR
70
ACKNOWLEDGMENT The authors would like to thank National Semiconductor for providing fabrication of the prototype IC and also R. Gregoire and P. Kurahashi for their useful comments. This work was supported by Semiconductor Research Corporation (SRC) under contract 2005-HJ-1308.
60
SNR, SNDR (dB)
Supply Voltage Sampling Frequency
50 40 74.6
30
R EFERENCES
20 10 −1.5 −70
Fig. 9.
−60
−50
−40 −30 Input Power(dBFS)
−20
−10
0
SNR and SNDR versus input power.
This prototype was tested at 1.2V analog and digital power supplies. Because a passive adder is used in front of the quantizer, input signals close to the full-scale voltage (FS=1.2V) can be processed by the modulator. In this design, the minimum power supply voltage was limited by the digital power supply. Analog power supply can be further reduced down to 1V with minimal degradation. Table I summarizes the measured performance of the prototype ADC. The total power dissipated in analog part is 2.1mW where 1.2mW of this power is dissipated in the opamps and the rest is dissipated in the
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