Precise Area-Controlled Return-to-Zero Current ... - Nima Maghari
Precise Area-Controlled Return-to-Zero Current Steering DAC with Reduced Sensitivity to Clock Jitter Nima Maghari and Un-Ku Moon Electrical Engineering and Computer Science Oregon State University, Corvallis, Oregon Abstract—A precise return-to-zero current steering DAC is presented. This architecture uses a scaled switched-capacitor replica and a comparator to integrate the current over time, resulting in an accurate pulse. Without significant increase in the pulse height, the generated pulse can have its minimal value at the end of the DAC phase, hence minimizing the clock jitter effect. The proposed DAC can be used in continuous-time deltasigma modulators to achieve high accuracy even in presence of the clock jitter. Simulation results are provided to prove the efficiency of this structure.
I.
INTRODUCTION
Over the past decades the digital systems has been widely used in many systems such as wireless communications systems, portable media, handheld devices and etc. In many of these systems, the interface between the purely digital system and the real world relies on data converters. The increase in the speed and the bandwidth of these digital systems demands the same advances in the data converters. All these should be with one stringent criterion: reducing the cost and area. Among various types of converters, the digital-to-analog converters (DACs) are extremely important since not only they are used in the digital to analog conversions, but also in many high accuracy analog-to-digital converters (ADCs) such as pipelined ADCs and delta-sigma modulators (both ADCs and DACs). For many years, designers preferred discrete-time (DT) switched-capacitor (SC) based DACs over its continuous-time (CT) counterpart especially in high resolution applications due to their reduced clock jitter sensitivity. However, these SCDACs are often power hungry, requiring fast slewing and accurate settling. As the demand for portable systems with reduced power consumption increases, continuous-time DACs are becoming more popular. The higher the resolution, the less clock jitter is required. Some designs use an on-chip phaselocked loop (PLL) to generate such an accurate pulse [1] while some others use different techniques to reduce the sensitivity to the variations of this clock pulse [2][3]. This paper presents a new return-to-zero (RZ) current steering DAC suitable for high accuracy systems such as continuous-time delta-sigma modulators. The main idea is to minimize the current at the end of the DAC phase hence
minimizing the sensitivity to clock jitter. This operation is done without significant incensement of the DAC pulse height not to put extra burden on the opamp. A scaled SC replica is used to integrate the area of the generated current pulse and compare it with a desired reference. Unlike other SC replicas where a large capacitor and accurate opamp [2] or an accurate comparator was required to minimize the noise on the discharging phase [3], the proposed structure can employ a small capacitor and a lousy comparator to minimize the power without significant noise penalty. This paper is organized as follows. Sections II provides the background of the DACs in CT delta-sigma modulators and the effect of the clock jitter on different types of DACs. In section III, the proposed structure is presented which solves the previous shortcomings. In section IV, the performance of this DAC is simulated and shown how with minimizing the current at the end of the DAC phase the clock jitter sensitivity is reduced. II.
In any regular delta-sigma ADC, the final digital output is subtracted from the input signal to form the feedback operation. Since this subtraction is done at the frontend of the modulator, any error or nonlinearity in this subtraction is undistinguishable from the input signal and hence it will appear at the output without suppression. The simplified block diagram shown in the Fig. 1 demonstrates this concept, where EDAC represents the errors in the DAC. This subtraction, in most of the cases, is done either by a SC circuit or current steering DAC. In the SC-DACs, the charge is sampled on the DAC capacitors in one phase and it will be transferred into the integrating capacitor of the opamp in the next phase. If the switch RC time constant is much smaller than the clock period, this operation is independent of the clock jitter. In this type of DAC, the accuracy is solely limited to mismatch between the unit elements of the DAC. The main drawback of this approach is the fast slewing requirement of the opamp. For this, high tail current is needed in the opamp which leads in increased power consumption. The other disadvantage is the feedback factor degradation due to increased capacitance at the input of the opamp.
This work is supported by the Semiconductor Research Corporation.
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
DACS IN CONTINOUS-TIME DELTA-SIGMA MODULATORS
297
Fig. 1. A single-loop delta-sigma undistinguishable from the input signal.
modulator.
EDAC
is
Although the DAC capacitors can be shared with the input signal, it might result in signal dependent charging on the references, resulting in tones to appear at the output spectrum. The alternative approach is to use a current steering DAC. In this type of DAC, because the output will ramp to its final value during the DAC phase, the slewing requirement of the opamp is greatly relaxed, allowing low-power operation. The advantage of relaxed slewing of continuous-time DAC comes with a critical penalty: the clock jitter will directly modulate the DAC pulse-width, and appears as an added error in the final output of the modulator [4]. For a fixed area of the DAC pulse, the minimum error due to the clock jitter is the maximum pulse-width with the minimum amplitude, as illustrated in Fig. 2. In a non return-tozero (NRZ) DAC, the error caused by an individual DAC pulse due to the clock jitter follows
e j − NRZ (n) = Qout I DAC Δt j
(1)
where Qout is the quantizers output code (normalized to the reference), IDAC is the height of each individual DAC pulse and Δtj is the clocking uncertainty. The power spectral density of ej-NRZ is white and it has a variance of σej-NRZ2 2 2 σ e2j − NRZ = (Qout σ IDAC )σ t 2j
(2)
where σtj2 is the variance of the clock jitter and σIDAC2 represents the variance of the DAC pulse at the end of the DAC phase. This equation shows the simplest way to reduce the clock jitter effect is to reduce the IDAC height. This is made possible with NRZ-DAC due to the maximum width of a full clock period used by this pulse. In other words, for a fixed pulse area, one with minimum height and maximum width has the least clock jitter sensitivity. However, the NRZ operation comes with another penalty: the main issue with this type of NRZ-DAC is the inter-symbol interference (ISI) which will modulate the output depending on the output code transitions [5].
Fig. 2. Different DAC pulses: (a) non-return to zero (b) return to zero.
Fig. 3. Minimizing the DAC current at the falling edge of the DAC phase. The dotted line shows the equivalent RZ-DAC pulse.
On the other hand, the RZ-DAC pulse is ISI free, but since it uses a fraction of the clock period, it has larger height and it is more prone to the clock jitter. In this DAC type, both the rising edge and falling edge of the clock will affect its jitter performance
e j − RZ (n) = Qout I DAC D −1 (Δt j1 + Δt j 2 )
(3)
where D is the duty cycle of IDAC, Δtj1 and Δtj2 are the clocking uncertainty of the rising and falling edges, respectively. The variance of ej-RZ is given as 2 2 σ e 2j − NRZ = Qout σ IDAC D −2 (σ t 2j1 + σ t 2j 2 )
(4)
Depending on duty-cycle (D) of the DAC pulse, the performance of the RZ-DAC (D=50%) pulses can be up to 15dB worse than that of the NRZ-DAC pulses [6]. Several different approaches have been proposed to combat this high clock sensitivity in RZ-DACs. These approaches fall into two main categories: minimizing the current at the end of the DAC phase [7] or create a precisearea pulse to operate the DAC [3]. The main issue with the first approach is the increased current in the starting of the DAC phase to enable minimizing it at the end of this phase. Also, it is difficult to maintain the desired area since the DAC pulse shape might be unpredictable, as shown in Fig. 3. The second approach requires an accurate comparator and a large capacitor to achieve the required resolution. The next section describes a new approach which not only minimizes the DAC current at the end of the clock phase, but also generates a precise area-controlled pulse. III.
PROPOSED PAC-DAC
The main concept of the proposed idea is to generate a precise area-controlled pulse (PAC) independent of the pulse shape. In other words, the goal is to create a pulse with its minimum value at the end of the sampling phase while keeping the area under the pulse fixed. In this way, clock jitter will have its minimal effect. A fixed-area pulse is created via integrating a current on a capacitor, and detecting the reference crossing via a comparator [3]. A simple area detector is shown in Fig. 4. In φDAC the fixed current source IPAC will start to charge the capacitor C till Vx crosses Vref. The final DAC pulse is the area between the rising edge of φDAC and the falling edge of Vpulse, shown with φPAC in Fig. 5. This pulse is then used to operate the main DAC at the input of the modulator. Hence, the jitter due to the rising edge of φDAC will
298
The noise analysis of this structure has been explored in literature focusing on comparator-based ADCs [8][9]. The comparator noise affects when Vx is crossing the reference voltage and it will translate to timing jitter in the rising edge of Vpulse, hence altering the overall accuracy. The noise of the charging current will only affect the output after preamplifier threshold is crossed. The added noise before this instance only changes the pulse-width. The noise contribution of this current consists of the random walk deviation on the capacitor during two independent time intervals. First, is the preamp response time (ti) and second is the delay time from the threshold detection to the sampling switch opening tc=td-ti where td is the delay of the comparator. The input referred final noise due to the shot noise of the current source is
⎛ qI PAC v ≈⎜ ⎜ ( C + C )2 X ⎝ L 2 n
⎞ ⎟ (α ti + t c ) ⎟ ⎠
(5)
where α shows the correlation factor between the randomwalk noise and the crossing detection and CX is the total parasitic capacitance at node Vx.
ϕ DAC
ϕ reset
Fig. 4. A basic area-controlled pulse is achieved by integrating a fixed current on a capacitor.
ϕ DAC
ϕ PAC
Fig. 5. Timing diagram of the PAC operation.
ϕ reset
D
D ϕ Dis ϕ DAC
ϕ reset
ϕ DAC
not affect the performance of the DAC and it will only change the time it takes to reach Vref. Also, the fixed comparator delay is not an issue since the operation of this circuit is periodic, and the comparator decision level and input remains constant, resulting in a fixed offset. However, the falling edge of the generated pulse which is decided by the comparator is affected by two main sources of noise; the current source noise (IPAC) and the comparator noise.
ϕ reset
ϕ Dis
Fig. 6. The proposed PAC-DAC structure. A discharging current will lower the gate voltage of the bias current hence minimizing it.
Unlike regular comparator-based circuit, in this case replicas of the current sources are used to form each DAC unit element (in multi-bit DACs), which will result in uncorrelated randomwalk effect on zero crossing detection of the area-controlling branch, hence α=1. Equation (5) clearly shows that the most effective way to reduce this noise (without modifying the comparator) is to reduce the current IPAC or increase the capacitor size. Note that increasing CL will not only increase the power consumption, but also demands higher current which leads to increased power consumption. However, since the jitter will only affect the current at the falling edge of the DAC phase, it is most efficient to minimize the current only at that instance. The proposed structure is shown in Fig. 6. The transistor Mc1 and Mb1 form a single unit-element current source for the DAC. The rest of the unit elements are a mirrored copy of this unit cell and are not shown for simplicity. Transistors Mc2 and Mb2 form a replica and are used to create the PAC pulse. The drain current of Mc1 will go to the virtual ground node of the opamp (not shown) and subtracts/adds its value. The same current passes through Mc2 and starts to pull down the node voltage Vx until it falls below Vref. At that point, the discharging operation will be terminated. So far, this operation was exactly similar to that of Fig. 4. However, the main difference here is, the currents (I1 and IPAC) are not fixed during the whole period. At the reset phase, a bias voltage (Vb) charges the bias capacitor (Cb) and the gate-source parasitic capacitance of the current sources (Cp). In the DAC phase, this bias voltage is disconnected and the current sources are connected via ϕ DAC switch. This will result in a fixed current in each DAC unit element (IPAC, I1 and its replicas). However, before the end of the DAC phase, φDis will go high and Idis will start to discharge the gate capacitors. Following this, the current in the DAC unit elements will start to subside. This operation continuous until the area under the pulse is equal to desired reference, and
299
then it will be terminated. An example of the timing diagram of the proposed DAC is shown in Fig. 7. The operation is similar to the one in Fig. 6 till the φDis phase. At this instance, IPAC will start to decrease and hence, Vx will ramp up slower. However, a majority of the energy (area) of the pulse is transferred before this point, hence the time required to reach t2 is not an important issue (ttrans). In this figure, a fixed current is used for Idis, however, different current sources can be used to obtain desired jitter performance. Note that with fixed current discharging gate capacitance, the IPAC will drop in quadratic form.
Volts
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0
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2.07
2.08
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x 10
It is evident from this figure that the current at the cut-off instance is less than 5uA, drastically lower than the regular RZ or even NRZ DACs. Since the rms power of the jitter noise is directly proportional with the current at the cut-off instance, the proposed circuit can improve jitter induced SNDR significantly (20dB in this case).
Vpulse
t t
Fig. 7. The timing diagram of the proposed PAC-DAC.
Same as before, the effect of the jitter resulting from comparator uncertainty will only affect the cutting off current at t2. However, with proper adjustment of Vb, this current can be significantly smaller than then IPAC DC value. Hence, the effect of the jitter can be minimized and the comparator requirements will be relaxed. Also, the shot noise from the current source (5) is reduced by the same amount. Furthermore, unlike SRC technique, this circuit does not exhibit a high peak current to compensate for its minimal current at the end of the phase, hence the bandwidth requirement of the opamp is alleviated. IV.
2.03
Fig. 8. Simulated DAC pulse. The current drops down to less than 5uA at the cutting instance. t
ϕ Dis
t2
2.02
Time(s)
t
t1
2.01
-7
0
ϕ PAC
2
x 10
ttrans
ϕ DAC
PAC
0.5
Vref IPAC
Φ
1
REFERENCES [1]
[2]
[3]
[4]
[5]
SIMULATION RESULTS
The circuit shown in Fig. 7. was simulated in a 0.18um CMOS process using Cadence. The operating frequency was 125MHz with 1.5V power supply. The unit capacitor was chosen to be 500fF (C1). To subtract Vdd/2 from this capacitor via a NRZ current-steering DAC, a fixed current of 47uA is needed. Using a traditional RZ DAC with 80% duty cycle, this current is increased to 59uA. The effect of the clock jitter on both of these cases can be from calculated (2) and (4). For the discharging phase of the proposed circuit, a single NMOS transistor operating in linear region was used for simplicity. Fig.9. shows the simulated waveforms. The DC current of the proposed technique is 69uA (equal to RZ with 70% duty cycle).
[6]
[7]
[8]
[9]
300
G. Mittergger et al., “A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHZ Signal Bandwidth and 12b ENOB," in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 62-63. S. Kwon et al., “An 11mW 100MHz 16X-OSR 64dB-SNDR Hybrid CT/DT ΔΣ ADC with relaxed DEM Timing”, in Proc. IEEE custom integrated circ. Design, CICC 2009, pp. 171-174. K. Nguyen, R. Adams, K. Sweetland, andH. Chen, “A 106dB SNR Hybrid Oversampling Analog-to-Digital Converter for Digital Audio,” IEEE J. Solid-State Circuits, vol. 40, No 12, pp. 2408-2415, Dec. 2005. K. Reddy and S. Pavan, “Fundamental Limitations of Continuous Time Delta-Sigma Modulators Due to Clock Jitter,” IEEE Trans. On Circ. and Syst. I, Vol. 54, No. 10, pp 2184-2194, OCT 2007. Shouli Yan and E. Sanchez-Sinencio, “A Continuous -Time ΔΣ Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth”, IEEE J. Solid-State Circuits, vol. 39, No 1, pp. 75-86, Jan. 2004. Z. Li and Terri S. Fiez, “A 14 Bit Continuous -Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth,” IEEE J. Solid-State Circuits, vol. 9, No 9, pp. 1873-1883, Sep. 2007. M. Ortmanns, F. Gerfers, and Y. Manoli, “A Continuous-Time ΔΣ Modulator with Reduced Sensitivity to Clock Jitter Through SCR Feedback,” IEEE Trans. On Circ. and Syst. I, Vol. 52, No. 5, pp 875884, May 2005. J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Solini, and H. S. Lee, “Comparator-bsaed switched-capacitor circuits for scaled CMOS technologies,” IEEE J. Solid-State Circuits, vol. 41, No 12, pp. 26582668, Dec. 2006. T. Sepke, . Holloway, C. G. Solini, and H. S. Lee, ”Noise analysis for comparator-based circuits,” ,” IEEE Trans. On Circ. and Syst. I, Vol. 56, No. 3, pp 541-553, Mar. 2009.
I.
INTRODUCTION
Over the past decades the digital systems has been widely used in many systems such as wireless communications systems, portable media, handheld devices and etc. In many of these systems, the interface between the purely digital system and the real world relies on data converters. The increase in the speed and the bandwidth of these digital systems demands the same advances in the data converters. All these should be with one stringent criterion: reducing the cost and area. Among various types of converters, the digital-to-analog converters (DACs) are extremely important since not only they are used in the digital to analog conversions, but also in many high accuracy analog-to-digital converters (ADCs) such as pipelined ADCs and delta-sigma modulators (both ADCs and DACs). For many years, designers preferred discrete-time (DT) switched-capacitor (SC) based DACs over its continuous-time (CT) counterpart especially in high resolution applications due to their reduced clock jitter sensitivity. However, these SCDACs are often power hungry, requiring fast slewing and accurate settling. As the demand for portable systems with reduced power consumption increases, continuous-time DACs are becoming more popular. The higher the resolution, the less clock jitter is required. Some designs use an on-chip phaselocked loop (PLL) to generate such an accurate pulse [1] while some others use different techniques to reduce the sensitivity to the variations of this clock pulse [2][3]. This paper presents a new return-to-zero (RZ) current steering DAC suitable for high accuracy systems such as continuous-time delta-sigma modulators. The main idea is to minimize the current at the end of the DAC phase hence
minimizing the sensitivity to clock jitter. This operation is done without significant incensement of the DAC pulse height not to put extra burden on the opamp. A scaled SC replica is used to integrate the area of the generated current pulse and compare it with a desired reference. Unlike other SC replicas where a large capacitor and accurate opamp [2] or an accurate comparator was required to minimize the noise on the discharging phase [3], the proposed structure can employ a small capacitor and a lousy comparator to minimize the power without significant noise penalty. This paper is organized as follows. Sections II provides the background of the DACs in CT delta-sigma modulators and the effect of the clock jitter on different types of DACs. In section III, the proposed structure is presented which solves the previous shortcomings. In section IV, the performance of this DAC is simulated and shown how with minimizing the current at the end of the DAC phase the clock jitter sensitivity is reduced. II.
In any regular delta-sigma ADC, the final digital output is subtracted from the input signal to form the feedback operation. Since this subtraction is done at the frontend of the modulator, any error or nonlinearity in this subtraction is undistinguishable from the input signal and hence it will appear at the output without suppression. The simplified block diagram shown in the Fig. 1 demonstrates this concept, where EDAC represents the errors in the DAC. This subtraction, in most of the cases, is done either by a SC circuit or current steering DAC. In the SC-DACs, the charge is sampled on the DAC capacitors in one phase and it will be transferred into the integrating capacitor of the opamp in the next phase. If the switch RC time constant is much smaller than the clock period, this operation is independent of the clock jitter. In this type of DAC, the accuracy is solely limited to mismatch between the unit elements of the DAC. The main drawback of this approach is the fast slewing requirement of the opamp. For this, high tail current is needed in the opamp which leads in increased power consumption. The other disadvantage is the feedback factor degradation due to increased capacitance at the input of the opamp.
This work is supported by the Semiconductor Research Corporation.
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
DACS IN CONTINOUS-TIME DELTA-SIGMA MODULATORS
297
Fig. 1. A single-loop delta-sigma undistinguishable from the input signal.
modulator.
EDAC
is
Although the DAC capacitors can be shared with the input signal, it might result in signal dependent charging on the references, resulting in tones to appear at the output spectrum. The alternative approach is to use a current steering DAC. In this type of DAC, because the output will ramp to its final value during the DAC phase, the slewing requirement of the opamp is greatly relaxed, allowing low-power operation. The advantage of relaxed slewing of continuous-time DAC comes with a critical penalty: the clock jitter will directly modulate the DAC pulse-width, and appears as an added error in the final output of the modulator [4]. For a fixed area of the DAC pulse, the minimum error due to the clock jitter is the maximum pulse-width with the minimum amplitude, as illustrated in Fig. 2. In a non return-tozero (NRZ) DAC, the error caused by an individual DAC pulse due to the clock jitter follows
e j − NRZ (n) = Qout I DAC Δt j
(1)
where Qout is the quantizers output code (normalized to the reference), IDAC is the height of each individual DAC pulse and Δtj is the clocking uncertainty. The power spectral density of ej-NRZ is white and it has a variance of σej-NRZ2 2 2 σ e2j − NRZ = (Qout σ IDAC )σ t 2j
(2)
where σtj2 is the variance of the clock jitter and σIDAC2 represents the variance of the DAC pulse at the end of the DAC phase. This equation shows the simplest way to reduce the clock jitter effect is to reduce the IDAC height. This is made possible with NRZ-DAC due to the maximum width of a full clock period used by this pulse. In other words, for a fixed pulse area, one with minimum height and maximum width has the least clock jitter sensitivity. However, the NRZ operation comes with another penalty: the main issue with this type of NRZ-DAC is the inter-symbol interference (ISI) which will modulate the output depending on the output code transitions [5].
Fig. 2. Different DAC pulses: (a) non-return to zero (b) return to zero.
Fig. 3. Minimizing the DAC current at the falling edge of the DAC phase. The dotted line shows the equivalent RZ-DAC pulse.
On the other hand, the RZ-DAC pulse is ISI free, but since it uses a fraction of the clock period, it has larger height and it is more prone to the clock jitter. In this DAC type, both the rising edge and falling edge of the clock will affect its jitter performance
e j − RZ (n) = Qout I DAC D −1 (Δt j1 + Δt j 2 )
(3)
where D is the duty cycle of IDAC, Δtj1 and Δtj2 are the clocking uncertainty of the rising and falling edges, respectively. The variance of ej-RZ is given as 2 2 σ e 2j − NRZ = Qout σ IDAC D −2 (σ t 2j1 + σ t 2j 2 )
(4)
Depending on duty-cycle (D) of the DAC pulse, the performance of the RZ-DAC (D=50%) pulses can be up to 15dB worse than that of the NRZ-DAC pulses [6]. Several different approaches have been proposed to combat this high clock sensitivity in RZ-DACs. These approaches fall into two main categories: minimizing the current at the end of the DAC phase [7] or create a precisearea pulse to operate the DAC [3]. The main issue with the first approach is the increased current in the starting of the DAC phase to enable minimizing it at the end of this phase. Also, it is difficult to maintain the desired area since the DAC pulse shape might be unpredictable, as shown in Fig. 3. The second approach requires an accurate comparator and a large capacitor to achieve the required resolution. The next section describes a new approach which not only minimizes the DAC current at the end of the clock phase, but also generates a precise area-controlled pulse. III.
PROPOSED PAC-DAC
The main concept of the proposed idea is to generate a precise area-controlled pulse (PAC) independent of the pulse shape. In other words, the goal is to create a pulse with its minimum value at the end of the sampling phase while keeping the area under the pulse fixed. In this way, clock jitter will have its minimal effect. A fixed-area pulse is created via integrating a current on a capacitor, and detecting the reference crossing via a comparator [3]. A simple area detector is shown in Fig. 4. In φDAC the fixed current source IPAC will start to charge the capacitor C till Vx crosses Vref. The final DAC pulse is the area between the rising edge of φDAC and the falling edge of Vpulse, shown with φPAC in Fig. 5. This pulse is then used to operate the main DAC at the input of the modulator. Hence, the jitter due to the rising edge of φDAC will
298
The noise analysis of this structure has been explored in literature focusing on comparator-based ADCs [8][9]. The comparator noise affects when Vx is crossing the reference voltage and it will translate to timing jitter in the rising edge of Vpulse, hence altering the overall accuracy. The noise of the charging current will only affect the output after preamplifier threshold is crossed. The added noise before this instance only changes the pulse-width. The noise contribution of this current consists of the random walk deviation on the capacitor during two independent time intervals. First, is the preamp response time (ti) and second is the delay time from the threshold detection to the sampling switch opening tc=td-ti where td is the delay of the comparator. The input referred final noise due to the shot noise of the current source is
⎛ qI PAC v ≈⎜ ⎜ ( C + C )2 X ⎝ L 2 n
⎞ ⎟ (α ti + t c ) ⎟ ⎠
(5)
where α shows the correlation factor between the randomwalk noise and the crossing detection and CX is the total parasitic capacitance at node Vx.
ϕ DAC
ϕ reset
Fig. 4. A basic area-controlled pulse is achieved by integrating a fixed current on a capacitor.
ϕ DAC
ϕ PAC
Fig. 5. Timing diagram of the PAC operation.
ϕ reset
D
D ϕ Dis ϕ DAC
ϕ reset
ϕ DAC
not affect the performance of the DAC and it will only change the time it takes to reach Vref. Also, the fixed comparator delay is not an issue since the operation of this circuit is periodic, and the comparator decision level and input remains constant, resulting in a fixed offset. However, the falling edge of the generated pulse which is decided by the comparator is affected by two main sources of noise; the current source noise (IPAC) and the comparator noise.
ϕ reset
ϕ Dis
Fig. 6. The proposed PAC-DAC structure. A discharging current will lower the gate voltage of the bias current hence minimizing it.
Unlike regular comparator-based circuit, in this case replicas of the current sources are used to form each DAC unit element (in multi-bit DACs), which will result in uncorrelated randomwalk effect on zero crossing detection of the area-controlling branch, hence α=1. Equation (5) clearly shows that the most effective way to reduce this noise (without modifying the comparator) is to reduce the current IPAC or increase the capacitor size. Note that increasing CL will not only increase the power consumption, but also demands higher current which leads to increased power consumption. However, since the jitter will only affect the current at the falling edge of the DAC phase, it is most efficient to minimize the current only at that instance. The proposed structure is shown in Fig. 6. The transistor Mc1 and Mb1 form a single unit-element current source for the DAC. The rest of the unit elements are a mirrored copy of this unit cell and are not shown for simplicity. Transistors Mc2 and Mb2 form a replica and are used to create the PAC pulse. The drain current of Mc1 will go to the virtual ground node of the opamp (not shown) and subtracts/adds its value. The same current passes through Mc2 and starts to pull down the node voltage Vx until it falls below Vref. At that point, the discharging operation will be terminated. So far, this operation was exactly similar to that of Fig. 4. However, the main difference here is, the currents (I1 and IPAC) are not fixed during the whole period. At the reset phase, a bias voltage (Vb) charges the bias capacitor (Cb) and the gate-source parasitic capacitance of the current sources (Cp). In the DAC phase, this bias voltage is disconnected and the current sources are connected via ϕ DAC switch. This will result in a fixed current in each DAC unit element (IPAC, I1 and its replicas). However, before the end of the DAC phase, φDis will go high and Idis will start to discharge the gate capacitors. Following this, the current in the DAC unit elements will start to subside. This operation continuous until the area under the pulse is equal to desired reference, and
299
then it will be terminated. An example of the timing diagram of the proposed DAC is shown in Fig. 7. The operation is similar to the one in Fig. 6 till the φDis phase. At this instance, IPAC will start to decrease and hence, Vx will ramp up slower. However, a majority of the energy (area) of the pulse is transferred before this point, hence the time required to reach t2 is not an important issue (ttrans). In this figure, a fixed current is used for Idis, however, different current sources can be used to obtain desired jitter performance. Note that with fixed current discharging gate capacitance, the IPAC will drop in quadratic form.
Volts
1.5
Vx
0
2.04
2.05
2.06
2.07
2.08
2.09
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DAC Current
uA
Current(uA)
100 69 50
5
0
2
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2.02
2.03
2.04
2.05
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2.07
2.08
2.09
2.1 -7
x 10
It is evident from this figure that the current at the cut-off instance is less than 5uA, drastically lower than the regular RZ or even NRZ DACs. Since the rms power of the jitter noise is directly proportional with the current at the cut-off instance, the proposed circuit can improve jitter induced SNDR significantly (20dB in this case).
Vpulse
t t
Fig. 7. The timing diagram of the proposed PAC-DAC.
Same as before, the effect of the jitter resulting from comparator uncertainty will only affect the cutting off current at t2. However, with proper adjustment of Vb, this current can be significantly smaller than then IPAC DC value. Hence, the effect of the jitter can be minimized and the comparator requirements will be relaxed. Also, the shot noise from the current source (5) is reduced by the same amount. Furthermore, unlike SRC technique, this circuit does not exhibit a high peak current to compensate for its minimal current at the end of the phase, hence the bandwidth requirement of the opamp is alleviated. IV.
2.03
Fig. 8. Simulated DAC pulse. The current drops down to less than 5uA at the cutting instance. t
ϕ Dis
t2
2.02
Time(s)
t
t1
2.01
-7
0
ϕ PAC
2
x 10
ttrans
ϕ DAC
PAC
0.5
Vref IPAC
Φ
1
REFERENCES [1]
[2]
[3]
[4]
[5]
SIMULATION RESULTS
The circuit shown in Fig. 7. was simulated in a 0.18um CMOS process using Cadence. The operating frequency was 125MHz with 1.5V power supply. The unit capacitor was chosen to be 500fF (C1). To subtract Vdd/2 from this capacitor via a NRZ current-steering DAC, a fixed current of 47uA is needed. Using a traditional RZ DAC with 80% duty cycle, this current is increased to 59uA. The effect of the clock jitter on both of these cases can be from calculated (2) and (4). For the discharging phase of the proposed circuit, a single NMOS transistor operating in linear region was used for simplicity. Fig.9. shows the simulated waveforms. The DC current of the proposed technique is 69uA (equal to RZ with 70% duty cycle).
[6]
[7]
[8]
[9]
300
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