a dynamic start-up circuit for low voltage cmos current ... - Nima Maghari
A Dynamic Start-Up Circuit for Low Voltage CMOS Current Mirrors with Power-Down Support Nima Maghari And Omid Shoaei dep. of Electrical & Computer Engineering University of Tehran Tehran, Iran [email protected] Abstract—In this paper, a dynamic start-up circuit for advanced bias circuits is presented. This start-up circuit supports both power-down and power-on-reset inputs for more stable functionality, satisfying the demand of low power dissipation in suspend mode. The dynamic operation of this circuit will minimize power dissipation especially when low power design is necessary. Complete analysis of this circuit is performed to help designers with device sizes and different effects of circuit parameters. HSPICE simulations are provided to show the proper functionality and validity of this circuit using 0.18-µm CMOS technology in 1.8 Volts.
I.
INTRODUCTION
Lowering power dissipation in analog and mixed signal ICs is much more desired nowadays to improve the battery life in many portable systems such as PDAs and mobile phones. This comes along with many difficulties such as lowering power supply voltage, suspending circuits in different phases of the system and other improvements that will force analog and mixed-mode IC designers to challenge with more complex circuits. As power supply voltage decrease year by year, the use of low supply voltage current mirrors becomes inevitable. These current mirrors are one of the most fundamental parts in any analog and mixed-mode ICs since they are often used to bias critical parts such as OTAs (Operational Transconductance Amplifiers), and the most important of all, in bandgap voltage reference. It is more desired in such circuits to achieve higher signal swing to improve SNR of the overall system. This also comes along with using low voltage structures, challenging with more complex circuits. Power dissipation in suspend mode is as much important as in normal operation mode, since in many portable systems the time period of suspend mode might be much longer than the time period of normal operation mode. As shown in Fig. 1, a simple current mirror is used to generate voltage or current. Capacitor CB consists of gatesource capacitance of PMOS devices and also other capacitors which is used to fix the gate source voltage of the PMOS transistors and avoid current variations according to power supply voltage variations. If all transistors carry a zero
0-7803-8834-8/05/$20.00 ©2005 IEEE.
current while the supply is turned on or it is rising from suspend mode, they may remain off indefinitely because the loop can support a zero current in both branches. To overcome this problem we can add a diode connected transistor (M5) to provide a current path from VDD through M4 and M1 to ground upon start-up. Thus, M3 and M1, and hence M2 and M4 cannot remain off [1]. This technique might be useful when dealing with non-low voltage structures while has several disadvantages such as current leakage and low allowable voltage swing. Another widely used current mirror is shown in Fig. 2 [2]. Such a wide swing current mirror not only helps us with voltage swing, but also minimizes most of the detrimental second-order imperfections caused by the finite-output impedance of transistors. Transistors MPD1 and MPD2 are added for supporting suspend mode. As PD1 goes high, the gate voltage of these transistors will become low, connecting their drain to VDD, making zero gate-source voltage and forcing transistors to operate in deep sub-threshold region, or completely off. This operation will cause CB1 and CB2 to lose their charge completely since both sides of these capacitances are connected to VDD. While PD is changing from high to low, there is a high risk of zero current loops which may occur, for there is no single diode connected transistor in the current path. Because of this reason, use of startup circuit is inevitable. So a technique is used in [2] for starting-up operation as will be discussed later.
Figure 1. A Simple bias circuit with diode connected device as a start-up. 1
Power-Down (sometimes called reset) pin is an input pin which forces the system to be suspended.
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Once the loop starts up, MS2 will come on, sinking all of the current from MS1, pulling the gates of MS3 and MS4 low, and thereby turning them off so they no longer affect the bias loop [2]. In the event that all currents in the bias loop are zero, MS2 will be off. Since MS1 operates as a highimpedance load that is always on, the gate of MS3 and MS4 will be pulled high. These transistors will then inject currents into the bias loop, which will startup the circuit. Based on this concept, several start-up circuits were used to ensure the stability of the bias circuit, and most of them hit the bandgap circuit, since its proper operation is vital for other bias circuits [3] [4]. These Mentioned start-up circuits work properly in most cases, but have two main disadvantages. First, they all consist of a single branch which is always on, dissipating power even in suspend mode. This fact becomes even more critical as for more complex structures we might need more than one regenerating point. And second, the parasitic effects of start-up transistors might affect the proper operation of the circuit. Leakage current out of the start-up circuit directly affects bias currents. These shortcomings become much more important while working with more accurate devices such as bandgap voltage reference [3]. This paper presents a new start-up circuit with dynamic operation compatible with any bias circuit, especially the bandgap voltage reference with wide variety of power supplies. In Section (II) this new start-up circuit will be presented and a complete analytical model of its operation is given. In section (III) some simulation results are presented to prove the proper functionality of this start-up circuit and section (IV) concludes this paper. II.
NEW START-UP CIRCUIT WITH DYNAMIC OPERATION
Almost all analog and mixed-mode ICs use power-down pin to force their operation to halt, and a large proportion of them use Power-On-Reset circuitry to start-up the chip for the first time it is connected to power supply. The idea is to use both power-on-reset and PD to generate a small pulse to be used for starting up the circuit as shown in Fig.3. Complete analytical model of this circuit will be presented later in this section. This start-up circuit is shown in Fig. 4. As mentioned before, the input of this circuit consists of two independent parts, power down and power-on-reset, to support both operation modes.
Figure 3. Top view of start-up system.
When power-down or power-on-reset is high, MS1 will be turned on; so both bottom and top plate of CS will be connected to ground, making it lose all of its charge. At falling edge of PD, top plate of CS will be connected to VDD; so it will force the bottom plate to raise near VDD voltage either, therefore VS will rise instantly after PD falls. Transistor MS2 will discharge the capacitor CS in a few nanoseconds and this operation will create a pulse on the gate of transistors MD1-Dn, so they will sink a current from PMOS bias capacitances, decreasing their gate voltage, hence turning them on. Assuming VS has risen to VDD voltage at the same time that PD falls, we can write:
I Discharge = I MS 2 =
KS 2 (VB − VTHN ) 2 2
(1)
( L) .
where K i = µ n COX W
i
This constant current will discharge CS until VS drops below Veff(MS2). It is worth to mention that if we choose Veff(MS2) > VTHN, MS2 will enter triode region before MDi is turned off, so nonlinear discharging of CS will occur which might increase the pulse width. So the best option is to choose Veff (MS2) VTHP
lowering its drain currant. This will make the discharge transistors MD1-Dn to operate in sub-threshold region, sinking a small amount of current from bias circuit, creating a small leakage current. But voltage of VS2 will fall far below VTHN in a short period of time, so this leakage will become truly negligible, almost in order of few Pico-amperes. It is worth to mention that in the equations (9), for simplicity we have assumed that VB is connected to power supply voltage and also VS2 will rise to power supply voltage, while this might not occur since the capacitor CS might loose a fraction of its charge during the falling time of PD signal when MS1 is not completely off. One can overcome this problem by using a high speed buffer in PD signal path. Another important issue here is to connect the VB to the proper voltage. This depends on the accuracy of leakage current, speed and availability of mentioned voltage. As mentioned before, for proper linear discharge of the capacitor which leads to linear voltage drop in node VS, one should choose Veff (MS2)
I.
INTRODUCTION
Lowering power dissipation in analog and mixed signal ICs is much more desired nowadays to improve the battery life in many portable systems such as PDAs and mobile phones. This comes along with many difficulties such as lowering power supply voltage, suspending circuits in different phases of the system and other improvements that will force analog and mixed-mode IC designers to challenge with more complex circuits. As power supply voltage decrease year by year, the use of low supply voltage current mirrors becomes inevitable. These current mirrors are one of the most fundamental parts in any analog and mixed-mode ICs since they are often used to bias critical parts such as OTAs (Operational Transconductance Amplifiers), and the most important of all, in bandgap voltage reference. It is more desired in such circuits to achieve higher signal swing to improve SNR of the overall system. This also comes along with using low voltage structures, challenging with more complex circuits. Power dissipation in suspend mode is as much important as in normal operation mode, since in many portable systems the time period of suspend mode might be much longer than the time period of normal operation mode. As shown in Fig. 1, a simple current mirror is used to generate voltage or current. Capacitor CB consists of gatesource capacitance of PMOS devices and also other capacitors which is used to fix the gate source voltage of the PMOS transistors and avoid current variations according to power supply voltage variations. If all transistors carry a zero
0-7803-8834-8/05/$20.00 ©2005 IEEE.
current while the supply is turned on or it is rising from suspend mode, they may remain off indefinitely because the loop can support a zero current in both branches. To overcome this problem we can add a diode connected transistor (M5) to provide a current path from VDD through M4 and M1 to ground upon start-up. Thus, M3 and M1, and hence M2 and M4 cannot remain off [1]. This technique might be useful when dealing with non-low voltage structures while has several disadvantages such as current leakage and low allowable voltage swing. Another widely used current mirror is shown in Fig. 2 [2]. Such a wide swing current mirror not only helps us with voltage swing, but also minimizes most of the detrimental second-order imperfections caused by the finite-output impedance of transistors. Transistors MPD1 and MPD2 are added for supporting suspend mode. As PD1 goes high, the gate voltage of these transistors will become low, connecting their drain to VDD, making zero gate-source voltage and forcing transistors to operate in deep sub-threshold region, or completely off. This operation will cause CB1 and CB2 to lose their charge completely since both sides of these capacitances are connected to VDD. While PD is changing from high to low, there is a high risk of zero current loops which may occur, for there is no single diode connected transistor in the current path. Because of this reason, use of startup circuit is inevitable. So a technique is used in [2] for starting-up operation as will be discussed later.
Figure 1. A Simple bias circuit with diode connected device as a start-up. 1
Power-Down (sometimes called reset) pin is an input pin which forces the system to be suspended.
4265
Once the loop starts up, MS2 will come on, sinking all of the current from MS1, pulling the gates of MS3 and MS4 low, and thereby turning them off so they no longer affect the bias loop [2]. In the event that all currents in the bias loop are zero, MS2 will be off. Since MS1 operates as a highimpedance load that is always on, the gate of MS3 and MS4 will be pulled high. These transistors will then inject currents into the bias loop, which will startup the circuit. Based on this concept, several start-up circuits were used to ensure the stability of the bias circuit, and most of them hit the bandgap circuit, since its proper operation is vital for other bias circuits [3] [4]. These Mentioned start-up circuits work properly in most cases, but have two main disadvantages. First, they all consist of a single branch which is always on, dissipating power even in suspend mode. This fact becomes even more critical as for more complex structures we might need more than one regenerating point. And second, the parasitic effects of start-up transistors might affect the proper operation of the circuit. Leakage current out of the start-up circuit directly affects bias currents. These shortcomings become much more important while working with more accurate devices such as bandgap voltage reference [3]. This paper presents a new start-up circuit with dynamic operation compatible with any bias circuit, especially the bandgap voltage reference with wide variety of power supplies. In Section (II) this new start-up circuit will be presented and a complete analytical model of its operation is given. In section (III) some simulation results are presented to prove the proper functionality of this start-up circuit and section (IV) concludes this paper. II.
NEW START-UP CIRCUIT WITH DYNAMIC OPERATION
Almost all analog and mixed-mode ICs use power-down pin to force their operation to halt, and a large proportion of them use Power-On-Reset circuitry to start-up the chip for the first time it is connected to power supply. The idea is to use both power-on-reset and PD to generate a small pulse to be used for starting up the circuit as shown in Fig.3. Complete analytical model of this circuit will be presented later in this section. This start-up circuit is shown in Fig. 4. As mentioned before, the input of this circuit consists of two independent parts, power down and power-on-reset, to support both operation modes.
Figure 3. Top view of start-up system.
When power-down or power-on-reset is high, MS1 will be turned on; so both bottom and top plate of CS will be connected to ground, making it lose all of its charge. At falling edge of PD, top plate of CS will be connected to VDD; so it will force the bottom plate to raise near VDD voltage either, therefore VS will rise instantly after PD falls. Transistor MS2 will discharge the capacitor CS in a few nanoseconds and this operation will create a pulse on the gate of transistors MD1-Dn, so they will sink a current from PMOS bias capacitances, decreasing their gate voltage, hence turning them on. Assuming VS has risen to VDD voltage at the same time that PD falls, we can write:
I Discharge = I MS 2 =
KS 2 (VB − VTHN ) 2 2
(1)
( L) .
where K i = µ n COX W
i
This constant current will discharge CS until VS drops below Veff(MS2). It is worth to mention that if we choose Veff(MS2) > VTHN, MS2 will enter triode region before MDi is turned off, so nonlinear discharging of CS will occur which might increase the pulse width. So the best option is to choose Veff (MS2) VTHP
lowering its drain currant. This will make the discharge transistors MD1-Dn to operate in sub-threshold region, sinking a small amount of current from bias circuit, creating a small leakage current. But voltage of VS2 will fall far below VTHN in a short period of time, so this leakage will become truly negligible, almost in order of few Pico-amperes. It is worth to mention that in the equations (9), for simplicity we have assumed that VB is connected to power supply voltage and also VS2 will rise to power supply voltage, while this might not occur since the capacitor CS might loose a fraction of its charge during the falling time of PD signal when MS1 is not completely off. One can overcome this problem by using a high speed buffer in PD signal path. Another important issue here is to connect the VB to the proper voltage. This depends on the accuracy of leakage current, speed and availability of mentioned voltage. As mentioned before, for proper linear discharge of the capacitor which leads to linear voltage drop in node VS, one should choose Veff (MS2)
