A CMOS Low-Noise Low-Power Quadrature LC ... - Semantic Scholar
A CMOS Low-Noise Low-Power Quadrature LC Oscillator Emad Ebrahimi and Sasan Naseh Electrical Engineering Group, Eng. Department, Ferdowsi University of Mashhad Mashhad, Iran E-mail: [email protected] Abstract— A new quadrature LC voltage-controlled oscillator circuit configuration for CMOS technology is presented. In the proposed circuit two identical cross-connected LC-VCOs are coupled together via the bulk of the cross-connected MOS transistors and the bulk of the MOS varactors. No additional components are needed for coupling the core oscillators. Therefore, no extra noise sources and power consumption are added to the circuit, which results in good phase noise and low power consumption. The circuit can operate with Vdd as low as 0.5 V. A linear analysis of the quadrature operation of the circuit is also provided. The same coupling scheme can be used for multiphase signal generation.
Figure 1. Schemaic of the P-QVCO in [6]. The solid and dashed arrows emphasize the "in-phase" and "anti-phase" connection, respectievely.
Index terms— Low-noise, low-power, low-voltage, quadrature LC voltage-controlled oscillators (LC-QVCO), multiphase.
I.
means via their common mode nodes [14−16], while in the second group also known as first-harmonic, differential nodes are used for coupling.
INTRODUCTION
Quadrature LC-VCOs are widely used in transceivers for wireless communications, and in half-rate clock and data recovery (CDR) circuits for wired communications [1−3]. Almost every I/Q based communication transceiver architecture operates based on quadrature signals for modulation, demodulation and image rejection [1].
The first QVCO of the second group, shown in Fig. 1 as in [6], is known as P-QVCO (P indicates that the coupling transistors Mcpl1-4 are in parallel with the cross-connected transistors M1-4) in which the first oscillator is connected to the second in an "in-phase" manner, and the second oscillator to the first, in an "anti-phase" manner.
Different techniques are available for generation of quadrature signals. Use of an RC-CR network as delayelement [1,4] has the disadvantage that it needs powerhungry buffers, and it has poor phase accuracy due to the tolerance of resistors. Utilization of an oscillator combined with master-slave flip-flops as a frequency divider [1] needs an oscillator with double the desired frequency which limits its use at high frequencies and also, its phase error is very sensitive to the input oscillator duty cycle. Another technique is to use quadrature ring oscillator, but it suffers from poor phase noise [5].
All the other QVCOs of this group presented afterward [7−13], have adopted the same "in-phase anti-phase" scheme of connection between the two core cross-connected LCVCOs. In [7] coupling transistors were placed in series with the cross-connected transistors, which resulted in a better phase noise and lower power consumption. However the stack of transistors limits the tuning range [17] and the output swing. Further improvements were made by replacing the coupling transistors with passive and less noisy devices (i.e. capacitors) [10,11]. In the QVCO in [10] the coupling of the two LC-VCOs were made via the bulk of the crossconnected transistors using capacitors as coupling devices. The QVCO in [11] uses capacitors as coupling means too, but it has the advantage of eliminating the need for separate wells for MOSFETs. In both QVCOs in [10,11], however, resistors were needed to provide the necessary DC bias for the bulk and gate of the transistors, respectively, which can degrade the phase noise due to the resistors' thermal noise. Also, the capacitors, while noiseless themselves, can introduce substrate noise via their bottom plates.
A widely used technique for quadrature signal generation is to couple two cross-connected LC-VCOs in a way that they operate in qudrature [6−16]. Due to their low phase noise and low power consumption, LC-QVCOs satisfy the strict requirements of the modern communication systems. They are categorized into two main groups. In one group known as superharmonic QVCOs, two identical crossconnected LC-VCOs are coupled to each other with different
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The QVCOs in [12,13] use on-chip inductors as coupling elements. Inductors, in addition to the large area they occupy, degrade phase noise due to their low quality factors. In all these works, coupling devices are components extra to the core VCOs, which inevitably introduce extra noise, extra power dissipation and larger chip area. Additionally, the mismatch in the coupling elements in these circuits can be a source of phase error. In this work, a new first-harmonic LC-QVCO is proposed in which no additional coupling components are required and thus, no extra noise and power consumption are introduced to the core oscillators. In Section II, the proposed QVCO circuit is explained in detail and a linear analysis of the quadrature operation of the circuit is presented. In Section III, simulation results are provided and compared with some previous works. Section IV provides a summary of the important results. II.
THE PROPOSED LC-QVCO
The proposed QVCO is shown in Fig. 2(a). Each of the four cross-connected transistors Msw1-4 is placed in a separate well, as their bulks need to be connected to different potentials. It is seen in Fig. 2(a) that no coupling devices extra to the two core LC-VCOs are used. The main idea of the proposed circuit is to use the bulk of the MOS varactors, as well as the bulk of the crossconnected transistors, to couple the core VCOs. The bulk of Mvar3 and Mvar4 are connected "in-phase" to the bulk of the Msw1 and Msw2, and the bulk of the Mvar1 and Mvar2 are connected in an "anti-phase" manner to the bulk of Msw3 and Msw4, respectively. Here the gate-bulk capacitances of the MOS varactors, and the gate-bulk and the bulk-drain capacitances of the cross-connected transistors (see Fig. 2(b)) play the role of the coupling devices between the two core VCOs and in this way, the need for any extra coupling elements is eliminated. It should be emphasized that while in strong inversion region of operation of a MOSFET the gatebulk capacitance is negligible, it does have a much larger value when the MOSFET is off [18]. Simulation results confirm that the varactor MOSFETs Mvar1-4 operate in off region for a large portion of each cycle, wherein the gatebulk capacitances are large enough that guaranties a strong coupling between the two core oscillators.
Figure 2. (a) Schematic of proposed QVCO (rL is ohmic losses of inductor). (b) Intrinsic capacitors of the MOS varactor and crossconnecred transistor that provide couppling.
considered ac ground):
j ω (V a −V )C bd −sw + j ω (V a +V )C gb −sw + j ωV aC bs −sw + j ωV a (C bd −var + C bs − var ) + j ω (V a −Ve j ϕ )C gb − var = 0
(1)
j ω (V c −Ve j ϕ )C bd −sw + j ω (V a +Ve j ϕ )C gb −sw + j ωV cC bs −sw + j ωV c (C bd −var + C bs −var ) + j ω (V c +V )C gb − var = 0
(2)
where Va and Vc are the voltages at the nodes a and c, and Cbd, Cbs and Cgb are intrinsic bulk-drain, bulk-source and gate-bulk capacitances of the transistors, respectively. Relations (1) and (2) can be rewritten as following:
j ωV a (C bd −sw + C gb −sw + C bs −sw + C bd − var + C bs − var + C gb − var ) =
To show that the outputs of the proposed circuit at nodes I+ and Q+ in Fig. 2(a) are in quadrature, a linear analysis of the circuit operation is presented in which it is assumed that all the voltages have sinusoidal waveform.
j ωV (C bd −sw − C gb −sw + (cos ϕ + j sin ϕ )C gb − var )
Because of the symmetry of the circuit, the oscillation amplitude at each of the 4 output nodes I+, I-, Q+ and Q- in Fig. 2(a) are the same, and there is 180o phase difference between I+ and I-, and also between Q+ and Q-. The potential at nodes I+ and Q+ are denoted in phasor domain with V and Vejϕ, respectively, in which ϕ is the phase difference between the potentials of I+ and Q+. The KCL for nodes a and c in Fig. 2 can be written as following (nodes x and y are
j ωV ((cos ϕ + j sin ϕ )(C bd −sw − C gb −sw ) − C gb − var )
(3)
j ωV c (C bd −sw + C gb −sw + C bs −sw + C bd − var + C bs − var + C gb − var ) = (4)
Due to symmetry of the proposed circuit, the amplitude of the voltage at the bulk of all transistors, i.e. voltages at nodes a, b, c and d, are the same. Therefore, |Va|=|Vc|, implying that the absolute value of the left side of (3) is equal to the absolute value of the left side of (4). Some
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TABLE I. PROPOSED QVCO PARAMETER VALUES FOR SIMULATION.
further manipulations of (3) and (4) results in the following:
(C bd −sw −C gb −sw + C gb −var cos ϕ )2 + (C gb −var sin ϕ )2 =
M1-4 Mvar1-4 L rL Rtune Vdd Vtune
(5)
(C gb −var + (C gb −sw −C bd −sw )cos ϕ )2 + ((C gb −sw −Cbd −sw )sin ϕ )2
3µm/0.18 µm 400µm/0.18 µm 2nH 2Ω 1KΩ 1.8 volt 0.85 volt
Solving (5) to obtain ϕ, leads to: 4((C −C )C )cosϕ = 0 bd − sw gb − sw gb − var
(6)
which results in:
ϕ = kπ +
π 2
k = 0,1, 2,...
(7)
meaning that outputs are in quadrature. It should be mentioned that although the above analysis was based on sinusoidal waveforms, simulation shows that for non-sinusoidal waveforms (resulted from a low quality factor LC tank, for example) the outputs are in quadrature as well. Simulation of the circuit for a wide range of variations of the circuit parameters generated quadrature outputs, which shows that the proposed QVCO is robust. III.
SIMULATION RESULTS AND COMPARISONS
In this section simulation results of the proposed QVCO are presented and compared with those of some previously reported QVCOs. Fig. 3 shows the output signals of the proposed QVCO simulated using a commercial 0.18µm CMOS technology. The total current drawn from a 1.8 volt power supply is 5.4 mA. The oscillation frequency of the QVCO can be changed from 4.3 to 4.7 GHz. The parameters used for simulation of the proposed QVCO are shown in Table I. The ohmic losses of the inductors are modeled with 1Ω series resistances per each nH of inductance [11] (indicated as rL in Fig. 2(a)). Fig. 4 shows a comparison of the phase-noise of the proposed QVCO with that of [6] and [10]. An improvement of about 15 dB and 5 dB compared with the QVCO of [6] and [10], respectively, is observed. For a more complete comparison, a figure of merit (FOM) such as the one proposed in [8] can be used: f FOM = PN ( Δ f ) − 20 log( osc ) + 10 log( PQV CO ) Δf
Figure 3. Simulated outputs of the proposed QVCO.
Simulation showed that different versions of the core VCOs, i.e. with their cross-connected transistors being NMOS-only, PMOS-only or complementary, and also VCOs with or without a tail current source, all can be used to implement QVCO using the proposed coupling method. It should also be noticed that using the P-type (N-type) for both cross-connected and varactor MOSFETs, makes it possible to use a single-well technology with P-type (N-type) substrate, and use of the more expensive more complicated triple-well technology is not essential for implementation of the proposed coupling method. A comparison of the simulated phase noise of the core VCO with that of the proposed QVCO (Δf=1MHz @fosc=4.5GHz) overall shows an improvement after coupling; a behavior in agreement with what reported in [19]. Simulation results for the tuning range of the different configurations of the proposed QVCO and their core VCOs are also shown in Table III (Vtune varies from 0 to 1.8 V with center frequency being 4.5GHz). For the core VCOs, the bulk of all PMOSFETs and NMOSFETS are connected to Vdd and ground, respectively. Simulation also showed that the same coupling method can also be used to generate multiphase signals by generalizing the "in-phase anti-phase" scheme of connection to several identical core VCOs [19]. IV.
(8)
where PN(Δf) is the phase noise at the offset frequency Δf in dBc/Hz, fosc is the centre frequency and PQVCO is the total power consumption in milliwatts. Table II shows FOM of some previous works and that of the proposed QVCO.
CONCLUSION
A well-known method of generation of quadrature and multiphase signals is to couple two or several identical LC VCOs via their differential nodes using the "in-phase antiphase" scheme of connection of VCOs. In all QVCOs presented previously there has been the need for some coupling elements such as transistors, capacitors or inductors, which naturally introduce extra noise sources or
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REFERENCES TABLE II.
FIGURE OF MERIT OF PREVIOUS WORKS AND PROPOSED QVCO.
CMOS QVCO
Technology [µm]
Frequency [GHz]
Power [mW]
[6]
1
0.9
30
[7]
0.25
1.8
20
[8]
0.35
1.8
50
[9]
0.18
6
6.8
[10]
0.18 Triple-well
1.1
5.4
This work
0.18 Triple-well
4.54
9.8
Phase-noise [dBc/Hz]
-85 [@100KHz] -143 [@3MHz] -140 [@3MHz] -106 [@3MHz] -120 [@1MHz] -125.3 [@1MHz]
[1] [2] [3]
FOM [dBc]
[4]
-149.31 -185.5
[5]
-178.5 -173.24
[6]
-173.5 -188.5
[7]
TABLE III. SIMULATED TUNING RANGE AND PHASE NOISE OF THE CORE VCO AND PROPOSED QVCO WITH DIFFERENT CONFIGURATIONS. Tuning range
Phase noise (dBc/Hz) Δf=1MHz Core QVCO VCO -119 -120.5
Crossconnected
MOS varactor
NMOS
NMOS
Core VCO 27%
NMOS
PMOS
13%
7%
-113
-125.3
PMOS
PMOS
8%
17%
-115
-120
Complementary
PMOS
25%
16%
-122
-122
QVCO 29%
[8]
[9]
[10]
[11] [12]
[13]
[14]
[15]
[16]
Figure 4. Phase noise simulation results of conventional, Kim's and proposed QVCOs. Agilent ADS simulator was used for simulations.
power consumption to the core VCOs. In this work a method of coupling of identical CMOS LC-VCOs was proposed in which VCOs were directly connected to each other via the bulk of the cross-connected transistors and MOS varactors. Therefore, no extra elements were needed for coupling, which led to a better phase noise and lower power consumption. The coupling elements in this method are the intrinsic bulk-gate capacitances of the MOS varactors and the bulk-gate and bulk-drain capacitances of the crossconnected transistors. A comparison of the performance of the proposed circuit with those of the previously reported QVCOs was presented. The same coupling scheme can be used for multiphase signal generation as well.
[17]
[18] [19]
B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River NJ, 1998. T. S. Rappaport, Wireless Communications, Prentice-Hall Inc., 1996. J. Savoj and B. Razavi, High-speed CMOS circuits for optical receivers , Kluwer Academic Publishers, 2001. J. Crols and M. S. J. Steyaert, “A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology,” IEEE J. Solid-State Circuits, vol. 30, pp. 1483–1492, Dec. 1995. H. Matsuoka and T. Tsukahara, “A 5-GHz frequency-doubling quadrature modulator with a ring-type local oscillator,” IEEE J. Solid-State Circuits, vol. 34, pp. 1345–1348, Sept. 1999. A. Rofougaran et al., “A single-chip 900-MHz spread-spectrum wireless transceiver in 1-µm CMOS-Part I: Architecture and transmitted design,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 515-534, Apr. 1998. A. Andreani, A. Bonfanti, L. Romano and C. Samori, “Analysis and design of 1.8GHz CMOS LC quadrature oscillator,” IEEE J. SolidState Circuits, Vol. 37, No. 12, pp.1737-1747, December 2002. M. Tiebout, “Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS,” IEEE J. Solid-State Circuits, vol. 36, pp. 1018–1024, July 2001. H. Shin, Z. Xu, and M. F. Chang, “A1.8V6/9 GHz switchable dualband quadrature LC VCO in SiGe BiCMOS technology,” Radio FrequencyIntegrated Circuits (RFIC) Symp. Dig., 2002, pp. 71–74. H. R. Kim, C. Y. Cha, S. M. Oh, M. S. Yang and S. G. Lee, “A very low-power quadrature VCO with back gated coupling,” IEEE J. Solid-State Circuits, Vol. 39, No. 6, pp.952-955, June 2004. M. Zarre Dooghabadi and Sasan Naseh, “A New Quadrature LCOscillator,” ISCAS 2007, pp. 1701-1703, May 2007. Alan, W. L., & Luong, H. C., “A 1V 17 GHz 5mW quadrature CMOS VCO based on transformer coupling,” IEEE International Conference Digest of Technical Papers, pp. 711–720, February 2006. Y. H. Chuang, S. H. Lee, R. H. Yen, S. L. Jang and M. H. Juang, “ A Low-Voltage Quadrature CMOS VCO Based on Voltage-Voltage Feedback Topology,” IEEE Microwave and Wireless Components letters, Vol. 16, No. 12, pp. 696-698, December 2006. C. C. Meng, Y. W. Chang, and S. C. Tseng, “4.9-GHz low-phasenoise transformer-based superharmonic-coupled GaInP/GaAs HBT QVCO,” IEEE Microwave and Wireless Component Letters, vol. 16,no. 6, pp. 339-341, June 2006. J. Cabanillas, L. Dussopt, J. Lopez-Villegas, and G. Rebeiz, “A 900MHz low phase noise CMOS quadrature oscillator,” IEEE Radio Frequency Integrated Circuits Symposium, 2002. S. Gierkink, S. Levantino, R. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1148-1154, July 2003. Owen Casha , Ivan Grech , Joseph Micallef, “Comparative study of gigahertz CMOS LC quadrature voltage-controlled oscillators with relevance to phase noise, ” Analog Integrated Circuits and Signal Processing, vol.52 no.1-2, pp.1-14, August 2007. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed., Mc-Graw-Hill, 1999. J. Kim and B. Kim, “A Low-Phase-Noise CMOS LC Oscillator with a Ring Structure,” ISSCC 2000, pp. 430–431, 2000.
Simulation showed that this QVCO can operate with supply voltage as low as 0.5 V.
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Figure 1. Schemaic of the P-QVCO in [6]. The solid and dashed arrows emphasize the "in-phase" and "anti-phase" connection, respectievely.
Index terms— Low-noise, low-power, low-voltage, quadrature LC voltage-controlled oscillators (LC-QVCO), multiphase.
I.
means via their common mode nodes [14−16], while in the second group also known as first-harmonic, differential nodes are used for coupling.
INTRODUCTION
Quadrature LC-VCOs are widely used in transceivers for wireless communications, and in half-rate clock and data recovery (CDR) circuits for wired communications [1−3]. Almost every I/Q based communication transceiver architecture operates based on quadrature signals for modulation, demodulation and image rejection [1].
The first QVCO of the second group, shown in Fig. 1 as in [6], is known as P-QVCO (P indicates that the coupling transistors Mcpl1-4 are in parallel with the cross-connected transistors M1-4) in which the first oscillator is connected to the second in an "in-phase" manner, and the second oscillator to the first, in an "anti-phase" manner.
Different techniques are available for generation of quadrature signals. Use of an RC-CR network as delayelement [1,4] has the disadvantage that it needs powerhungry buffers, and it has poor phase accuracy due to the tolerance of resistors. Utilization of an oscillator combined with master-slave flip-flops as a frequency divider [1] needs an oscillator with double the desired frequency which limits its use at high frequencies and also, its phase error is very sensitive to the input oscillator duty cycle. Another technique is to use quadrature ring oscillator, but it suffers from poor phase noise [5].
All the other QVCOs of this group presented afterward [7−13], have adopted the same "in-phase anti-phase" scheme of connection between the two core cross-connected LCVCOs. In [7] coupling transistors were placed in series with the cross-connected transistors, which resulted in a better phase noise and lower power consumption. However the stack of transistors limits the tuning range [17] and the output swing. Further improvements were made by replacing the coupling transistors with passive and less noisy devices (i.e. capacitors) [10,11]. In the QVCO in [10] the coupling of the two LC-VCOs were made via the bulk of the crossconnected transistors using capacitors as coupling devices. The QVCO in [11] uses capacitors as coupling means too, but it has the advantage of eliminating the need for separate wells for MOSFETs. In both QVCOs in [10,11], however, resistors were needed to provide the necessary DC bias for the bulk and gate of the transistors, respectively, which can degrade the phase noise due to the resistors' thermal noise. Also, the capacitors, while noiseless themselves, can introduce substrate noise via their bottom plates.
A widely used technique for quadrature signal generation is to couple two cross-connected LC-VCOs in a way that they operate in qudrature [6−16]. Due to their low phase noise and low power consumption, LC-QVCOs satisfy the strict requirements of the modern communication systems. They are categorized into two main groups. In one group known as superharmonic QVCOs, two identical crossconnected LC-VCOs are coupled to each other with different
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The QVCOs in [12,13] use on-chip inductors as coupling elements. Inductors, in addition to the large area they occupy, degrade phase noise due to their low quality factors. In all these works, coupling devices are components extra to the core VCOs, which inevitably introduce extra noise, extra power dissipation and larger chip area. Additionally, the mismatch in the coupling elements in these circuits can be a source of phase error. In this work, a new first-harmonic LC-QVCO is proposed in which no additional coupling components are required and thus, no extra noise and power consumption are introduced to the core oscillators. In Section II, the proposed QVCO circuit is explained in detail and a linear analysis of the quadrature operation of the circuit is presented. In Section III, simulation results are provided and compared with some previous works. Section IV provides a summary of the important results. II.
THE PROPOSED LC-QVCO
The proposed QVCO is shown in Fig. 2(a). Each of the four cross-connected transistors Msw1-4 is placed in a separate well, as their bulks need to be connected to different potentials. It is seen in Fig. 2(a) that no coupling devices extra to the two core LC-VCOs are used. The main idea of the proposed circuit is to use the bulk of the MOS varactors, as well as the bulk of the crossconnected transistors, to couple the core VCOs. The bulk of Mvar3 and Mvar4 are connected "in-phase" to the bulk of the Msw1 and Msw2, and the bulk of the Mvar1 and Mvar2 are connected in an "anti-phase" manner to the bulk of Msw3 and Msw4, respectively. Here the gate-bulk capacitances of the MOS varactors, and the gate-bulk and the bulk-drain capacitances of the cross-connected transistors (see Fig. 2(b)) play the role of the coupling devices between the two core VCOs and in this way, the need for any extra coupling elements is eliminated. It should be emphasized that while in strong inversion region of operation of a MOSFET the gatebulk capacitance is negligible, it does have a much larger value when the MOSFET is off [18]. Simulation results confirm that the varactor MOSFETs Mvar1-4 operate in off region for a large portion of each cycle, wherein the gatebulk capacitances are large enough that guaranties a strong coupling between the two core oscillators.
Figure 2. (a) Schematic of proposed QVCO (rL is ohmic losses of inductor). (b) Intrinsic capacitors of the MOS varactor and crossconnecred transistor that provide couppling.
considered ac ground):
j ω (V a −V )C bd −sw + j ω (V a +V )C gb −sw + j ωV aC bs −sw + j ωV a (C bd −var + C bs − var ) + j ω (V a −Ve j ϕ )C gb − var = 0
(1)
j ω (V c −Ve j ϕ )C bd −sw + j ω (V a +Ve j ϕ )C gb −sw + j ωV cC bs −sw + j ωV c (C bd −var + C bs −var ) + j ω (V c +V )C gb − var = 0
(2)
where Va and Vc are the voltages at the nodes a and c, and Cbd, Cbs and Cgb are intrinsic bulk-drain, bulk-source and gate-bulk capacitances of the transistors, respectively. Relations (1) and (2) can be rewritten as following:
j ωV a (C bd −sw + C gb −sw + C bs −sw + C bd − var + C bs − var + C gb − var ) =
To show that the outputs of the proposed circuit at nodes I+ and Q+ in Fig. 2(a) are in quadrature, a linear analysis of the circuit operation is presented in which it is assumed that all the voltages have sinusoidal waveform.
j ωV (C bd −sw − C gb −sw + (cos ϕ + j sin ϕ )C gb − var )
Because of the symmetry of the circuit, the oscillation amplitude at each of the 4 output nodes I+, I-, Q+ and Q- in Fig. 2(a) are the same, and there is 180o phase difference between I+ and I-, and also between Q+ and Q-. The potential at nodes I+ and Q+ are denoted in phasor domain with V and Vejϕ, respectively, in which ϕ is the phase difference between the potentials of I+ and Q+. The KCL for nodes a and c in Fig. 2 can be written as following (nodes x and y are
j ωV ((cos ϕ + j sin ϕ )(C bd −sw − C gb −sw ) − C gb − var )
(3)
j ωV c (C bd −sw + C gb −sw + C bs −sw + C bd − var + C bs − var + C gb − var ) = (4)
Due to symmetry of the proposed circuit, the amplitude of the voltage at the bulk of all transistors, i.e. voltages at nodes a, b, c and d, are the same. Therefore, |Va|=|Vc|, implying that the absolute value of the left side of (3) is equal to the absolute value of the left side of (4). Some
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TABLE I. PROPOSED QVCO PARAMETER VALUES FOR SIMULATION.
further manipulations of (3) and (4) results in the following:
(C bd −sw −C gb −sw + C gb −var cos ϕ )2 + (C gb −var sin ϕ )2 =
M1-4 Mvar1-4 L rL Rtune Vdd Vtune
(5)
(C gb −var + (C gb −sw −C bd −sw )cos ϕ )2 + ((C gb −sw −Cbd −sw )sin ϕ )2
3µm/0.18 µm 400µm/0.18 µm 2nH 2Ω 1KΩ 1.8 volt 0.85 volt
Solving (5) to obtain ϕ, leads to: 4((C −C )C )cosϕ = 0 bd − sw gb − sw gb − var
(6)
which results in:
ϕ = kπ +
π 2
k = 0,1, 2,...
(7)
meaning that outputs are in quadrature. It should be mentioned that although the above analysis was based on sinusoidal waveforms, simulation shows that for non-sinusoidal waveforms (resulted from a low quality factor LC tank, for example) the outputs are in quadrature as well. Simulation of the circuit for a wide range of variations of the circuit parameters generated quadrature outputs, which shows that the proposed QVCO is robust. III.
SIMULATION RESULTS AND COMPARISONS
In this section simulation results of the proposed QVCO are presented and compared with those of some previously reported QVCOs. Fig. 3 shows the output signals of the proposed QVCO simulated using a commercial 0.18µm CMOS technology. The total current drawn from a 1.8 volt power supply is 5.4 mA. The oscillation frequency of the QVCO can be changed from 4.3 to 4.7 GHz. The parameters used for simulation of the proposed QVCO are shown in Table I. The ohmic losses of the inductors are modeled with 1Ω series resistances per each nH of inductance [11] (indicated as rL in Fig. 2(a)). Fig. 4 shows a comparison of the phase-noise of the proposed QVCO with that of [6] and [10]. An improvement of about 15 dB and 5 dB compared with the QVCO of [6] and [10], respectively, is observed. For a more complete comparison, a figure of merit (FOM) such as the one proposed in [8] can be used: f FOM = PN ( Δ f ) − 20 log( osc ) + 10 log( PQV CO ) Δf
Figure 3. Simulated outputs of the proposed QVCO.
Simulation showed that different versions of the core VCOs, i.e. with their cross-connected transistors being NMOS-only, PMOS-only or complementary, and also VCOs with or without a tail current source, all can be used to implement QVCO using the proposed coupling method. It should also be noticed that using the P-type (N-type) for both cross-connected and varactor MOSFETs, makes it possible to use a single-well technology with P-type (N-type) substrate, and use of the more expensive more complicated triple-well technology is not essential for implementation of the proposed coupling method. A comparison of the simulated phase noise of the core VCO with that of the proposed QVCO (Δf=1MHz @fosc=4.5GHz) overall shows an improvement after coupling; a behavior in agreement with what reported in [19]. Simulation results for the tuning range of the different configurations of the proposed QVCO and their core VCOs are also shown in Table III (Vtune varies from 0 to 1.8 V with center frequency being 4.5GHz). For the core VCOs, the bulk of all PMOSFETs and NMOSFETS are connected to Vdd and ground, respectively. Simulation also showed that the same coupling method can also be used to generate multiphase signals by generalizing the "in-phase anti-phase" scheme of connection to several identical core VCOs [19]. IV.
(8)
where PN(Δf) is the phase noise at the offset frequency Δf in dBc/Hz, fosc is the centre frequency and PQVCO is the total power consumption in milliwatts. Table II shows FOM of some previous works and that of the proposed QVCO.
CONCLUSION
A well-known method of generation of quadrature and multiphase signals is to couple two or several identical LC VCOs via their differential nodes using the "in-phase antiphase" scheme of connection of VCOs. In all QVCOs presented previously there has been the need for some coupling elements such as transistors, capacitors or inductors, which naturally introduce extra noise sources or
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REFERENCES TABLE II.
FIGURE OF MERIT OF PREVIOUS WORKS AND PROPOSED QVCO.
CMOS QVCO
Technology [µm]
Frequency [GHz]
Power [mW]
[6]
1
0.9
30
[7]
0.25
1.8
20
[8]
0.35
1.8
50
[9]
0.18
6
6.8
[10]
0.18 Triple-well
1.1
5.4
This work
0.18 Triple-well
4.54
9.8
Phase-noise [dBc/Hz]
-85 [@100KHz] -143 [@3MHz] -140 [@3MHz] -106 [@3MHz] -120 [@1MHz] -125.3 [@1MHz]
[1] [2] [3]
FOM [dBc]
[4]
-149.31 -185.5
[5]
-178.5 -173.24
[6]
-173.5 -188.5
[7]
TABLE III. SIMULATED TUNING RANGE AND PHASE NOISE OF THE CORE VCO AND PROPOSED QVCO WITH DIFFERENT CONFIGURATIONS. Tuning range
Phase noise (dBc/Hz) Δf=1MHz Core QVCO VCO -119 -120.5
Crossconnected
MOS varactor
NMOS
NMOS
Core VCO 27%
NMOS
PMOS
13%
7%
-113
-125.3
PMOS
PMOS
8%
17%
-115
-120
Complementary
PMOS
25%
16%
-122
-122
QVCO 29%
[8]
[9]
[10]
[11] [12]
[13]
[14]
[15]
[16]
Figure 4. Phase noise simulation results of conventional, Kim's and proposed QVCOs. Agilent ADS simulator was used for simulations.
power consumption to the core VCOs. In this work a method of coupling of identical CMOS LC-VCOs was proposed in which VCOs were directly connected to each other via the bulk of the cross-connected transistors and MOS varactors. Therefore, no extra elements were needed for coupling, which led to a better phase noise and lower power consumption. The coupling elements in this method are the intrinsic bulk-gate capacitances of the MOS varactors and the bulk-gate and bulk-drain capacitances of the crossconnected transistors. A comparison of the performance of the proposed circuit with those of the previously reported QVCOs was presented. The same coupling scheme can be used for multiphase signal generation as well.
[17]
[18] [19]
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Simulation showed that this QVCO can operate with supply voltage as low as 0.5 V.
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